From ddae41f2e4dad5eb6ebc3dd67cc9ea0a5b12dbdf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 12 Apr 2015 15:21:58 +0200 Subject: [PATCH] liteeth/phy/mii: simplify LiteEthPHYMIITX using Converter --- misoclib/com/liteeth/common.py | 1 + misoclib/com/liteeth/phy/mii.py | 43 +++++++++++---------------------- 2 files changed, 15 insertions(+), 29 deletions(-) diff --git a/misoclib/com/liteeth/common.py b/misoclib/com/liteeth/common.py index 59e958b2..7a0b88bc 100644 --- a/misoclib/com/liteeth/common.py +++ b/misoclib/com/liteeth/common.py @@ -139,6 +139,7 @@ def _remove_from_layout(layout, *args): if not remove: r.append(f) return r + def eth_phy_description(dw): payload_layout = [ ("data", dw), diff --git a/misoclib/com/liteeth/phy/mii.py b/misoclib/com/liteeth/phy/mii.py index f42768fe..e77bc544 100644 --- a/misoclib/com/liteeth/phy/mii.py +++ b/misoclib/com/liteeth/phy/mii.py @@ -1,44 +1,29 @@ from misoclib.com.liteeth.common import * from misoclib.com.liteeth.generic import * +def converter_description(dw): + payload_layout = [("data", dw)] + return EndpointDescription(payload_layout, packetized=True) + class LiteEthPHYMIITX(Module): def __init__(self, pads): self.sink = sink = Sink(eth_phy_description(8)) ### if hasattr(pads, "tx_er"): self.sync += pads.tx_er.eq(0) - tx_en_r = Signal() - tx_data_r = Signal(4) + converter = Converter(converter_description(8), converter_description(4)) + self.submodules += converter + self.comb += [ + converter.sink.stb.eq(sink.stb), + converter.sink.data.eq(sink.data), + sink.ack.eq(converter.sink.ack), + converter.source.ack.eq(1) + ] self.sync += [ - pads.tx_en.eq(tx_en_r), - pads.tx_data.eq(tx_data_r) + pads.tx_en.eq(converter.source.stb), + pads.tx_data.eq(converter.source.data) ] - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - fsm.act("IDLE", - sink.ack.eq(1), - If(sink.stb & sink.sop, - sink.ack.eq(0), - NextState("SEND_LO") - ) - ) - fsm.act("SEND_LO", - tx_data_r.eq(sink.data[0:4]), - tx_en_r.eq(1), - NextState("SEND_HI") - ) - fsm.act("SEND_HI", - tx_data_r.eq(sink.data[4:8]), - tx_en_r.eq(1), - sink.ack.eq(1), - If(sink.stb & sink.eop, - NextState("IDLE") - ).Else( - NextState("SEND_LO") - ) - ) - class LiteEthPHYMIIRX(Module): def __init__(self, pads): self.source = source = Source(eth_phy_description(8)) -- 2.30.2