From ddb900d814670be1bf67594307cec2d4cff2e055 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Wed, 21 Jul 2021 19:57:55 +0200 Subject: [PATCH] update pi_dcbz function --- src/soc/config/test/test_pi2ls.py | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py index 2c4b89cc..4bdd1184 100644 --- a/src/soc/config/test/test_pi2ls.py +++ b/src/soc/config/test/test_pi2ls.py @@ -67,14 +67,13 @@ def pi_st(port1, addr, data, datalen, msr_pr=0): yield from wait_busy(port1, True) # wait while busy # copy of pi_st -def pi_dcbz(port1, addr, data, datalen, msr_pr=0): +def pi_dcbz(port1, addr, msr_pr=0): # have to wait until not busy yield from wait_busy(port1, no=False,debug="busy") # wait until not busy # set up a ST on the port. address first: yield port1.is_st_i.eq(1) # indicate ST - yield port1.data_len.eq(datalen) # ST length (1/2/4/8) yield port1.msr_pr.eq(msr_pr) # MSR PR bit (1==>virt, 0==>real) yield port1.is_dcbz.eq(1) # set dcbz @@ -82,14 +81,18 @@ def pi_dcbz(port1, addr, data, datalen, msr_pr=0): yield port1.addr.data.eq(addr) # set address yield port1.addr.ok.eq(1) # set ok yield Settle() - yield from wait_addr(port1,debug="addr") # wait until addr ok - # yield # not needed, just for checking - # yield # not needed, just for checking - # assert "ST" for one cycle (required by the API) - yield port1.st.data.eq(data) + + # guess: this is not needed + # yield from wait_addr(port1,debug="addr") # wait until addr ok + + # just write some dummy data -- remove + print("dummy write begin") + yield port1.st.data.eq(0) yield port1.st.ok.eq(1) yield yield port1.st.ok.eq(0) + print("dummy write end") + yield from wait_busy(port1, no=True, debug="not_busy") # wait while busy # can go straight to reset. -- 2.30.2