From dde610f718c890e29419f1bdbf2f9f2e428866f9 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Wed, 13 May 2020 15:54:55 -0400 Subject: [PATCH] Add support for OP_EXTS --- src/soc/alu/main_stage.py | 11 +++++++++++ src/soc/alu/test/test_pipe_caller.py | 10 ++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py index b2851015..1231aeae 100644 --- a/src/soc/alu/main_stage.py +++ b/src/soc/alu/main_stage.py @@ -61,6 +61,17 @@ class ALUMainStage(PipeModBase): #### xor #### with m.Case(InternalOp.OP_XOR): comb += self.o.o.eq(self.i.a ^ self.i.b) + with m.Case(InternalOp.OP_EXTS): + with m.If(self.i.ctx.op.data_len == 1): + comb += self.o.o.eq(Cat(self.i.a[0:8], + Repl(self.i.a[7], 64-8))) + with m.If(self.i.ctx.op.data_len == 2): + comb += self.o.o.eq(Cat(self.i.a[0:16], + Repl(self.i.a[15], 64-16))) + with m.If(self.i.ctx.op.data_len == 4): + comb += self.o.o.eq(Cat(self.i.a[0:32], + Repl(self.i.a[31], 64-32))) + ###### sticky overflow and context, both pass-through ##### diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py index ad1ae63a..604b5af2 100644 --- a/src/soc/alu/test/test_pipe_caller.py +++ b/src/soc/alu/test/test_pipe_caller.py @@ -151,6 +151,16 @@ class ALUTestCase(FHDLTestCase): initial_regs[7] = random.randint(0, (1<<64)-1) self.run_tst_program(Program(lst), initial_regs, {}) + def test_extsb(self): + insns = ["extsb", "extsh", "extsw"] + for i in range(10): + choice = random.choice(insns) + lst = [f"{choice} 3, 1"] + print(lst) + initial_regs = [0] * 32 + initial_regs[1] = random.randint(0, (1<<64)-1) + self.run_tst_program(Program(lst), initial_regs) + def test_ilang(self): rec = CompALUOpSubset() -- 2.30.2