From dde9447363fbecf5871f246b429f2b558e6682cb Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Thu, 27 Apr 2023 15:14:47 +0000 Subject: [PATCH] microwatt_tutorial: Fix formatting --- HDL_workflow/microwatt_tutorial.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/HDL_workflow/microwatt_tutorial.mdwn b/HDL_workflow/microwatt_tutorial.mdwn index e43f3d7e7..03cb94bcd 100644 --- a/HDL_workflow/microwatt_tutorial.mdwn +++ b/HDL_workflow/microwatt_tutorial.mdwn @@ -27,8 +27,9 @@ Make sure verilator binaries in $PATH: (GHDLSYNTH needs to be redefined because the Makefile has default `ghdl.so`, but somewhere else '.so' gets appended. You may see the following error if you -don't redefine: `ERROR: Can't load module `./ghdl.so': -/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`) +don't redefine: +`ERROR: Can't load module +./ghdl.so':/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`) To run the Verilator simulation, set verilator as the target: -- 2.30.2