From ddebd445e7a2fa57570384607fae042508a43aa9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 6 Sep 2020 19:43:40 +0100 Subject: [PATCH] add reset option to Register --- src/soc/regfile/regfile.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py index 10b3fa06..30063726 100644 --- a/src/soc/regfile/regfile.py +++ b/src/soc/regfile/regfile.py @@ -32,8 +32,9 @@ import operator class Register(Elaboratable): - def __init__(self, width, writethru=True, synced=True): + def __init__(self, width, writethru=True, synced=True, resetval=0): self.width = width + self.reset = resetval self.writethru = writethru self.synced = synced self._rdports = [] @@ -55,7 +56,7 @@ class Register(Elaboratable): def elaborate(self, platform): m = Module() - self.reg = reg = Signal(self.width, name="reg") + self.reg = reg = Signal(self.width, name="reg", reset=self.reset) if self.synced: domain = m.d.sync -- 2.30.2