From de07786df4aedbafaf742ab21ec04d0bbe0e55cd Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 21 Dec 2020 03:45:39 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 3bbdfabfc..8c5fafd79 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -593,7 +593,9 @@ but select different *bits* of the same CRs `offs` is defined as CR48 (6x8) so as to mesh cleanly with Vectorised Rc=1 operations (see below). Arithmetic Rc=1 operations start from CR16 (TBD); FP Rc=1 from CR32 (TBD). -# Twin Predication +# Appendix + +## Twin Predication This is a novel concept that allows predication to be applied to a single source and a single dest register. The following types of traditional @@ -624,8 +626,6 @@ Additional unusual capabilities of Twin Predication include a back-to-back version of VCOMPRESS-VEXPAND which is effectively the ability to do an ordered multiple VINSERT. -# Appendix - ## CR Operations CRs are slightly more involved than INT or FP registers due to the -- 2.30.2