From de103f942c8fe5f284e41125f17759e242762924 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 22 Jun 2023 19:58:04 -0700 Subject: [PATCH] use the CSV "CR out" column to compute which mode to use for Rc=1 this works much better than trying to bodge it by checking if the instruction name meets some pattern --- src/openpower/decoder/isa/caller.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index b5688c92..8ad794c5 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -2255,8 +2255,9 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): return True, vli_ def do_rc_ov(self, ins_name, result, overflow, cr0, cr1, output_names): - if ins_name.startswith("f") and "RT" not in output_names: - rc_reg = "CR1" # not calculated correctly yet for FP compares + cr_out = yield self.dec2.op.cr_out + if cr_out == CROutSel.CR1.value: + rc_reg = "CR1" else: rc_reg = "CR0" regnum, is_vec = yield from get_cr_out(self.dec2, rc_reg) -- 2.30.2