From de1d81511af7a5ca362c334635190609c45e998b Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 17 Dec 2016 12:01:22 +0800 Subject: [PATCH] greenpak4: Updated GP_DCMP cell model --- techlibs/greenpak4/cells_sim.v | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 0f1eaf8fb..27c5ff054 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -136,8 +136,26 @@ module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT); endmodule -module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg OUTP, output reg OUTN); - //TODO finish implementing +module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL); + parameter PWRDN_SYNC = 1'b0; + parameter CLK_EDGE = "RISING"; + parameter GREATER_OR_EQUAL = 1'b0; + + //TODO implement power-down mode + + initial GREATER = 0; + initial EQUAL = 0; + + wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK; + always @(posedge clk_minv) begin + if(GREATER_OR_EQUAL) + GREATER <= (INP >= INN); + else + GREATER <= (INP > INN); + + EQUAL <= (INP == INN); + end + endmodule module GP_DCMPREF(output reg[7:0]OUT); -- 2.30.2