From de34a44a21c86dc7f5b73aa00e43a17de5a4abd5 Mon Sep 17 00:00:00 2001 From: programmerjake Date: Wed, 16 Feb 2022 00:56:43 +0000 Subject: [PATCH] add tables for 8-wide fetch/decode --- ...of-more-decode-stages-on-reg-renaming.mdwn | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/openpower/openpower/sv/effect-of-more-decode-stages-on-reg-renaming.mdwn b/openpower/openpower/sv/effect-of-more-decode-stages-on-reg-renaming.mdwn index b7b823d11..85cf1dc2f 100644 --- a/openpower/openpower/sv/effect-of-more-decode-stages-on-reg-renaming.mdwn +++ b/openpower/openpower/sv/effect-of-more-decode-stages-on-reg-renaming.mdwn @@ -2,6 +2,8 @@ there's basically no effect except execution starts a few cycles later. no additional execution resources are needed, notice the exact same number of renamed hardware registers are used. +# 5 decode stages, 4 wide + | Cycle | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | |----------------------------|-----|-------|----------|----------|----------|----------|----------|------------------------------|------------------------------|-------------------------------|--------------------------------|---------------------------------|---------------------------------|---------------------------------|--------------------------------|--------------------|-------------------------|--------------------------------|--------------------------------|------------------|-------------------------|-----------------------|----------------|--------|-----| | 0x100: mtctr r4 | | Fetch | Decode 0 | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Renamed: mtctr h2 \<- h1 | Read Inputs: h1 | Write Outputs: h2 | Retire | | | | | | | | | | | | | | | @@ -30,6 +32,8 @@ there's basically no effect except execution starts a few cycles later. no addit | 0x10c: std r9, 0(r3) | | | | | | | | Fetch | Decode 0 | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Renamed: std h25, 0(h24) | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25 | Read Inputs: h25, h24 | Write Outputs: | Retire | | | 0x110: bdnz .L2 | | | | | | | | Fetch | Decode 0 | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Renamed: bdnz h26 \<- h22, .L2 | Read Inputs: h22 | Write Outputs: h26 | Wait: Retire | Wait: Retire | Wait: Retire | Wait: Retire | Wait: Retire | Wait: Retire | Wait: Retire | Retire | | +# 1 decode stage, 4 wide + | Cycle | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | |----------------------------|-----|-------|----------|------------------------------|------------------------------|-------------------------------|--------------------------------|---------------------------------|---------------------------------|---------------------------------|--------------------------------|--------------------|-------------------------|--------------------------------|--------------------------------|------------------|-------------------------|-----------------------|----------------|--------|-----|-----|-----|-----|-----| | 0x100: mtctr r4 | | Fetch | Decode 0 | Renamed: mtctr h2 \<- h1 | Read Inputs: h1 | Write Outputs: h2 | Retire | | | | | | | | | | | | | | | | | | | @@ -57,3 +61,63 @@ there's basically no effect except execution starts a few cycles later. no addit | 0x108: addi r9 \<- r9, 100 | | | | | | | | Fetch | Decode 0 | Renamed: addi h25 \<- h23, 100 | Wait: h23 | Wait: h23 | Wait: h23 | Wait: h23 | Wait: h23 | Wait: h23 | Read Inputs: h23 | Write Outputs: h25 | Retire | | | | | | | | 0x10c: std r9, 0(r3) | | | | | | | | Fetch | Decode 0 | Renamed: std h25, 0(h24) | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25 | Read Inputs: h25, h24 | Write Outputs: | Retire | | | | | | | 0x110: bdnz .L2 | | | | | | | | Fetch | Decode 0 | Renamed: bdnz h26 \<- h22, .L2 | Read Inputs: h22 | Write Outputs: h26 | Wait: Retire | Wait: Retire | Wait: Retire | Wait: Retire | Wait: Retire | Wait: Retire | Wait: Retire | Retire | | | | | | + +# 8 decode stages, 8 wide + +| Cycle | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | +|----------------------------|-----|-------|----------|----------|----------|----------|----------|----------|----------|----------|------------------------------|--------------------------------|---------------------------------|---------------------------------|-------------------------|-------------------------|-------------------------|-------------------------|-----------------------|----------------|--------|-----|-----|-----|-----| +| 0x100: mtctr r4 | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: mtctr h2 \<- h1 | Read Inputs: h1 | Write Outputs: h2 | Retire | | | | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: ldu h3, 8(h0 -> h4) | Read Inputs: h0 | Write Outputs: h3, h4 | Retire | | | | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: addi h5 \<- h3, 100 | Wait: h3 | Read Inputs: h3 | Write Outputs: h5 | Retire | | | | | | | | | | | +| 0x10c: std r9, 0(r3) | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: std h5, 0(h4) | Wait: h5, h4 | Wait: h5 | Read Inputs: h5, h4 | Write Outputs: | Retire | | | | | | | | | | +| 0x110: bdnz .L2 | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: bdnz h6 \<- h2, .L2 | Wait: h2 | Read Inputs: h2 | Write Outputs: h6 | Wait: Retire | Retire | | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: ldu h7, 8(h4 -> h8) | Wait: h4 | Read Inputs: h4 | Write Outputs: h7, h8 | Wait: Retire | Retire | | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: addi h9 \<- h7, 100 | Wait: h7 | Wait: h7 | Read Inputs: h7 | Write Outputs: h9 | Retire | | | | | | | | | | +| 0x10c: std r9, 0(r3) | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: std h9, 0(h8) | Wait: h9, h8 | Wait: h9, h8 | Wait: h9 | Read Inputs: h9, h8 | Write Outputs: | Retire | | | | | | | | | +| 0x110: bdnz .L2 | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: bdnz h10 \<- h6, .L2 | Wait: h6 | Read Inputs: h6 | Write Outputs: h10 | Wait: Retire | Retire | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: ldu h11, 8(h8 -> h12) | Wait: h8 | Read Inputs: h8 | Write Outputs: h11, h12 | Wait: Retire | Retire | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: addi h13 \<- h11, 100 | Wait: h11 | Wait: h11 | Read Inputs: h11 | Write Outputs: h13 | Retire | | | | | | | | | +| 0x10c: std r9, 0(r3) | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: std h13, 0(h12) | Wait: h13, h12 | Wait: h13, h12 | Wait: h13 | Read Inputs: h13, h12 | Write Outputs: | Retire | | | | | | | | +| 0x110: bdnz .L2 | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: bdnz h14 \<- h10, .L2 | Wait: h10 | Wait: h10 | Read Inputs: h10 | Write Outputs: h14 | Wait: Retire | Retire | | | | | | | | +| 0x104: ldu r9, 8(r3) | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: ldu h15, 8(h12 -> h16) | Wait: h12 | Read Inputs: h12 | Write Outputs: h15, h16 | Wait: Retire | Retire | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: addi h17 \<- h15, 100 | Wait: h15 | Wait: h15 | Read Inputs: h15 | Write Outputs: h17 | Retire | | | | | | | | +| 0x10c: std r9, 0(r3) | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: std h17, 0(h16) | Wait: h17, h16 | Wait: h17, h16 | Wait: h17 | Read Inputs: h17, h16 | Write Outputs: | Retire | | | | | | | +| 0x110: bdnz .L2 | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: bdnz h18 \<- h14, .L2 | Wait: h14 | Wait: h14 | Read Inputs: h14 | Write Outputs: h18 | Wait: Retire | Retire | | | | | | | +| 0x104: ldu r9, 8(r3) | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: ldu h19, 8(h16 -> h20) | Wait: h16 | Wait: h16 | Read Inputs: h16 | Write Outputs: h19, h20 | Wait: Retire | Retire | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: addi h21 \<- h19, 100 | Wait: h19 | Wait: h19 | Wait: h19 | Read Inputs: h19 | Write Outputs: h21 | Retire | | | | | | | +| 0x10c: std r9, 0(r3) | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: std h21, 0(h20) | Wait: h21, h20 | Wait: h21, h20 | Wait: h21, h20 | Wait: h21 | Read Inputs: h21, h20 | Write Outputs: | Retire | | | | | | +| 0x110: bdnz .L2 | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: bdnz h22 \<- h18, .L2 | Wait: h18 | Wait: h18 | Wait: h18 | Read Inputs: h18 | Write Outputs: h22 | Wait: Retire | Retire | | | | | | +| 0x104: ldu r9, 8(r3) | | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: ldu h23, 8(h20 -> h24) | Wait: h20 | Wait: h20 | Read Inputs: h20 | Write Outputs: h23, h24 | Wait: Retire | Retire | | | | | | +| 0x108: addi r9 \<- r9, 100 | | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: addi h25 \<- h23, 100 | Wait: h23 | Wait: h23 | Wait: h23 | Read Inputs: h23 | Write Outputs: h25 | Retire | | | | | | +| 0x10c: std r9, 0(r3) | | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: std h25, 0(h24) | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25 | Read Inputs: h25, h24 | Write Outputs: | Retire | | | | | +| 0x110: bdnz .L2 | | | | | Fetch | Decode 1 | Decode 2 | Decode 3 | Decode 4 | Decode 5 | Decode 6 | Decode 7 | Decode 8 | Renamed: bdnz h26 \<- h22, .L2 | Wait: h22 | Wait: h22 | Wait: h22 | Read Inputs: h22 | Write Outputs: h26 | Wait: Retire | Retire | | | | | + +# 1 decode stage, 8 wide + +| Cycle | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | +|----------------------------|-----|-------|----------|------------------------------|--------------------------------|---------------------------------|---------------------------------|-------------------------|-------------------------|-------------------------|-------------------------|-----------------------|----------------|--------|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +| 0x100: mtctr r4 | | Fetch | Decode 1 | Renamed: mtctr h2 \<- h1 | Read Inputs: h1 | Write Outputs: h2 | Retire | | | | | | | | | | | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | Fetch | Decode 1 | Renamed: ldu h3, 8(h0 -> h4) | Read Inputs: h0 | Write Outputs: h3, h4 | Retire | | | | | | | | | | | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | Fetch | Decode 1 | Renamed: addi h5 \<- h3, 100 | Wait: h3 | Read Inputs: h3 | Write Outputs: h5 | Retire | | | | | | | | | | | | | | | | | | +| 0x10c: std r9, 0(r3) | | Fetch | Decode 1 | Renamed: std h5, 0(h4) | Wait: h5, h4 | Wait: h5 | Read Inputs: h5, h4 | Write Outputs: | Retire | | | | | | | | | | | | | | | | | +| 0x110: bdnz .L2 | | Fetch | Decode 1 | Renamed: bdnz h6 \<- h2, .L2 | Wait: h2 | Read Inputs: h2 | Write Outputs: h6 | Wait: Retire | Retire | | | | | | | | | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | Fetch | Decode 1 | Renamed: ldu h7, 8(h4 -> h8) | Wait: h4 | Read Inputs: h4 | Write Outputs: h7, h8 | Wait: Retire | Retire | | | | | | | | | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | Fetch | Decode 1 | Renamed: addi h9 \<- h7, 100 | Wait: h7 | Wait: h7 | Read Inputs: h7 | Write Outputs: h9 | Retire | | | | | | | | | | | | | | | | | +| 0x10c: std r9, 0(r3) | | Fetch | Decode 1 | Renamed: std h9, 0(h8) | Wait: h9, h8 | Wait: h9, h8 | Wait: h9 | Read Inputs: h9, h8 | Write Outputs: | Retire | | | | | | | | | | | | | | | | +| 0x110: bdnz .L2 | | | Fetch | Decode 1 | Renamed: bdnz h10 \<- h6, .L2 | Wait: h6 | Read Inputs: h6 | Write Outputs: h10 | Wait: Retire | Retire | | | | | | | | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | | Fetch | Decode 1 | Renamed: ldu h11, 8(h8 -> h12) | Wait: h8 | Read Inputs: h8 | Write Outputs: h11, h12 | Wait: Retire | Retire | | | | | | | | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | | Fetch | Decode 1 | Renamed: addi h13 \<- h11, 100 | Wait: h11 | Wait: h11 | Read Inputs: h11 | Write Outputs: h13 | Retire | | | | | | | | | | | | | | | | +| 0x10c: std r9, 0(r3) | | | Fetch | Decode 1 | Renamed: std h13, 0(h12) | Wait: h13, h12 | Wait: h13, h12 | Wait: h13 | Read Inputs: h13, h12 | Write Outputs: | Retire | | | | | | | | | | | | | | | +| 0x110: bdnz .L2 | | | Fetch | Decode 1 | Renamed: bdnz h14 \<- h10, .L2 | Wait: h10 | Wait: h10 | Read Inputs: h10 | Write Outputs: h14 | Wait: Retire | Retire | | | | | | | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | | | Fetch | Decode 1 | Renamed: ldu h15, 8(h12 -> h16) | Wait: h12 | Read Inputs: h12 | Write Outputs: h15, h16 | Wait: Retire | Retire | | | | | | | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | | | Fetch | Decode 1 | Renamed: addi h17 \<- h15, 100 | Wait: h15 | Wait: h15 | Read Inputs: h15 | Write Outputs: h17 | Retire | | | | | | | | | | | | | | | +| 0x10c: std r9, 0(r3) | | | | Fetch | Decode 1 | Renamed: std h17, 0(h16) | Wait: h17, h16 | Wait: h17, h16 | Wait: h17 | Read Inputs: h17, h16 | Write Outputs: | Retire | | | | | | | | | | | | | | +| 0x110: bdnz .L2 | | | | Fetch | Decode 1 | Renamed: bdnz h18 \<- h14, .L2 | Wait: h14 | Wait: h14 | Read Inputs: h14 | Write Outputs: h18 | Wait: Retire | Retire | | | | | | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | | | Fetch | Decode 1 | Renamed: ldu h19, 8(h16 -> h20) | Wait: h16 | Wait: h16 | Read Inputs: h16 | Write Outputs: h19, h20 | Wait: Retire | Retire | | | | | | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | | | Fetch | Decode 1 | Renamed: addi h21 \<- h19, 100 | Wait: h19 | Wait: h19 | Wait: h19 | Read Inputs: h19 | Write Outputs: h21 | Retire | | | | | | | | | | | | | | +| 0x10c: std r9, 0(r3) | | | | Fetch | Decode 1 | Renamed: std h21, 0(h20) | Wait: h21, h20 | Wait: h21, h20 | Wait: h21, h20 | Wait: h21 | Read Inputs: h21, h20 | Write Outputs: | Retire | | | | | | | | | | | | | +| 0x110: bdnz .L2 | | | | Fetch | Decode 1 | Renamed: bdnz h22 \<- h18, .L2 | Wait: h18 | Wait: h18 | Wait: h18 | Read Inputs: h18 | Write Outputs: h22 | Wait: Retire | Retire | | | | | | | | | | | | | +| 0x104: ldu r9, 8(r3) | | | | | Fetch | Decode 1 | Renamed: ldu h23, 8(h20 -> h24) | Wait: h20 | Wait: h20 | Read Inputs: h20 | Write Outputs: h23, h24 | Wait: Retire | Retire | | | | | | | | | | | | | +| 0x108: addi r9 \<- r9, 100 | | | | | Fetch | Decode 1 | Renamed: addi h25 \<- h23, 100 | Wait: h23 | Wait: h23 | Wait: h23 | Read Inputs: h23 | Write Outputs: h25 | Retire | | | | | | | | | | | | | +| 0x10c: std r9, 0(r3) | | | | | Fetch | Decode 1 | Renamed: std h25, 0(h24) | Wait: h25, h24 | Wait: h25, h24 | Wait: h25, h24 | Wait: h25 | Read Inputs: h25, h24 | Write Outputs: | Retire | | | | | | | | | | | | +| 0x110: bdnz .L2 | | | | | Fetch | Decode 1 | Renamed: bdnz h26 \<- h22, .L2 | Wait: h22 | Wait: h22 | Wait: h22 | Read Inputs: h22 | Write Outputs: h26 | Wait: Retire | Retire | | | | | | | | | | | | -- 2.30.2