From de6e2485dff057322f6686ddeba6458b63a47159 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Wed, 13 May 2020 18:44:49 -0400 Subject: [PATCH] Fix bug in rotator preventing use of 64 bit rlcl/r --- src/soc/shift_rot/main_stage.py | 14 +++++++++++--- src/soc/shift_rot/rotator.py | 10 +++++----- src/soc/shift_rot/test/test_pipe_caller.py | 14 +++++++++++++- 3 files changed, 29 insertions(+), 9 deletions(-) diff --git a/src/soc/shift_rot/main_stage.py b/src/soc/shift_rot/main_stage.py index a4fdf8c4..e0a1a150 100644 --- a/src/soc/shift_rot/main_stage.py +++ b/src/soc/shift_rot/main_stage.py @@ -36,17 +36,17 @@ class ShiftRotMainStage(PipeModBase): md_fields = self.fields.instrs['MD'] mb = Signal(m_fields['MB'][0:-1].shape()) me = Signal(m_fields['ME'][0:-1].shape()) - XO = Signal(md_fields['XO'][0:-1].shape()) + mb_extra = Signal(1) comb += mb.eq(m_fields['MB'][0:-1]) comb += me.eq(m_fields['ME'][0:-1]) - comb += XO.eq(md_fields['XO'][0:-1]) + comb += mb_extra.eq(md_fields['mb'][0:-1][0]) # set up microwatt rotator module m.submodules.rotator = rotator = Rotator() comb += [ rotator.me.eq(me), rotator.mb.eq(mb), - rotator.XO.eq(XO), + rotator.mb_extra.eq(mb_extra), rotator.rs.eq(self.i.rs), rotator.ra.eq(self.i.ra), rotator.shift.eq(self.i.rb), @@ -68,6 +68,14 @@ class ShiftRotMainStage(PipeModBase): comb += [rotator.right_shift.eq(0), rotator.clear_left.eq(1), rotator.clear_right.eq(1)] + with m.Case(InternalOp.OP_RLCL): + comb += [rotator.right_shift.eq(0), + rotator.clear_left.eq(1), + rotator.clear_right.eq(0)] + with m.Case(InternalOp.OP_RLCR): + comb += [rotator.right_shift.eq(0), + rotator.clear_left.eq(0), + rotator.clear_right.eq(1)] # outputs from the microwatt rotator module comb += [self.o.o.eq(rotator.result_o), diff --git a/src/soc/shift_rot/rotator.py b/src/soc/shift_rot/rotator.py index 035afa47..b695a4e1 100644 --- a/src/soc/shift_rot/rotator.py +++ b/src/soc/shift_rot/rotator.py @@ -38,9 +38,9 @@ class Rotator(Elaboratable): """ def __init__(self): # input - self.me = Signal(5, reset_less=True) # ME field - self.mb = Signal(5, reset_less=True) # MB field - self.XO = Signal(1, reset_less=True) # XO field + self.me = Signal(5, reset_less=True) # ME field + self.mb = Signal(5, reset_less=True) # MB field + self.mb_extra = Signal(1, reset_less=True) # NOT XO field, extra bit of mb in MD-form self.ra = Signal(64, reset_less=True) # RA self.rs = Signal(64, reset_less=True) # RS self.ra = Signal(64, reset_less=True) # RA @@ -103,7 +103,7 @@ class Rotator(Elaboratable): with m.If(self.is_32bit): comb += mb.eq(Cat(self.mb, Const(0b01, 2))) with m.Else(): - comb += mb.eq(Cat(self.mb, self.XO, Const(0b0, 1))) + comb += mb.eq(Cat(self.mb, self.mb_extra, Const(0b0, 1))) with m.Elif(self.right_shift): # this is basically mb = sh + (is_32bit? 32: 0); with m.If(self.is_32bit): @@ -119,7 +119,7 @@ class Rotator(Elaboratable): comb += me.eq(Cat(self.me, Const(0b01, 2))) with m.Elif(self.clear_right & ~self.clear_left): # this is me, have to use fields - comb += me.eq(Cat(self.mb, self.XO, Const(0b0, 1))) + comb += me.eq(Cat(self.mb, self.mb_extra, Const(0b0, 1))) with m.Else(): # effectively, 63 - sh comb += me.eq(Cat(~self.shift[0:6], self.shift[6])) diff --git a/src/soc/shift_rot/test/test_pipe_caller.py b/src/soc/shift_rot/test/test_pipe_caller.py index 888de74c..6eae89a6 100644 --- a/src/soc/shift_rot/test/test_pipe_caller.py +++ b/src/soc/shift_rot/test/test_pipe_caller.py @@ -153,7 +153,19 @@ class ALUTestCase(FHDLTestCase): initial_regs[1] = random.randint(0, (1<<64)-1) initial_regs[2] = random.randint(0, 63) self.run_tst_program(Program(lst), initial_regs) - + + def test_rldicl(self): + lst = ["rldicl 3, 1, 5, 20"] + initial_regs = [0] * 32 + initial_regs[1] = random.randint(0, (1<<64)-1) + self.run_tst_program(Program(lst), initial_regs) + + def test_rldicr(self): + lst = ["rldicr 3, 1, 5, 20"] + initial_regs = [0] * 32 + initial_regs[1] = random.randint(0, (1<<64)-1) + self.run_tst_program(Program(lst), initial_regs) + def test_ilang(self): rec = CompALUOpSubset() -- 2.30.2