From de84d2ecc92acc9526e0c255b39bd59f26254d42 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 23 Nov 2021 12:03:19 +0000 Subject: [PATCH] use fascinating trick of defaultdict-of-defaultdicts --- src/soc/simple/core.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 9f3a1141..83670420 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -40,7 +40,7 @@ from soc.config.test.test_loadstore import TestMemPspec from openpower.decoder.power_enums import MicrOp, Function from soc.simple.core_data import CoreInput, CoreOutput -from collections import defaultdict +from collections import defaultdict, namedtuple import operator from nmutil.util import rising_edge @@ -873,9 +873,9 @@ class NonProductionCore(ControlBase): fus = self.fus.fus e = self.ireg.e # decoded instruction to execute - # dictionary of dictionaries of lists of regfile ports. + # dictionary of dictionaries of lists/tuples of regfile ports. # first key: regfile. second key: regfile port name - byregfiles = defaultdict(dict) + byregfiles = defaultdict(lambda: defaultdict(list)) byregfiles_spec = defaultdict(dict) for (funame, fu) in fus.items(): @@ -912,8 +912,6 @@ class NonProductionCore(ControlBase): byregfiles_spec[regfile][regname] = \ (rdflag, wrport, read, write, wid, []) # here we start to create "lanes" - if idx not in byregfiles[regfile]: - byregfiles[regfile][idx] = [] fuspec = (funame, fu, idx) byregfiles[regfile][idx].append(fuspec) byregfiles_spec[regfile][regname][5].append(fuspec) -- 2.30.2