From de89e133d8a3f92d9f2f99d0d8bcca50e9da6cb4 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Tue, 18 Jun 2013 16:10:21 +0200 Subject: [PATCH] x86: Fix the flag handling code in FABS and FCHS This changeset fixes two problems in the FABS and FCHS implementation. First, the ISA parser expects the assignment in flag_code to be a pure assignment and not an and-assignment, which leads to the isa_parser omitting the misc reg update. Second, the FCHS and FABS macro-ops don't set the SetStatus flag, which means that the default micro-op version, which doesn't update FSW, is executed. --- src/arch/x86/isa/insts/x87/arithmetic/change_sign.py | 4 ++-- src/arch/x86/isa/microops/fpop.isa | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py index 779f1b5b2..207b8a0b0 100644 --- a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py +++ b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py @@ -38,10 +38,10 @@ microcode = ''' def macroop FABS { - absfp st(0), st(0) + absfp st(0), st(0), SetStatus=True }; def macroop FCHS { - chsfp st(0), st(0) + chsfp st(0), st(0), SetStatus=True }; ''' diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index abb6abb72..e6372ba6b 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -365,9 +365,9 @@ let {{ class absfp(FpUnaryOp): code = 'FpDestReg = fabs(FpSrcReg1);' - flag_code = 'FSW &= (~CC1Bit);' + flag_code = 'FSW = FSW & (~CC1Bit);' class chsfp(FpUnaryOp): code = 'FpDestReg = (-1) * (FpSrcReg1);' - flag_code = 'FSW &= (~CC1Bit);' + flag_code = 'FSW = FSW & (~CC1Bit);' }}; -- 2.30.2