From de8a67d3ed9126ad46e8b92b03158b4f22677ab7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 14:50:33 +0100 Subject: [PATCH] correct link --- simple_v_extension/specification.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 5f3dd51ce..df52287e7 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -512,7 +512,7 @@ be applied to integer registers; 0 indicates that it is relevant to floating-point registers. The 8 bit format is used for a much more compact expression. "isvec" -is implicit and, similar to [[sv-prefix-proposal]], the target vector +is implicit and, similar to [[sv_prefix_proposal]], the target vector is "regnum<<2", implicitly. Contrast this with the 16-bit format where the target vector is *explicitly* named in bits 8 to 14, and bit 15 may optionally set "scalar" mode. -- 2.30.2