From dea7acdb3e0357e580bc4e15e3346177b58d7ee0 Mon Sep 17 00:00:00 2001 From: Lena Olson Date: Mon, 13 Apr 2015 17:33:57 -0500 Subject: [PATCH] ruby: allow restoring from checkpoint when using DRAMCtrl Restoring from a checkpoint with ruby + the DRAMCtrl memory model was not working, because ruby and DRAMCtrl disagreed on the current tick during warmup. Since there is no reason to do timing requests during warmup, use functional requests instead. Committed by: Nilay Vaish --- .../ruby/slicc_interface/AbstractController.cc | 17 ++++++++++++++++- .../ruby/slicc_interface/AbstractController.hh | 3 +++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index a1d6ab83e..4290c63fa 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -40,7 +40,8 @@ AbstractController::AbstractController(const Params *p) m_transitions_per_cycle(p->transitions_per_cycle), m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), memoryPort(csprintf("%s.memory", name()), this, ""), - m_responseFromMemory_ptr(new MessageBuffer()) + m_responseFromMemory_ptr(new MessageBuffer()), + m_rubySystem(p->ruby_system) { // Set the sender pointer of the response message buffer from the // memory controller. @@ -217,6 +218,13 @@ AbstractController::queueMemoryRead(const MachineID &id, Address addr, SenderState *s = new SenderState(id); pkt->pushSenderState(s); + // Use functional rather than timing accesses during warmup + if (m_rubySystem->m_warmup_enabled) { + memoryPort.sendFunctional(pkt); + recvTimingResp(pkt); + return; + } + memoryPort.schedTimingReq(pkt, clockEdge(latency)); } @@ -237,6 +245,13 @@ AbstractController::queueMemoryWrite(const MachineID &id, Address addr, SenderState *s = new SenderState(id); pkt->pushSenderState(s); + // Use functional rather than timing accesses during warmup + if (m_rubySystem->m_warmup_enabled) { + memoryPort.sendFunctional(pkt); + recvTimingResp(pkt); + return; + } + // Create a block and copy data from the block. memoryPort.schedTimingReq(pkt, clockEdge(latency)); } diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index f8970fb59..01859397a 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -205,6 +205,9 @@ class AbstractController : public MemObject, public Consumer // memory controller. MessageBuffer *m_responseFromMemory_ptr; + // Needed so we know if we are warming up + RubySystem *m_rubySystem; + // State that is stored in packets sent to the memory controller. struct SenderState : public Packet::SenderState { -- 2.30.2