From dea80df0999ae0bad56e79af2a88a30be38bb8e4 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 18 Mar 2014 19:39:41 +0000 Subject: [PATCH] Power: Correct little-endian e500v2 GPR frame offsets This change corrects GPR frame offset calculation for the e500v2 processor. On this target, featuring the SPE APU, GPRs are 64-bit and are held in stack frames whole with the use of `evstdd' and `evldd' instructions. Their integer 32-bit part occupies the low-order word and therefore its offset varies between the two endiannesses possible. * rs6000-tdep.c (rs6000_frame_cache): Correct little-endian GPR offset into SPE pseudo registers. --- gdb/ChangeLog | 5 +++++ gdb/rs6000-tdep.c | 6 ++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 1c689378c9a..4f486e9e74a 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2014-03-18 Maciej W. Rozycki + + * rs6000-tdep.c (rs6000_frame_cache): Correct little-endian GPR + offset into SPE pseudo registers. + 2014-03-18 Pedro Alves PR gdb/13860 diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index bec06c7db89..dbe3aa24506 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -3257,12 +3257,14 @@ rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) { int i; CORE_ADDR ev_addr = cache->base + fdata.ev_offset; + CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0); + for (i = fdata.saved_ev; i < ppc_num_gprs; i++) { cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; - cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; + cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off; ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); - } + } } } -- 2.30.2