From ded769c98cffe5682c0211dba08abc4a1efe3d5a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 12 Jul 2013 01:15:37 +0200 Subject: [PATCH] Fixed sign handling in ternary operator --- frontends/ast/genrtlil.cc | 4 ++-- tests/simple/vloghammer.v | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 791ee9867..a9574254d 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1007,8 +1007,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = std::max(val1.width, val2.width); is_signed = children[1]->is_signed && children[2]->is_signed; - val1.extend(width); - val2.extend(width); + val1.extend(width, is_signed); + val2.extend(width, is_signed); return mux2rtlil(this, cond, val1, val2); } diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index eb0e15d02..c97a2be50 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -57,3 +57,11 @@ module test08(a, b, y); assign y = a == ($signed(b) >>> 1); endmodule +module test09(a, b, c, y); + input a; + input signed [1:0] b; + input signed [2:0] c; + output [3:0] y; + assign y = a ? b : c; +endmodule + -- 2.30.2