From dedcea923d45923ed680a4b131d378bdf1e93fab Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 8 May 2022 16:45:42 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 015fcc2cd..a70389608 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -34,9 +34,10 @@ this task, and what, in Computer Science, actually needs solving? First hints are that whilst memory bitcells have not increased in speed since the 90s (around 150 mhz), increasing the bank width, striping, and -datapath widths and speeds to the same has allowed -significant apparent speed increases: 3200 mhz DDR4 and even faster DDR5, -and other advanced Memory interfaces such as HBM, Gen-Z, and OpenCAPI, +datapath widths and speeds to the same has, with significant relative +latency penalties, allowed +apparent speed increases: 3200 mhz DDR4 and even faster DDR5, +and other advanced Memory interfaces such as HBM, Gen-Z, and OpenCAPI's OMI, all make an effort (all simply increasing the parallel deployment of the underlying 150 mhz bitcells), but these efforts are dwarfed by the two nearly three orders of magnitude increase in CPU horsepower -- 2.30.2