From deebc49ab09411db558aef288ad9cbb63a3853b8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 9 Apr 2020 23:04:29 +0200 Subject: [PATCH] boards/platforms: cosmetic cleanups. --- litex/boards/platforms/arty.py | 98 ++--- litex/boards/platforms/avalanche.py | 34 +- litex/boards/platforms/de0nano.py | 73 ++-- litex/boards/platforms/genesys2.py | 38 +- litex/boards/platforms/icebreaker.py | 6 +- litex/boards/platforms/kc705.py | 565 +++++++++++++------------ litex/boards/platforms/kcu105.py | 526 +++++++++++------------ litex/boards/platforms/machxo3.py | 2 +- litex/boards/platforms/minispartan6.py | 63 ++- litex/boards/platforms/netv2.py | 85 ++-- litex/boards/platforms/nexys4ddr.py | 47 +- litex/boards/platforms/nexys_video.py | 232 +++++----- litex/boards/platforms/tinyfpga_bx.py | 12 +- litex/boards/platforms/ulx3s.py | 3 +- litex/boards/platforms/versa_ecp5.py | 81 ++-- 15 files changed, 948 insertions(+), 917 deletions(-) diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py index c996cff2..1e2d8743 100644 --- a/litex/boards/platforms/arty.py +++ b/litex/boards/platforms/arty.py @@ -8,9 +8,9 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ - ("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")), - ("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")), - ("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")), + ("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")), ("rgb_led", 0, @@ -41,7 +41,7 @@ _io = [ IOStandard("LVCMOS33"), ), - ("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")), + ("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")), ("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")), ("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")), ("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")), @@ -62,7 +62,7 @@ _io = [ ), ("spi", 0, - Subsignal("clk", Pins("F1")), + Subsignal("clk", Pins("F1")), Subsignal("cs_n", Pins("C1")), Subsignal("mosi", Pins("H1")), Subsignal("miso", Pins("G1")), @@ -79,16 +79,16 @@ _io = [ ("spiflash4x", 0, Subsignal("cs_n", Pins("L13")), - Subsignal("clk", Pins("L16")), - Subsignal("dq", Pins("K17", "K18", "L14", "M14")), + Subsignal("clk", Pins("L16")), + Subsignal("dq", Pins("K17", "K18", "L14", "M14")), IOStandard("LVCMOS33") ), ("spiflash", 0, Subsignal("cs_n", Pins("L13")), - Subsignal("clk", Pins("L16")), + Subsignal("clk", Pins("L16")), Subsignal("mosi", Pins("K17")), Subsignal("miso", Pins("K18")), - Subsignal("wp", Pins("L14")), + Subsignal("wp", Pins("L14")), Subsignal("hold", Pins("M14")), IOStandard("LVCMOS33"), ), @@ -98,11 +98,11 @@ _io = [ "R2 M6 N4 T1 N6 R7 V6 U7", "R8 V7 R6 U6 T6 T8"), IOStandard("SSTL135")), - Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL135")), + Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL135")), Subsignal("ras_n", Pins("P3"), IOStandard("SSTL135")), Subsignal("cas_n", Pins("M4"), IOStandard("SSTL135")), - Subsignal("we_n", Pins("P5"), IOStandard("SSTL135")), - Subsignal("cs_n", Pins("U8"), IOStandard("SSTL135")), + Subsignal("we_n", Pins("P5"), IOStandard("SSTL135")), + Subsignal("cs_n", Pins("U8"), IOStandard("SSTL135")), Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL135")), Subsignal("dq", Pins( "K5 L3 K3 L6 M3 M1 L4 M2", @@ -117,8 +117,8 @@ _io = [ Misc("IN_TERM=UNTUNED_SPLIT_40")), Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")), Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")), - Subsignal("cke", Pins("N5"), IOStandard("SSTL135")), - Subsignal("odt", Pins("R5"), IOStandard("SSTL135")), + Subsignal("cke", Pins("N5"), IOStandard("SSTL135")), + Subsignal("odt", Pins("R5"), IOStandard("SSTL135")), Subsignal("reset_n", Pins("K6"), IOStandard("SSTL135")), Misc("SLEW=FAST"), ), @@ -130,16 +130,16 @@ _io = [ IOStandard("LVCMOS33"), ), ("eth", 0, - Subsignal("rst_n", Pins("C16")), - Subsignal("mdio", Pins("K13")), - Subsignal("mdc", Pins("F16")), - Subsignal("rx_dv", Pins("G16")), - Subsignal("rx_er", Pins("C17")), + Subsignal("rst_n", Pins("C16")), + Subsignal("mdio", Pins("K13")), + Subsignal("mdc", Pins("F16")), + Subsignal("rx_dv", Pins("G16")), + Subsignal("rx_er", Pins("C17")), Subsignal("rx_data", Pins("D18 E17 E18 G17")), - Subsignal("tx_en", Pins("H15")), + Subsignal("tx_en", Pins("H15")), Subsignal("tx_data", Pins("H14 J14 J13 H17")), - Subsignal("col", Pins("D17")), - Subsignal("crs", Pins("G14")), + Subsignal("col", Pins("D17")), + Subsignal("crs", Pins("G14")), IOStandard("LVCMOS33"), ), ] @@ -153,16 +153,16 @@ _connectors = [ ("pmodd", "D4 D3 F4 F3 E2 D2 H2 G2"), ("ck_io", { # Outer Digital Header - "ck_io0" : "V15", - "ck_io1" : "U16", - "ck_io2" : "P14", - "ck_io3" : "T11", - "ck_io4" : "R12", - "ck_io5" : "T14", - "ck_io6" : "T15", - "ck_io7" : "T16", - "ck_io8" : "N15", - "ck_io9" : "M16", + "ck_io0" : "V15", + "ck_io1" : "U16", + "ck_io2" : "P14", + "ck_io3" : "T11", + "ck_io4" : "R12", + "ck_io5" : "T14", + "ck_io6" : "T15", + "ck_io7" : "T16", + "ck_io8" : "N15", + "ck_io9" : "M16", "ck_io10" : "V17", "ck_io11" : "U18", "ck_io12" : "R17", @@ -204,18 +204,18 @@ _connectors = [ } ), ("XADC", { # Outer Analog Header - "vaux4_n" : "C5", - "vaux4_p" : "C6", - "vaux5_n" : "A5", - "vaux5_p" : "A6", - "vaux6_n" : "B4", - "vaux6_p" : "C4", - "vaux7_n" : "A1", - "vaux7_p" : "B1", + "vaux4_n" : "C5", + "vaux4_p" : "C6", + "vaux5_n" : "A5", + "vaux5_p" : "A6", + "vaux6_n" : "B4", + "vaux6_p" : "C4", + "vaux7_n" : "A1", + "vaux7_p" : "B1", "vaux15_n" : "B2", "vaux15_p" : "B3", - "vaux0_n" : "C14", - "vaux0_p" : "D14", + "vaux0_n" : "C14", + "vaux0_p" : "D14", # Inner Analog Header "vaux12_n" : "B7", @@ -226,12 +226,12 @@ _connectors = [ "vaux14_p" : "A3", # Power Measurements - "vsnsuv_n" : "B17", - "vsnsuv_p" : "B16", - "vsns5v0_n" : "B12", - "vsns5v0_p" : "C12", - "isns5v0_n" : "F14", - "isns5v0_n" : "F13", + "vsnsuv_n" : "B17", + "vsnsuv_p" : "B16", + "vsns5v0_n" : "B12", + "vsns5v0_p" : "C12", + "isns5v0_n" : "F14", + "isns5v0_n" : "F13", "isns0v95_n" : "A16", "isns0v95_n" : "A15", } ), @@ -240,7 +240,7 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk100" + default_clk_name = "clk100" default_clk_period = 1e9/100e6 def __init__(self, variant="a7-35"): diff --git a/litex/boards/platforms/avalanche.py b/litex/boards/platforms/avalanche.py index c14b2a58..5de18cde 100644 --- a/litex/boards/platforms/avalanche.py +++ b/litex/boards/platforms/avalanche.py @@ -27,41 +27,41 @@ _io = [ ), ("spiflash4x", 0, - Subsignal("clk", Pins("J1")), + Subsignal("clk", Pins("J1")), Subsignal("cs_n", Pins("H1")), - Subsignal("dq", Pins("F2 F1 M7 M8")), + Subsignal("dq", Pins("F2 F1 M7 M8")), IOStandard("LVCMOS25") ), ("spiflash", 0, - Subsignal("clk", Pins("J1")), + Subsignal("clk", Pins("J1")), Subsignal("cs_n", Pins("H1")), Subsignal("mosi", Pins("F2")), Subsignal("miso", Pins("F1")), - Subsignal("wp", Pins("M7")), + Subsignal("wp", Pins("M7")), Subsignal("hold", Pins("M8")), IOStandard("LVCMOS25"), ), ("ddram", 0, Subsignal("a", Pins( - "U5 U4 V4 W3 V5 W4 Y3 AA3", + "U5 U4 V4 W3 V5 W4 Y3 AA3", "Y4 Y5 AA2 AB2 V6 W6 AB3"), IOStandard("SSTL15II")), - Subsignal("ba", Pins("V7 Y6 U7"), IOStandard("SSTL15II")), + Subsignal("ba", Pins("V7 Y6 U7"), IOStandard("SSTL15II")), Subsignal("ras_n", Pins("AA6"), IOStandard("SSTL15II")), Subsignal("cas_n", Pins("AA5"), IOStandard("SSTL15II")), - Subsignal("we_n", Pins("AB5"), IOStandard("SSTL15II")), - Subsignal("cs_n", Pins("W7"), IOStandard("SSTL15II")), + Subsignal("we_n", Pins("AB5"), IOStandard("SSTL15II")), + Subsignal("cs_n", Pins("W7"), IOStandard("SSTL15II")), Subsignal("dm", Pins("Y9 R15"), IOStandard("SSTL15II")), Subsignal("dq", Pins( - "T7 T8 U8 U9 R10 V9 V10 W9", + "T7 T8 U8 U9 R10 V9 V10 W9", "V14 U14 R12 T11 U15 T13 U13 T15"), IOStandard("SSTL15II")), Subsignal("dqs_p", Pins("T10 R13"), IOStandard("SSTL15II")), Subsignal("dqs_n", Pins("U10 T12"), IOStandard("SSTL15II")), Subsignal("clk_p", Pins("V2"), IOStandard("SSTL15II")), Subsignal("clk_n", Pins("W2"), IOStandard("SSTL15II")), - Subsignal("cke", Pins("W8"), IOStandard("SSTL15II")), + Subsignal("cke", Pins("W8"), IOStandard("SSTL15II")), Subsignal("odt", Pins("AA7"), IOStandard("SSTL15II")), Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15II")), ), @@ -72,13 +72,13 @@ _io = [ IOStandard("LVCMOS25") ), ("eth", 0, - Subsignal("rst_n", Pins("L8"), IOStandard("LVCMOS33")), - Subsignal("int_n", Pins("J4")), - Subsignal("mdio", Pins("H2")), - Subsignal("mdc", Pins("J2")), - Subsignal("rx_ctl", Pins("K5")), + Subsignal("rst_n", Pins("L8"), IOStandard("LVCMOS33")), + Subsignal("int_n", Pins("J4")), + Subsignal("mdio", Pins("H2")), + Subsignal("mdc", Pins("J2")), + Subsignal("rx_ctl", Pins("K5")), Subsignal("rx_data", Pins("J9 K1 K6 K4")), - Subsignal("tx_ctl", Pins("L5")), + Subsignal("tx_ctl", Pins("L5")), Subsignal("tx_data", Pins("K8 L1 L2 L3")), IOStandard("LVCMOS25") ), @@ -87,7 +87,7 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- class Platform(MicrosemiPlatform): - default_clk_name = "clk50" + default_clk_name = "clk50" default_clk_period = 1e9/50e6 def __init__(self): diff --git a/litex/boards/platforms/de0nano.py b/litex/boards/platforms/de0nano.py index 8cc079ce..56cc5f16 100644 --- a/litex/boards/platforms/de0nano.py +++ b/litex/boards/platforms/de0nano.py @@ -14,17 +14,17 @@ _io = [ ("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")), ("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")), ("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")), - ("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")), - ("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")), - ("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")), - ("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")), + ("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")), + ("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")), + ("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")), + ("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")), ("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")), - ("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")), + ("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")), - ("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")), - ("sw", 1, Pins("T8"), IOStandard("3.3-V LVTTL")), - ("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")), + ("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")), + ("sw", 1, Pins("T8"), IOStandard("3.3-V LVTTL")), + ("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")), ("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")), ("serial", 0, @@ -34,23 +34,27 @@ _io = [ ("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")), ("sdram", 0, - Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")), - Subsignal("ba", Pins("M7 M6")), - Subsignal("cs_n", Pins("P6")), - Subsignal("cke", Pins("L7")), + Subsignal("a", Pins( + "P2 N5 N6 M8 P8 T7 N8 T6", + "R1 P1 N2 N1 L4")), + Subsignal("ba", Pins("M7 M6")), + Subsignal("cs_n", Pins("P6")), + Subsignal("cke", Pins("L7")), Subsignal("ras_n", Pins("L2")), Subsignal("cas_n", Pins("L1")), - Subsignal("we_n", Pins("C2")), - Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")), + Subsignal("we_n", Pins("C2")), + Subsignal("dq", Pins( + "G2 G1 L8 K5 K2 J2 J1 R7", + "T4 T2 T3 R3 R5 P3 N3 K1")), Subsignal("dm", Pins("R6 T5")), IOStandard("3.3-V LVTTL") ), ("epcs", 0, Subsignal("data0", Pins("H2")), - Subsignal("dclk", Pins("H1")), - Subsignal("ncs0", Pins("D2")), - Subsignal("asd0", Pins("C1")), + Subsignal("dclk", Pins("H1")), + Subsignal("ncs0", Pins("D2")), + Subsignal("asd0", Pins("C1")), IOStandard("3.3-V LVTTL") ), @@ -62,32 +66,37 @@ _io = [ ("g_sensor", 0, Subsignal("cs_n", Pins("G5")), - Subsignal("int", Pins("M2")), + Subsignal("int", Pins("M2")), IOStandard("3.3-V LVTTL") ), ("adc", 0, - Subsignal("cs_n", Pins("A10")), + Subsignal("cs_n", Pins("A10")), Subsignal("saddr", Pins("B10")), - Subsignal("sclk", Pins("B14")), - Subsignal("sdat", Pins("A9")), + Subsignal("sclk", Pins("B14")), + Subsignal("sdat", Pins("A9")), IOStandard("3.3-V LVTTL") ), - ("gpio_0", 0, - Pins("D3 C3 A2 A3 B3 B4 A4 B5 A5 D5 B6 A6 B7 D6 A7 C6", - "C8 E6 E7 D8 E8 F8 F9 E9 C9 D9 E11 E10 C11 B11 A12 D11", - "D12 B12"), + ("gpio_0", 0, Pins( + "D3 C3 A2 A3 B3 B4 A4 B5", + "A5 D5 B6 A6 B7 D6 A7 C6", + "C8 E6 E7 D8 E8 F8 F9 E9", + "C9 D9 E11 E10 C11 B11 A12 D11", + "D12 B12"), IOStandard("3.3-V LVTTL") ), - ("gpio_1", 0, - Pins("F13 T15 T14 T13 R13 T12 R12 T11 T10 R11 P11 R10 N12 P9 N9 N11", - "L16 K16 R16 L15 P15 P16 R14 N16 N15 P14 L14 N14 M10 L13 J16 K15", - "J13 J14"), + ("gpio_1", 0, Pins( + "F13 T15 T14 T13 R13 T12 R12 T11", + "T10 R11 P11 R10 N12 P9 N9 N11", + "L16 K16 R16 L15 P15 P16 R14 N16", + "N15 P14 L14 N14 M10 L13 J16 K15", + "J13 J14"), IOStandard("3.3-V LVTTL") ), - ("gpio_2", 0, - Pins("A14 B16 C14 C16 C15 D16 D15 D14 F15 F16 F14 G16 G15"), + ("gpio_2", 0, Pins( + "A14 B16 C14 C16 C15 D16 D15 D14", + "F15 F16 F14 G16 G15"), IOStandard("3.3-V LVTTL") ), ] @@ -95,7 +104,7 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- class Platform(AlteraPlatform): - default_clk_name = "clk50" + default_clk_name = "clk50" default_clk_period = 1e9/50e6 def __init__(self): diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py index 675e50c4..523aa92b 100644 --- a/litex/boards/platforms/genesys2.py +++ b/litex/boards/platforms/genesys2.py @@ -46,21 +46,21 @@ _io = [ ("ddram", 0, Subsignal("a", Pins( - "AC12 AE8 AD8 AC10 AD9 AA13 AA10 AA11", - "Y10 Y11 AB8 AA8 AB12 AA12 AH9"), + "AC12 AE8 AD8 AC10 AD9 AA13 AA10 AA11", + "Y10 Y11 AB8 AA8 AB12 AA12 AH9"), IOStandard("SSTL15")), - Subsignal("ba", Pins("AE9 AB10 AC11"), IOStandard("SSTL15")), + Subsignal("ba", Pins("AE9 AB10 AC11"), IOStandard("SSTL15")), Subsignal("ras_n", Pins("AE11"), IOStandard("SSTL15")), Subsignal("cas_n", Pins("AF11"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("AG13"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("AH12"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("AG13"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AH12"), IOStandard("SSTL15")), Subsignal("dm", Pins("AD4 AF3 AH4 AF8"), IOStandard("SSTL15")), Subsignal("dq", Pins( "AD3 AC2 AC1 AC5 AC4 AD6 AE6 AC7", "AF2 AE1 AF1 AE4 AE3 AE5 AF5 AF6", "AJ4 AH6 AH5 AH2 AJ2 AJ1 AK1 AJ3", - "AF7 AG7 AJ6 AK6 AJ8 AK8 AK5 AK4"), + "AF7 AG7 AJ6 AK6 AJ8 AK8 AK5 AK4"), IOStandard("SSTL15_T_DCI")), Subsignal("dqs_p", Pins("AD2 AG4 AG2 AH7"), IOStandard("DIFF_SSTL15")), @@ -68,8 +68,8 @@ _io = [ IOStandard("DIFF_SSTL15")), Subsignal("clk_p", Pins("AB9"), IOStandard("DIFF_SSTL15")), Subsignal("clk_n", Pins("AC9"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("AJ9"), IOStandard("SSTL15")), - Subsignal("odt", Pins("AK9"), IOStandard("SSTL15")), + Subsignal("cke", Pins("AJ9"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AK9"), IOStandard("SSTL15")), Subsignal("reset_n", Pins("AG5"), IOStandard("LVCMOS15")), Misc("SLEW=FAST"), Misc("VCCAUX_IO=HIGH") @@ -81,13 +81,13 @@ _io = [ IOStandard("LVCMOS15") ), ("eth", 0, - Subsignal("rst_n", Pins("AH24"), IOStandard("LVCMOS33")), - Subsignal("int_n", Pins("AK16"), IOStandard("LVCMOS18")), - Subsignal("mdio", Pins("AG12"), IOStandard("LVCMOS15")), - Subsignal("mdc", Pins("AF12"), IOStandard("LVCMOS15")), - Subsignal("rx_ctl", Pins("AH11"), IOStandard("LVCMOS15")), + Subsignal("rst_n", Pins("AH24"), IOStandard("LVCMOS33")), + Subsignal("int_n", Pins("AK16"), IOStandard("LVCMOS18")), + Subsignal("mdio", Pins("AG12"), IOStandard("LVCMOS15")), + Subsignal("mdc", Pins("AF12"), IOStandard("LVCMOS15")), + Subsignal("rx_ctl", Pins("AH11"), IOStandard("LVCMOS15")), Subsignal("rx_data", Pins("AJ14 AH14 AK13 AJ13"), IOStandard("LVCMOS15")), - Subsignal("tx_ctl", Pins(" AK14"), IOStandard("LVCMOS15")), + Subsignal("tx_ctl", Pins(" AK14"), IOStandard("LVCMOS15")), Subsignal("tx_data", Pins("AJ12 AK11 AJ11 AK10"), IOStandard("LVCMOS15")), ), ] @@ -96,10 +96,10 @@ _io = [ _connectors = [ ("HPC", { - "DP0_C2M_P": "Y2", - "DP0_C2M_N": "Y1", - "DP0_M2C_P": "AA4", - "DP0_M2C_N": "AA3", + "DP0_C2M_P": "Y2", + "DP0_C2M_N": "Y1", + "DP0_M2C_P": "AA4", + "DP0_M2C_N": "AA3", "GBTCLK0_M2C_P": "L8", "GBTCLK0_M2C_N": "L7", } @@ -109,7 +109,7 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk200" + default_clk_name = "clk200" default_clk_period = 1e9/200e6 def __init__(self): diff --git a/litex/boards/platforms/icebreaker.py b/litex/boards/platforms/icebreaker.py index 18a32c14..a46651ef 100644 --- a/litex/boards/platforms/icebreaker.py +++ b/litex/boards/platforms/icebreaker.py @@ -22,7 +22,7 @@ _io = [ ("serial", 0, Subsignal("rx", Pins("6")), - Subsignal("tx", Pins("9")), + Subsignal("tx", Pins("9"), Misc("PULLUP")), IOStandard("LVCMOS33") ), @@ -47,7 +47,7 @@ _io = [ # Connectors --------------------------------------------------------------------------------------- _connectors = [ - ("PMOD1A", "4 2 47 45 3 48 46 44"), + ("PMOD1A", "4 2 47 45 3 48 46 44"), ("PMOD1B", "43 38 34 31 42 36 32 28"), ("PMOD2", "27 25 21 19 26 23 20 18") ] @@ -79,7 +79,7 @@ break_off_pmod = [ class Platform(LatticePlatform): default_clk_name = "clk12" - default_clk_period = 1e9 / 12e6 + default_clk_period = 1e9/12e6 def __init__(self): LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm") diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py index 3abde5bb..d1f02a50 100644 --- a/litex/boards/platforms/kc705.py +++ b/litex/boards/platforms/kc705.py @@ -8,27 +8,27 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ - ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), - ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")), - ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")), - ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")), + ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), + ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")), + ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")), + ("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")), ("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")), - ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")), - ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")), - ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), + ("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")), + ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")), + ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")), - ("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")), + ("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")), ("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")), ("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")), - ("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")), - ("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")), + ("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")), + ("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")), - ("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")), - ("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")), + ("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")), + ("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")), ("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")), - ("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")), + ("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")), ("user_sma_clock", 0, Subsignal("p", Pins("L25"), IOStandard("LVDS_25"), @@ -60,19 +60,19 @@ _io = [ ("serial", 0, Subsignal("cts", Pins("L27")), Subsignal("rts", Pins("K23")), - Subsignal("tx", Pins("K24")), - Subsignal("rx", Pins("M19")), + Subsignal("tx", Pins("K24")), + Subsignal("rx", Pins("M19")), IOStandard("LVCMOS25") ), ("spiflash", 0, # clock needs to be accessed through STARTUPE2 Subsignal("cs_n", Pins("U19")), - Subsignal("dq", Pins("P24", "R25", "R20", "R21")), + Subsignal("dq", Pins("P24", "R25", "R20", "R21")), IOStandard("LVCMOS25") ), ("mmc", 0, - Subsignal("wp", Pins("Y21")), + Subsignal("wp", Pins("Y21")), Subsignal("det", Pins("AA21")), Subsignal("cmd", Pins("AB22")), Subsignal("clk", Pins("AB23")), @@ -81,14 +81,14 @@ _io = [ ("mmc_spi", 0, Subsignal("miso", Pins("AC20"), Misc("PULLUP")), - Subsignal("clk", Pins("AB23")), + Subsignal("clk", Pins("AB23")), Subsignal("mosi", Pins("AB22")), Subsignal("cs_n", Pins("AC21")), IOStandard("LVCMOS25")), ("lcd", 0, Subsignal("db", Pins("AA13 AA10 AA11 Y10")), - Subsignal("e", Pins("AB10")), + Subsignal("e", Pins("AB10")), Subsignal("rs", Pins("Y11")), Subsignal("rw", Pins("AB13")), IOStandard("LVCMOS15")), @@ -100,13 +100,16 @@ _io = [ IOStandard("LVCMOS25")), ("hdmi", 0, - Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")), - Subsignal("de", Pins("H17")), - Subsignal("clk", Pins("K18")), - Subsignal("vsync", Pins("H20")), - Subsignal("hsync", Pins("J18")), - Subsignal("int", Pins("AH24")), - Subsignal("spdif", Pins("J17")), + Subsignal("d", Pins( + "B23 A23 E23 D23 F25 E25 E24 D24", + "F26 E26 G23 G24 J19 H19 L17 L18", + "K19 K20")), + Subsignal("de", Pins("H17")), + Subsignal("clk", Pins("K18")), + Subsignal("vsync", Pins("H20")), + Subsignal("hsync", Pins("J18")), + Subsignal("int", Pins("AH24")), + Subsignal("spdif", Pins("J17")), Subsignal("spdif_out", Pins("G20")), IOStandard("LVCMOS25")), @@ -183,24 +186,24 @@ _io = [ ), ("eth_clocks", 0, - Subsignal("tx", Pins("M28")), + Subsignal("tx", Pins("M28")), Subsignal("gtx", Pins("K30")), - Subsignal("rx", Pins("U27")), + Subsignal("rx", Pins("U27")), IOStandard("LVCMOS25") ), ("eth", 0, - Subsignal("rst_n", Pins("L20")), - Subsignal("int_n", Pins("N30")), - Subsignal("mdio", Pins("J21")), - Subsignal("mdc", Pins("R23")), - Subsignal("rx_dv", Pins("R28")), - Subsignal("rx_er", Pins("V26")), + Subsignal("rst_n", Pins("L20")), + Subsignal("int_n", Pins("N30")), + Subsignal("mdio", Pins("J21")), + Subsignal("mdc", Pins("R23")), + Subsignal("rx_dv", Pins("R28")), + Subsignal("rx_er", Pins("V26")), Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")), - Subsignal("tx_en", Pins("M27")), - Subsignal("tx_er", Pins("N29")), + Subsignal("tx_en", Pins("M27")), + Subsignal("tx_er", Pins("N29")), Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), + Subsignal("col", Pins("W19")), + Subsignal("crs", Pins("R30")), IOStandard("LVCMOS25") ), @@ -208,37 +211,37 @@ _io = [ Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), Subsignal("clk_p", Pins("U8")), Subsignal("clk_n", Pins("U7")), - Subsignal("rx_p", Pins("M6")), - Subsignal("rx_n", Pins("M5")), - Subsignal("tx_p", Pins("L4")), - Subsignal("tx_n", Pins("L3")) + Subsignal("rx_p", Pins("M6")), + Subsignal("rx_n", Pins("M5")), + Subsignal("tx_p", Pins("L4")), + Subsignal("tx_n", Pins("L3")) ), ("pcie_x2", 0, Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), Subsignal("clk_p", Pins("U8")), Subsignal("clk_n", Pins("U7")), - Subsignal("rx_p", Pins("M6 P6")), - Subsignal("rx_n", Pins("M5 P5")), - Subsignal("tx_p", Pins("L4 M2")), - Subsignal("tx_n", Pins("L3 M1")) + Subsignal("rx_p", Pins("M6 P6")), + Subsignal("rx_n", Pins("M5 P5")), + Subsignal("tx_p", Pins("L4 M2")), + Subsignal("tx_n", Pins("L3 M1")) ), ("pcie_x4", 0, Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), Subsignal("clk_p", Pins("U8")), Subsignal("clk_n", Pins("U7")), - Subsignal("rx_p", Pins("M6 P6 R4 T6")), - Subsignal("rx_n", Pins("M5 P5 R3 T5")), - Subsignal("tx_p", Pins("L4 M2 N4 P2")), - Subsignal("tx_n", Pins("L3 M1 N3 P1")) + Subsignal("rx_p", Pins("M6 P6 R4 T6")), + Subsignal("rx_n", Pins("M5 P5 R3 T5")), + Subsignal("tx_p", Pins("L4 M2 N4 P2")), + Subsignal("tx_n", Pins("L3 M1 N3 P1")) ), ("pcie_x8", 0, Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), Subsignal("clk_p", Pins("U8")), Subsignal("clk_n", Pins("U7")), - Subsignal("rx_p", Pins("M6 P6 R4 T6 V6 W4 Y6 AA4")), - Subsignal("rx_n", Pins("M5 P5 R3 T5 V5 W3 Y5 AA3")), - Subsignal("tx_p", Pins("L4 M2 N4 P2 T2 U4 V2 Y2")), - Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1")) + Subsignal("rx_p", Pins("M6 P6 R4 T6 V6 W4 Y6 AA4")), + Subsignal("rx_n", Pins("M5 P5 R3 T5 V5 W3 Y5 AA3")), + Subsignal("tx_p", Pins("L4 M2 N4 P2 T2 U4 V2 Y2")), + Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1")) ), ("vadj_on_b", 0, Pins("J27"), IOStandard("LVCMOS25")), @@ -275,11 +278,11 @@ _io = [ Subsignal("n", Pins("G3")) ), ("sfp_tx_disable_n", 0, Pins("Y20"), IOStandard("LVCMOS25")), - ("sfp_rx_los", 0, Pins("P19"), IOStandard("LVCMOS25")), + ("sfp_rx_los", 0, Pins("P19"), IOStandard("LVCMOS25")), ("si5324", 0, Subsignal("rst_n", Pins("AE20"), IOStandard("LVCMOS25")), - Subsignal("int", Pins("AG24"), IOStandard("LVCMOS25")) + Subsignal("int", Pins("AG24"), IOStandard("LVCMOS25")) ), ("si5324_clkin", 0, Subsignal("p", Pins("W27"), IOStandard("LVDS_25")), @@ -295,236 +298,236 @@ _io = [ _connectors = [ ("HPC", { - "DP1_M2C_P": "D6", - "DP1_M2C_N": "D5", - "DP2_M2C_P": "B6", - "DP2_M2C_N": "B5", - "DP3_M2C_P": "A8", - "DP3_M2C_N": "A7", - "DP1_C2M_P": "C4", - "DP1_C2M_N": "C3", - "DP2_C2M_P": "B2", - "DP2_C2M_N": "B1", - "DP3_C2M_P": "A4", - "DP3_C2M_N": "A3", - "DP0_C2M_P": "D2", - "DP0_C2M_N": "D1", - "DP0_M2C_P": "E4", - "DP0_M2C_N": "E3", - "LA06_P" : "H30", - "LA06_N" : "G30", - "LA10_P" : "D29", - "LA10_N" : "C30", - "LA14_P": "B28", - "LA14_N": "A28", - "LA18_CC_P": "F21", - "LA18_CC_N": "E21", - "LA27_P": "C19", - "LA27_N": "B19", - "HA01_CC_P": "H14", - "HA01_CC_N": "G14", - "HA05_P": "F15", - "HA05_N": "E16", - "HA09_P": "F12", - "HA09_N": "E13", - "HA13_P": "L16", - "HA13_N": "K16", - "HA16_P": "L15", - "HA16_N": "K15", - "HA20_P": "K13", - "HA20_N": "J13", - "CLK1_M2C_P": "D17", - "CLK1_M2C_N": "D18", - "LA00_CC_P": "C25", - "LA00_CC_N": "B25", - "LA03_P": "H26", - "LA03_N": "H27", - "LA08_P": "E29", - "LA08_N": "E30", - "LA12_P": "C29", - "LA12_N": "B29", - "LA16_P": "B27", - "LA16_N": "A27", - "LA20_P": "E19", - "LA20_N": "D19", - "LA22_P": "C20", - "LA22_N": "B20", - "LA25_P": "G17", - "LA25_N": "F17", - "LA29_P": "C17", - "LA29_N": "B17", - "LA31_P": "G22", - "LA31_N": "F22", - "LA33_P": "H21", - "LA33_N": "H22", - "HA03_P": "C12", - "HA03_N": "B12", - "HA07_P": "B14", - "HA07_N": "A15", - "HA11_P": "B13", - "HA11_N": "A13", - "HA14_P": "J16", - "HA14_N": "H16", - "HA18_P": "K14", - "HA18_N": "J14", - "HA22_P": "L11", - "HA22_N": "K11", - "GBTCLK1_M2C_P": "E8", - "GBTCLK1_M2C_N": "E7", - "GBTCLK0_M2C_P": "C8", - "GBTCLK0_M2C_N": "C7", - "LA01_CC_P": "D26", - "LA01_CC_N": "C26", - "LA05_P": "G29", - "LA05_N": "F30", - "LA09_P": "B30", - "LA09_N": "A30", - "LA13_P": "A25", - "LA13_N": "A26", - "LA17_CC_P": "F20", - "LA17_CC_N": "E20", - "LA23_P": "B22", - "LA23_N": "A22", - "LA26_P": "B18", - "LA26_N": "A18", - "PG_M2C": "J29", - "HA00_CC_P": "D12", - "HA00_CC_N": "D13", - "HA04_P": "F11", - "HA04_N": "E11", - "HA08_P": "E14", - "HA08_N": "E15", - "HA12_P": "C15", - "HA12_N": "B15", - "HA15_P": "H15", - "HA15_N": "G15", - "HA19_P": "H11", - "HA19_N": "H12", - "PRSNT_M2C_B": "M20", - "CLK0_M2C_P": "D27", - "CLK0_M2C_N": "C27", - "LA02_P": "H24", - "LA02_N": "H25", - "LA04_P": "G28", - "LA04_N": "F28", - "LA07_P": "E28", - "LA07_N": "D28", - "LA11_P": "G27", - "LA11_N": "F27", - "LA15_P": "C24", - "LA15_N": "B24", - "LA19_P": "G18", - "LA19_N": "F18", - "LA21_P": "A20", - "LA21_N": "A21", - "LA24_P": "A16", - "LA24_N": "A17", - "LA28_P": "D16", - "LA28_N": "C16", - "LA30_P": "D22", - "LA30_N": "C22", - "LA32_P": "D21", - "LA32_N": "C21", - "HA02_P": "D11", - "HA02_N": "C11", - "HA06_P": "D14", - "HA06_N": "C14", - "HA10_P": "A11", - "HA10_N": "A12", - "HA17_CC_P": "G13", - "HA17_CC_N": "F13", - "HA21_P": "J11", - "HA21_N": "J12", - "HA23_P": "L12", - "HA23_N": "L13", + "DP1_M2C_P" : "D6", + "DP1_M2C_N" : "D5", + "DP2_M2C_P" : "B6", + "DP2_M2C_N" : "B5", + "DP3_M2C_P" : "A8", + "DP3_M2C_N" : "A7", + "DP1_C2M_P" : "C4", + "DP1_C2M_N" : "C3", + "DP2_C2M_P" : "B2", + "DP2_C2M_N" : "B1", + "DP3_C2M_P" : "A4", + "DP3_C2M_N" : "A3", + "DP0_C2M_P" : "D2", + "DP0_C2M_N" : "D1", + "DP0_M2C_P" : "E4", + "DP0_M2C_N" : "E3", + "LA06_P" : "H30", + "LA06_N" : "G30", + "LA10_P" : "D29", + "LA10_N" : "C30", + "LA14_P" : "B28", + "LA14_N" : "A28", + "LA18_CC_P" : "F21", + "LA18_CC_N" : "E21", + "LA27_P" : "C19", + "LA27_N" : "B19", + "HA01_CC_P" : "H14", + "HA01_CC_N" : "G14", + "HA05_P" : "F15", + "HA05_N" : "E16", + "HA09_P" : "F12", + "HA09_N" : "E13", + "HA13_P" : "L16", + "HA13_N" : "K16", + "HA16_P" : "L15", + "HA16_N" : "K15", + "HA20_P" : "K13", + "HA20_N" : "J13", + "CLK1_M2C_P" : "D17", + "CLK1_M2C_N" : "D18", + "LA00_CC_P" : "C25", + "LA00_CC_N" : "B25", + "LA03_P" : "H26", + "LA03_N" : "H27", + "LA08_P" : "E29", + "LA08_N" : "E30", + "LA12_P" : "C29", + "LA12_N" : "B29", + "LA16_P" : "B27", + "LA16_N" : "A27", + "LA20_P" : "E19", + "LA20_N" : "D19", + "LA22_P" : "C20", + "LA22_N" : "B20", + "LA25_P" : "G17", + "LA25_N" : "F17", + "LA29_P" : "C17", + "LA29_N" : "B17", + "LA31_P" : "G22", + "LA31_N" : "F22", + "LA33_P" : "H21", + "LA33_N" : "H22", + "HA03_P" : "C12", + "HA03_N" : "B12", + "HA07_P" : "B14", + "HA07_N" : "A15", + "HA11_P" : "B13", + "HA11_N" : "A13", + "HA14_P" : "J16", + "HA14_N" : "H16", + "HA18_P" : "K14", + "HA18_N" : "J14", + "HA22_P" : "L11", + "HA22_N" : "K11", + "GBTCLK1_M2C_P" : "E8", + "GBTCLK1_M2C_N" : "E7", + "GBTCLK0_M2C_P" : "C8", + "GBTCLK0_M2C_N" : "C7", + "LA01_CC_P" : "D26", + "LA01_CC_N" : "C26", + "LA05_P" : "G29", + "LA05_N" : "F30", + "LA09_P" : "B30", + "LA09_N" : "A30", + "LA13_P" : "A25", + "LA13_N" : "A26", + "LA17_CC_P" : "F20", + "LA17_CC_N" : "E20", + "LA23_P" : "B22", + "LA23_N" : "A22", + "LA26_P" : "B18", + "LA26_N" : "A18", + "PG_M2C" : "J29", + "HA00_CC_P" : "D12", + "HA00_CC_N" : "D13", + "HA04_P" : "F11", + "HA04_N" : "E11", + "HA08_P" : "E14", + "HA08_N" : "E15", + "HA12_P" : "C15", + "HA12_N" : "B15", + "HA15_P" : "H15", + "HA15_N" : "G15", + "HA19_P" : "H11", + "HA19_N" : "H12", + "PRSNT_M2C_B" : "M20", + "CLK0_M2C_P" : "D27", + "CLK0_M2C_N" : "C27", + "LA02_P" : "H24", + "LA02_N" : "H25", + "LA04_P" : "G28", + "LA04_N" : "F28", + "LA07_P" : "E28", + "LA07_N" : "D28", + "LA11_P" : "G27", + "LA11_N" : "F27", + "LA15_P" : "C24", + "LA15_N" : "B24", + "LA19_P" : "G18", + "LA19_N" : "F18", + "LA21_P" : "A20", + "LA21_N" : "A21", + "LA24_P" : "A16", + "LA24_N" : "A17", + "LA28_P" : "D16", + "LA28_N" : "C16", + "LA30_P" : "D22", + "LA30_N" : "C22", + "LA32_P" : "D21", + "LA32_N" : "C21", + "HA02_P" : "D11", + "HA02_N" : "C11", + "HA06_P" : "D14", + "HA06_N" : "C14", + "HA10_P" : "A11", + "HA10_N" : "A12", + "HA17_CC_P" : "G13", + "HA17_CC_N" : "F13", + "HA21_P" : "J11", + "HA21_N" : "J12", + "HA23_P" : "L12", + "HA23_N" : "L13", } ), ("LPC", { - "GBTCLK0_M2C_P": "N8", - "GBTCLK0_M2C_N": "N7", - "LA01_CC_P": "AE23", - "LA01_CC_N": "AF23", - "LA05_P": "AG22", - "LA05_N": "AH22", - "LA09_P": "AK23", - "LA09_N": "AK24", - "LA13_P": "AB24", - "LA13_N": "AC25", - "LA17_CC_P": "AB27", - "LA17_CC_N": "AC27", - "LA23_P": "AH26", - "LA23_N": "AH27", - "LA26_P": "AK29", - "LA26_N": "AK30", - "CLK0_M2C_P": "AF22", - "CLK0_M2C_N": "AG23", - "LA02_P": "AF20", - "LA02_N": "AF21", - "LA04_P": "AH21", - "LA04_N": "AJ21", - "LA07_P": "AG25", - "LA07_N": "AH25", - "LA11_P": "AE25", - "LA11_N": "AF25", - "LA15_P": "AC24", - "LA15_N": "AD24", - "LA19_P": "AJ26", - "LA19_N": "AK26", - "LA21_P": "AG27", - "LA21_N": "AG28", - "LA24_P": "AG30", - "LA24_N": "AH30", - "LA28_P": "AE30", - "LA28_N": "AF30", - "LA30_P": "AB29", - "LA30_N": "AB30", - "LA32_P": "Y30", - "LA32_N": "AA30", - "LA06_P": "AK20", - "LA06_N": "AK21", - "LA10_P": "AJ24", - "LA10_N": "AK25", - "LA14_P": "AD21", - "LA14_N": "AE21", - "LA18_CC_P": "AD27", - "LA18_CC_N": "AD28", - "LA27_P": "AJ28", - "LA27_N": "AJ29", - "CLK1_M2C_P": "AG29", - "CLK1_M2C_N": "AH29", - "LA00_CC_P": "AD23", - "LA00_CC_N": "AE24", - "LA03_P": "AG20", - "LA03_N": "AH20", - "LA08_P": "AJ22", - "LA08_N": "AJ23", - "LA12_P": "AA20", - "LA12_N": "AB20", - "LA16_P": "AC22", - "LA16_N": "AD22", - "LA20_P": "AF26", - "LA20_N": "AF27", - "LA22_P": "AJ27", - "LA22_N": "AK28", - "LA25_P": "AC26", - "LA25_N": "AD26", - "LA29_P": "AE28", - "LA29_N": "AF28", - "LA31_P": "AD29", - "LA31_N": "AE29", - "LA33_P": "AC29", - "LA33_N": "AC30", + "GBTCLK0_M2C_P" : "N8", + "GBTCLK0_M2C_N" : "N7", + "LA01_CC_P" : "AE23", + "LA01_CC_N" : "AF23", + "LA05_P" : "AG22", + "LA05_N" : "AH22", + "LA09_P" : "AK23", + "LA09_N" : "AK24", + "LA13_P" : "AB24", + "LA13_N" : "AC25", + "LA17_CC_P" : "AB27", + "LA17_CC_N" : "AC27", + "LA23_P" : "AH26", + "LA23_N" : "AH27", + "LA26_P" : "AK29", + "LA26_N" : "AK30", + "CLK0_M2C_P" : "AF22", + "CLK0_M2C_N" : "AG23", + "LA02_P" : "AF20", + "LA02_N" : "AF21", + "LA04_P" : "AH21", + "LA04_N" : "AJ21", + "LA07_P" : "AG25", + "LA07_N" : "AH25", + "LA11_P" : "AE25", + "LA11_N" : "AF25", + "LA15_P" : "AC24", + "LA15_N" : "AD24", + "LA19_P" : "AJ26", + "LA19_N" : "AK26", + "LA21_P" : "AG27", + "LA21_N" : "AG28", + "LA24_P" : "AG30", + "LA24_N" : "AH30", + "LA28_P" : "AE30", + "LA28_N" : "AF30", + "LA30_P" : "AB29", + "LA30_N" : "AB30", + "LA32_P" : "Y30", + "LA32_N" : "AA30", + "LA06_P" : "AK20", + "LA06_N" : "AK21", + "LA10_P" : "AJ24", + "LA10_N" : "AK25", + "LA14_P" : "AD21", + "LA14_N" : "AE21", + "LA18_CC_P" : "AD27", + "LA18_CC_N" : "AD28", + "LA27_P" : "AJ28", + "LA27_N" : "AJ29", + "CLK1_M2C_P" : "AG29", + "CLK1_M2C_N" : "AH29", + "LA00_CC_P" : "AD23", + "LA00_CC_N" : "AE24", + "LA03_P" : "AG20", + "LA03_N" : "AH20", + "LA08_P" : "AJ22", + "LA08_N" : "AJ23", + "LA12_P" : "AA20", + "LA12_N" : "AB20", + "LA16_P" : "AC22", + "LA16_N" : "AD22", + "LA20_P" : "AF26", + "LA20_N" : "AF27", + "LA22_P" : "AJ27", + "LA22_N" : "AK28", + "LA25_P" : "AC26", + "LA25_N" : "AD26", + "LA29_P" : "AE28", + "LA29_N" : "AF28", + "LA31_P" : "AD29", + "LA31_N" : "AE29", + "LA33_P" : "AC29", + "LA33_N" : "AC30", } ), ("XADC", { - "GPIO0": "AB25", - "GPIO1": "AA25", - "GPIO2": "AB28", - "GPIO3": "AA27", - "VAUX0_N": "J24", - "VAUX0_P": "J23", - "VAUX8_N": "L23", - "VAUX8_P": "L22", + "GPIO0" : "AB25", + "GPIO1" : "AA25", + "GPIO2" : "AB28", + "GPIO3" : "AA27", + "VAUX0_N" : "J24", + "VAUX0_P" : "J23", + "VAUX8_N" : "L23", + "VAUX8_P" : "L22", } ), ] @@ -532,7 +535,7 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk156" + default_clk_name = "clk156" default_clk_period = 1e9/156.5e6 def __init__(self): diff --git a/litex/boards/platforms/kcu105.py b/litex/boards/platforms/kcu105.py index 3843b54d..038df0fb 100644 --- a/litex/boards/platforms/kcu105.py +++ b/litex/boards/platforms/kcu105.py @@ -20,9 +20,9 @@ _io = [ ("user_btn_c", 0, Pins("AE10"), IOStandard("LVCMOS18")), ("user_btn_n", 0, Pins("AD10"), IOStandard("LVCMOS18")), - ("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")), - ("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")), - ("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")), + ("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")), + ("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")), + ("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")), ("user_dip_btn", 0, Pins("AN16"), IOStandard("LVCMOS12")), ("user_dip_btn", 1, Pins("AN19"), IOStandard("LVCMOS12")), @@ -62,26 +62,26 @@ _io = [ ("serial", 0, Subsignal("cts", Pins("L23")), Subsignal("rts", Pins("K27")), - Subsignal("tx", Pins("K26")), - Subsignal("rx", Pins("G25")), + Subsignal("tx", Pins("K26")), + Subsignal("rx", Pins("G25")), IOStandard("LVCMOS18") ), ("spiflash", 0, # clock needs to be accessed through primitive Subsignal("cs_n", Pins("U7")), - Subsignal("dq", Pins("AC7 AB7 AA7 Y7")), + Subsignal("dq", Pins("AC7 AB7 AA7 Y7")), IOStandard("LVCMOS18") ), ("spiflash", 1, # clock needs to be accessed through primitive Subsignal("cs_n", Pins("G26")), - Subsignal("dq", Pins("M20 L20 R21 R22")), + Subsignal("dq", Pins("M20 L20 R21 R22")), IOStandard("LVCMOS18") ), ("rotary", 0, - Subsignal("a", Pins("Y21")), - Subsignal("b", Pins("AD26")), + Subsignal("a", Pins("Y21")), + Subsignal("b", Pins("AD26")), Subsignal("push", Pins("AF28")), IOStandard("LVCMOS18") ), @@ -91,11 +91,11 @@ _io = [ "AK11 AP11 AP13 AN13 AN11 AM11 AN12 AM12", "AL12 AK12 AL13 AK13 AD11 AH12 AG12 AJ11", "AG10 AK8")), - Subsignal("de", Pins("AE11")), - Subsignal("clk", Pins("AF13")), - Subsignal("vsync", Pins("AH13")), - Subsignal("hsync", Pins("AE13")), - Subsignal("spdif", Pins("AE12")), + Subsignal("de", Pins("AE11")), + Subsignal("clk", Pins("AF13")), + Subsignal("vsync", Pins("AH13")), + Subsignal("hsync", Pins("AE13")), + Subsignal("spdif", Pins("AE12")), Subsignal("spdif_out", Pins("AF12")), IOStandard("LVCMOS18") ), @@ -149,40 +149,40 @@ _io = [ Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB6")), Subsignal("clk_n", Pins("AB5")), - Subsignal("rx_p", Pins("AB2")), - Subsignal("rx_n", Pins("AB1")), - Subsignal("tx_p", Pins("AC4")), - Subsignal("tx_n", Pins("AC3")) + Subsignal("rx_p", Pins("AB2")), + Subsignal("rx_n", Pins("AB1")), + Subsignal("tx_p", Pins("AC4")), + Subsignal("tx_n", Pins("AC3")) ), ("pcie_x2", 0, Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB6")), Subsignal("clk_n", Pins("AB5")), - Subsignal("rx_p", Pins("AB2 AD2")), - Subsignal("rx_n", Pins("AB1 AD1")), - Subsignal("tx_p", Pins("AC4 AE4")), - Subsignal("tx_n", Pins("AC3 AE3")) + Subsignal("rx_p", Pins("AB2 AD2")), + Subsignal("rx_n", Pins("AB1 AD1")), + Subsignal("tx_p", Pins("AC4 AE4")), + Subsignal("tx_n", Pins("AC3 AE3")) ), ("pcie_x4", 0, Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB6")), Subsignal("clk_n", Pins("AB5")), - Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")), - Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")), - Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6")), - Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5")) + Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")), + Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")), + Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6")), + Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5")) ), ("pcie_x8", 0, Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB6")), Subsignal("clk_n", Pins("AB5")), - Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")), - Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")), - Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6 AK6 AL4 AM6 AN4")), - Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5 AK5 AL3 AM5 AN3")) + Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")), + Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")), + Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6 AK6 AL4 AM6 AN4")), + Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5 AK5 AL3 AM5 AN3")) ), ("sgmii_clock", 0, @@ -245,241 +245,241 @@ _io = [ _connectors = [ ("HPC", { - "DP0_C2M_P": "F6", - "DP0_C2M_N": "F5", - "DP0_M2C_P": "E4", - "DP0_M2C_N": "E3", - "DP1_C2M_P": "D6", - "DP1_C2M_N": "D5", - "DP1_M2C_P": "D2", - "DP1_M2C_N": "D1", - "DP2_C2M_P": "C4", - "DP2_C2M_N": "C3", - "DP2_M2C_P": "B2", - "DP2_M2C_N": "B1", - "DP3_C2M_P": "B6", - "DP3_C2M_N": "B5", - "DP3_M2C_P": "A4", - "DP3_M2C_N": "A3", - "DP4_C2M_P": "N4", - "DP4_C2M_N": "N3", - "DP4_M2C_P": "M2", - "DP4_M2C_N": "M1", - "DP5_C2M_P": "J4", - "DP5_C2M_N": "J3", - "DP5_M2C_P": "H2", - "DP5_M2C_N": "H1", - "DP6_C2M_P": "L4", - "DP6_C2M_N": "L3", - "DP6_M2C_P": "K2", - "DP6_M2C_N": "K1", - "DP7_C2M_P": "G4", - "DP7_C2M_N": "G3", - "DP7_M2C_P": "F2", - "DP7_M2C_N": "F1", - "LA06_P": "D13", - "LA06_N": "C13", - "LA10_P": "L8", - "LA10_N": "K8", - "LA14_P": "B10", - "LA14_N": "A10", - "LA18_CC_P": "E22", - "LA18_CC_N": "E23", - "LA27_P": "H21", - "LA27_N": "G21", - "HA01_CC_P": "E16", - "HA01_CC_N": "D16", - "HA05_P": "J15", - "HA05_N": "J14", - "HA09_P": "F18", - "HA09_N": "F17", - "HA13_P": "B14", - "HA13_N": "A14", - "HA16_P": "A19", - "HA16_N": "A18", - "HA20_P": "C19", - "HA20_N": "B19", - "CLK1_M2C_P": "E25", - "CLK1_M2C_N": "D25", - "LA00_CC_P": "H11", - "LA00_CC_N": "G11", - "LA03_P": "A13", - "LA03_N": "A12", - "LA08_P": "J8", - "LA08_N": "H8", - "LA12_P": "E10", - "LA12_N": "D10", - "LA16_P": "B9", - "LA16_N": "A9", - "LA20_P": "B24", - "LA20_N": "A24", - "LA22_P": "G24", - "LA22_N": "F25", - "LA25_P": "D20", - "LA25_N": "D21", - "LA29_P": "B20", - "LA29_N": "A20", - "LA31_P": "B25", - "LA31_N": "A25", - "LA33_P": "A27", - "LA33_N": "A28", - "HA03_P": "G15", - "HA03_N": "G14", - "HA07_P": "L19", - "HA07_N": "L18", - "HA11_P": "J19", - "HA11_N": "J18", - "HA14_P": "F15", - "HA14_N": "F14", - "HA18_P": "B17", - "HA18_N": "B16", - "HA22_P": "C18", - "HA22_N": "C17", - "GBTCLK1_M2C_P": "H6", - "GBTCLK1_M2C_N": "H5", - "GBTCLK0_M2C_P": "K6", - "GBTCLK0_M2C_N": "K5", - "LA01_CC_P": "G9", - "LA01_CC_N": "F9", - "LA05_P": "L13", - "LA05_N": "K13", - "LA09_P": "J9", - "LA09_N": "H9", - "LA13_P": "D9", - "LA13_N": "C9", - "LA17_CC_P": "D24", - "LA17_CC_N": "C24", - "LA23_P": "G22", - "LA23_N": "F22", - "LA26_P": "G20", - "LA26_N": "F20", - "PG_M2C": "L27", - "HA00_CC_P": "G17", - "HA00_CC_N": "G16", - "HA04_P": "G19", - "HA04_N": "F19", - "HA08_P": "K18", - "HA08_N": "K17", - "HA12_P": "K16", - "HA12_N": "J16", - "HA15_P": "D14", - "HA15_N": "C14", - "HA19_P": "D19", - "HA19_N": "D18", - "PRSNT_M2C_B": "H24", - "CLK0_M2C_P": "H12", - "CLK0_M2C_N": "G12", - "LA02_P": "K10", - "LA02_N": "J10", - "LA04_P": "L12", - "LA04_N": "K12", - "LA07_P": "F8", - "LA07_N": "E8", - "LA11_P": "K11", - "LA11_N": "J11", - "LA15_P": "D8", - "LA15_N": "C8", - "LA19_P": "C21", - "LA19_N": "C22", - "LA21_P": "F23", - "LA21_N": "F24", - "LA24_P": "E20", - "LA24_N": "E21", - "LA28_P": "B21", - "LA28_N": "B22", - "LA30_P": "C26", - "LA30_N": "B26", - "LA32_P": "E26", - "LA32_N": "D26", - "HA02_P": "H19", - "HA02_N": "H18", - "HA06_P": "L15", - "HA06_N": "K15", - "HA10_P": "H17", - "HA10_N": "H16", - "HA17_CC_P": "E18", - "HA17_CC_N": "E17", - "HA21_P": "E15", - "HA21_N": "D15", - "HA23_P": "B15", - "HA23_N": "A15", + "DP0_C2M_P" : "F6", + "DP0_C2M_N" : "F5", + "DP0_M2C_P" : "E4", + "DP0_M2C_N" : "E3", + "DP1_C2M_P" : "D6", + "DP1_C2M_N" : "D5", + "DP1_M2C_P" : "D2", + "DP1_M2C_N" : "D1", + "DP2_C2M_P" : "C4", + "DP2_C2M_N" : "C3", + "DP2_M2C_P" : "B2", + "DP2_M2C_N" : "B1", + "DP3_C2M_P" : "B6", + "DP3_C2M_N" : "B5", + "DP3_M2C_P" : "A4", + "DP3_M2C_N" : "A3", + "DP4_C2M_P" : "N4", + "DP4_C2M_N" : "N3", + "DP4_M2C_P" : "M2", + "DP4_M2C_N" : "M1", + "DP5_C2M_P" : "J4", + "DP5_C2M_N" : "J3", + "DP5_M2C_P" : "H2", + "DP5_M2C_N" : "H1", + "DP6_C2M_P" : "L4", + "DP6_C2M_N" : "L3", + "DP6_M2C_P" : "K2", + "DP6_M2C_N" : "K1", + "DP7_C2M_P" : "G4", + "DP7_C2M_N" : "G3", + "DP7_M2C_P" : "F2", + "DP7_M2C_N" : "F1", + "LA06_P" : "D13", + "LA06_N" : "C13", + "LA10_P" : "L8", + "LA10_N" : "K8", + "LA14_P" : "B10", + "LA14_N" : "A10", + "LA18_CC_P" : "E22", + "LA18_CC_N" : "E23", + "LA27_P" : "H21", + "LA27_N" : "G21", + "HA01_CC_P" : "E16", + "HA01_CC_N" : "D16", + "HA05_P" : "J15", + "HA05_N" : "J14", + "HA09_P" : "F18", + "HA09_N" : "F17", + "HA13_P" : "B14", + "HA13_N" : "A14", + "HA16_P" : "A19", + "HA16_N" : "A18", + "HA20_P" : "C19", + "HA20_N" : "B19", + "CLK1_M2C_P" : "E25", + "CLK1_M2C_N" : "D25", + "LA00_CC_P" : "H11", + "LA00_CC_N" : "G11", + "LA03_P" : "A13", + "LA03_N" : "A12", + "LA08_P" : "J8", + "LA08_N" : "H8", + "LA12_P" : "E10", + "LA12_N" : "D10", + "LA16_P" : "B9", + "LA16_N" : "A9", + "LA20_P" : "B24", + "LA20_N" : "A24", + "LA22_P" : "G24", + "LA22_N" : "F25", + "LA25_P" : "D20", + "LA25_N" : "D21", + "LA29_P" : "B20", + "LA29_N" : "A20", + "LA31_P" : "B25", + "LA31_N" : "A25", + "LA33_P" : "A27", + "LA33_N" : "A28", + "HA03_P" : "G15", + "HA03_N" : "G14", + "HA07_P" : "L19", + "HA07_N" : "L18", + "HA11_P" : "J19", + "HA11_N" : "J18", + "HA14_P" : "F15", + "HA14_N" : "F14", + "HA18_P" : "B17", + "HA18_N" : "B16", + "HA22_P" : "C18", + "HA22_N" : "C17", + "GBTCLK1_M2C_P" : "H6", + "GBTCLK1_M2C_N" : "H5", + "GBTCLK0_M2C_P" : "K6", + "GBTCLK0_M2C_N" : "K5", + "LA01_CC_P" : "G9", + "LA01_CC_N" : "F9", + "LA05_P" : "L13", + "LA05_N" : "K13", + "LA09_P" : "J9", + "LA09_N" : "H9", + "LA13_P" : "D9", + "LA13_N" : "C9", + "LA17_CC_P" : "D24", + "LA17_CC_N" : "C24", + "LA23_P" : "G22", + "LA23_N" : "F22", + "LA26_P" : "G20", + "LA26_N" : "F20", + "PG_M2C" : "L27", + "HA00_CC_P" : "G17", + "HA00_CC_N" : "G16", + "HA04_P" : "G19", + "HA04_N" : "F19", + "HA08_P" : "K18", + "HA08_N" : "K17", + "HA12_P" : "K16", + "HA12_N" : "J16", + "HA15_P" : "D14", + "HA15_N" : "C14", + "HA19_P" : "D19", + "HA19_N" : "D18", + "PRSNT_M2C_B" : "H24", + "CLK0_M2C_P" : "H12", + "CLK0_M2C_N" : "G12", + "LA02_P" : "K10", + "LA02_N" : "J10", + "LA04_P" : "L12", + "LA04_N" : "K12", + "LA07_P" : "F8", + "LA07_N" : "E8", + "LA11_P" : "K11", + "LA11_N" : "J11", + "LA15_P" : "D8", + "LA15_N" : "C8", + "LA19_P" : "C21", + "LA19_N" : "C22", + "LA21_P" : "F23", + "LA21_N" : "F24", + "LA24_P" : "E20", + "LA24_N" : "E21", + "LA28_P" : "B21", + "LA28_N" : "B22", + "LA30_P" : "C26", + "LA30_N" : "B26", + "LA32_P" : "E26", + "LA32_N" : "D26", + "HA02_P" : "H19", + "HA02_N" : "H18", + "HA06_P" : "L15", + "HA06_N" : "K15", + "HA10_P" : "H17", + "HA10_N" : "H16", + "HA17_CC_P" : "E18", + "HA17_CC_N" : "E17", + "HA21_P" : "E15", + "HA21_N" : "D15", + "HA23_P" : "B15", + "HA23_N" : "A15", } ), ("LPC", { - "GBTCLK0_M2C_P": "AA24", - "GBTCLK0_M2C_N": "AA25", - "LA01_CC_P": "W25", - "LA01_CC_N": "Y25", - "LA05_P": "V27", - "LA05_N": "V28", - "LA09_P": "V26", - "LA09_N": "W26", - "LA13_P": "AA20", - "LA13_N": "AB20", - "LA17_CC_P": "AA32", - "LA17_CC_N": "AB32", - "LA23_P": "AD30", - "LA23_N": "AD31", - "LA26_P": "AF33", - "LA26_N": "AG34", - "CLK0_M2C_P": "AA24", - "CLK0_M2C_N": "AA25", - "LA02_P": "AA22", - "LA02_N": "AB22", - "LA04_P": "U26", - "LA04_N": "U27", - "LA07_P": "V22", - "LA07_N": "V23", - "LA11_P": "V21", - "LA11_N": "W21", - "LA15_P": "AB25", - "LA15_N": "AB26", - "LA19_P": "AA29", - "LA19_N": "AB29", - "LA21_P": "AC33", - "LA21_N": "AD33", - "LA24_P": "AE32", - "LA24_N": "AF32", - "LA28_P": "V31", - "LA28_N": "W31", - "LA30_P": "Y31", - "LA30_N": "Y32", - "LA32_P": "W30", - "LA32_N": "Y30", - "LA06_P": "V29", - "LA06_N": "W29", - "LA10_P": "T22", - "LA10_N": "T23", - "LA14_P": "U21", - "LA14_N": "U22", - "LA18_CC_P": "AB30", - "LA18_CC_N": "AB31", - "LA27_P": "AG31", - "LA27_N": "AG32", - "CLK1_M2C_P": "AC31", - "CLK1_M2C_N": "AC32", - "LA00_CC_P": "W23", - "LA00_CC_N": "W24", - "LA03_P": "W28", - "LA03_N": "Y28", - "LA08_P": "U24", - "LA08_N": "U25", - "LA12_P": "AC22", - "LA12_N": "AC23", - "LA16_P": "AB21", - "LA16_N": "AC21", - "LA20_P": "AA34", - "LA20_N": "AB34", - "LA22_P": "AC34", - "LA22_N": "AD34", - "LA25_P": "AE33", - "LA25_N": "AF34", - "LA29_P": "U34", - "LA29_N": "V34", - "LA31_P": "V33", - "LA31_N": "W34", - "LA33_P": "W33", - "LA33_N": "Y33", + "GBTCLK0_M2C_P" : "AA24", + "GBTCLK0_M2C_N" : "AA25", + "LA01_CC_P" : "W25", + "LA01_CC_N" : "Y25", + "LA05_P" : "V27", + "LA05_N" : "V28", + "LA09_P" : "V26", + "LA09_N" : "W26", + "LA13_P" : "AA20", + "LA13_N" : "AB20", + "LA17_CC_P" : "AA32", + "LA17_CC_N" : "AB32", + "LA23_P" : "AD30", + "LA23_N" : "AD31", + "LA26_P" : "AF33", + "LA26_N" : "AG34", + "CLK0_M2C_P" : "AA24", + "CLK0_M2C_N" : "AA25", + "LA02_P" : "AA22", + "LA02_N" : "AB22", + "LA04_P" : "U26", + "LA04_N" : "U27", + "LA07_P" : "V22", + "LA07_N" : "V23", + "LA11_P" : "V21", + "LA11_N" : "W21", + "LA15_P" : "AB25", + "LA15_N" : "AB26", + "LA19_P" : "AA29", + "LA19_N" : "AB29", + "LA21_P" : "AC33", + "LA21_N" : "AD33", + "LA24_P" : "AE32", + "LA24_N" : "AF32", + "LA28_P" : "V31", + "LA28_N" : "W31", + "LA30_P" : "Y31", + "LA30_N" : "Y32", + "LA32_P" : "W30", + "LA32_N" : "Y30", + "LA06_P" : "V29", + "LA06_N" : "W29", + "LA10_P" : "T22", + "LA10_N" : "T23", + "LA14_P" : "U21", + "LA14_N" : "U22", + "LA18_CC_P" : "AB30", + "LA18_CC_N" : "AB31", + "LA27_P" : "AG31", + "LA27_N" : "AG32", + "CLK1_M2C_P" : "AC31", + "CLK1_M2C_N" : "AC32", + "LA00_CC_P" : "W23", + "LA00_CC_N" : "W24", + "LA03_P" : "W28", + "LA03_N" : "Y28", + "LA08_P" : "U24", + "LA08_N" : "U25", + "LA12_P" : "AC22", + "LA12_N" : "AC23", + "LA16_P" : "AB21", + "LA16_N" : "AC21", + "LA20_P" : "AA34", + "LA20_N" : "AB34", + "LA22_P" : "AC34", + "LA22_N" : "AD34", + "LA25_P" : "AE33", + "LA25_N" : "AF34", + "LA29_P" : "U34", + "LA29_N" : "V34", + "LA31_P" : "V33", + "LA31_N" : "W34", + "LA33_P" : "W33", + "LA33_N" : "Y33", } ) ] @@ -487,7 +487,7 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk125" + default_clk_name = "clk125" default_clk_period = 1e9/125e6 def __init__(self): diff --git a/litex/boards/platforms/machxo3.py b/litex/boards/platforms/machxo3.py index edad3214..ebf72d6a 100644 --- a/litex/boards/platforms/machxo3.py +++ b/litex/boards/platforms/machxo3.py @@ -34,7 +34,7 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): - default_clk_name = "clk12" + default_clk_name = "clk12" default_clk_period = 1e9/12e6 def __init__(self): diff --git a/litex/boards/platforms/minispartan6.py b/litex/boards/platforms/minispartan6.py index e390c91b..046ee16b 100644 --- a/litex/boards/platforms/minispartan6.py +++ b/litex/boards/platforms/minispartan6.py @@ -51,47 +51,64 @@ _io = [ ("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), ("sdram", 0, - Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")), - Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")), - Subsignal("we_n", Pins("R5")), + Subsignal("a", Pins( + "T15 R16 P15 P16 N16 M15 M16 L16", + "K15 K16 R15 J16 H15")), + Subsignal("dq", Pins( + "T13 T12 R12 T9 R9 T7 R7 T6", + "F16 E15 E16 D16 B16 B15 C16 C15")), + Subsignal("we_n", Pins("R5")), Subsignal("ras_n", Pins("R2")), Subsignal("cas_n", Pins("T4")), - Subsignal("cs_n", Pins("R1")), - Subsignal("cke", Pins("H16")), - Subsignal("ba", Pins("R14 T14")), - Subsignal("dm", Pins("T5 F15")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") + Subsignal("cs_n", Pins("R1")), + Subsignal("cke", Pins("H16")), + Subsignal("ba", Pins("R14 T14")), + Subsignal("dm", Pins("T5 F15")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS33"), ), ("usb_fifo", 0, - Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")), + Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")), Subsignal("rxf_n", Pins("N3")), Subsignal("txe_n", Pins("N1")), - Subsignal("rd_n", Pins("M1")), - Subsignal("wr_n", Pins("M2")), + Subsignal("rd_n", Pins("M1")), + Subsignal("wr_n", Pins("M2")), Subsignal("siwua", Pins("M3")), - IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST") + Misc("SLEW=FAST"), + Drive(8), + IOStandard("LVCMOS33"), + ), + + ("spisdcard", 0, + Subsignal("clk", Pins("L12")), + Subsignal("mosi", Pins("K11"), Misc("PULLUP")), + Subsignal("cs_n", Pins("K12"), Misc("PULLUP")), + Subsignal("miso", Pins("M10"), Misc("PULLUP")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS33"), ), ("sdcard", 0, Subsignal("data", Pins("M10 L10 J11 K12"), Misc("PULLUP")), - Subsignal("cmd", Pins("K11"), Misc("PULLUP")), - Subsignal("clk", Pins("L12")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") + Subsignal("cmd", Pins("K11"), Misc("PULLUP")), + Subsignal("clk", Pins("L12")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS33"), ), ("dvi_in", 0, - Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")), + Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")), Subsignal("data_p", Pins("C7 B6 B5"), IOStandard("TMDS_33")), Subsignal("data_n", Pins("A7 A6 A5"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33")) + Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33")) ), ("dvi_out", 0, - Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")), + Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")), Subsignal("data_p", Pins("C13 B12 C11"), IOStandard("TMDS_33")), Subsignal("data_n", Pins("A13 A12 A11"), IOStandard("TMDS_33")), ) @@ -100,7 +117,7 @@ _io = [ # Connectors --------------------------------------------------------------------------------------- _connectors = [ - ("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"), + ("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"), ("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"), ("C", "J13 J12 K14 L14 L13 M14 M13 N14 M12 N12 P12 M11"), ("D", "D6 C6 E6 C5"), @@ -111,7 +128,7 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk32" + default_clk_name = "clk32" default_clk_period = 1e9/32e6 def __init__(self, device="xc6slx25"): diff --git a/litex/boards/platforms/netv2.py b/litex/boards/platforms/netv2.py index a8fe3797..f3e8abc8 100644 --- a/litex/boards/platforms/netv2.py +++ b/litex/boards/platforms/netv2.py @@ -11,12 +11,12 @@ _io = [ ("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")), # leds - ("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")), - ("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")), - ("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")), + ("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("AA21"), IOStandard("LVCMOS33")), - ("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")), - ("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")), + ("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")), + ("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")), # spiflash ("flash", 0, @@ -31,7 +31,7 @@ _io = [ # spiflash4x ("spiflash4x", 0, Subsignal("cs_n", Pins("T19")), - Subsignal("dq", Pins("P22 R22 P21 R21")), + Subsignal("dq", Pins("P22 R22 P21 R21")), IOStandard("LVCMOS33") ), @@ -48,10 +48,10 @@ _io = [ "U6 V4 W5 V5 AA1 Y2 AB1 AB3", "AB2 Y3 W6 Y1 V2 AA3"), IOStandard("SSTL15_R")), - Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15_R")), + Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15_R")), Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15_R")), Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15_R")), - Subsignal("we_n", Pins("V8"), IOStandard("SSTL15_R")), + Subsignal("we_n", Pins("V8"), IOStandard("SSTL15_R")), Subsignal("dm", Pins("G1 H4 M5 L3"), IOStandard("SSTL15_R")), Subsignal("dq", Pins( "C2 F1 B1 F3 A1 D2 B2 E2", @@ -64,8 +64,8 @@ _io = [ Subsignal("dqs_n", Pins("D1 J2 P4 L1"), IOStandard("DIFF_SSTL15_R")), Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15_R")), Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15_R")), - Subsignal("cke", Pins("Y8"), IOStandard("SSTL15_R")), - Subsignal("odt", Pins("W9"), IOStandard("SSTL15_R")), + Subsignal("cke", Pins("Y8"), IOStandard("SSTL15_R")), + Subsignal("odt", Pins("W9"), IOStandard("SSTL15_R")), Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")), Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15_R")), Misc("SLEW=FAST"), @@ -76,30 +76,30 @@ _io = [ Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), Subsignal("clk_p", Pins("F10")), Subsignal("clk_n", Pins("E10")), - Subsignal("rx_p", Pins("D11")), - Subsignal("rx_n", Pins("C11")), - Subsignal("tx_p", Pins("D5")), - Subsignal("tx_n", Pins("C5")) + Subsignal("rx_p", Pins("D11")), + Subsignal("rx_n", Pins("C11")), + Subsignal("tx_p", Pins("D5")), + Subsignal("tx_n", Pins("C5")) ), ("pcie_x2", 0, Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), Subsignal("clk_p", Pins("F10")), Subsignal("clk_n", Pins("E10")), - Subsignal("rx_p", Pins("D11 B10")), - Subsignal("rx_n", Pins("C11 A10")), - Subsignal("tx_p", Pins("D5 B6")), - Subsignal("tx_n", Pins("C5 A6")) + Subsignal("rx_p", Pins("D11 B10")), + Subsignal("rx_n", Pins("C11 A10")), + Subsignal("tx_p", Pins("D5 B6")), + Subsignal("tx_n", Pins("C5 A6")) ), ("pcie_x4", 0, Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), Subsignal("clk_p", Pins("F10")), Subsignal("clk_n", Pins("E10")), - Subsignal("rx_p", Pins("D11 B10 D9 B8")), - Subsignal("rx_n", Pins("C11 A10 C9 A8")), - Subsignal("tx_p", Pins("D5 B6 D7 B4")), - Subsignal("tx_n", Pins("C5 A6 C7 A4")) + Subsignal("rx_p", Pins("D11 B10 D9 B8")), + Subsignal("rx_n", Pins("C11 A10 C9 A8")), + Subsignal("tx_p", Pins("D5 B6 D7 B4")), + Subsignal("tx_n", Pins("C5 A6 C7 A4")) ), # ethernet @@ -109,30 +109,30 @@ _io = [ ), ("eth", 0, - Subsignal("rst_n", Pins("F16")), + Subsignal("rst_n", Pins("F16")), Subsignal("rx_data", Pins("A20 B18")), - Subsignal("crs_dv", Pins("C20")), - Subsignal("tx_en", Pins("A19")), + Subsignal("crs_dv", Pins("C20")), + Subsignal("tx_en", Pins("A19")), Subsignal("tx_data", Pins("C18 C19")), - Subsignal("mdc", Pins("F14")), - Subsignal("mdio", Pins("F13")), - Subsignal("rx_er", Pins("B20")), - Subsignal("int_n", Pins("D21")), + Subsignal("mdc", Pins("F14")), + Subsignal("mdio", Pins("F13")), + Subsignal("rx_er", Pins("B20")), + Subsignal("int_n", Pins("D21")), IOStandard("LVCMOS33") ), # sdcard ("sdcard", 0, Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")), - Subsignal("cmd", Pins("L13"), Misc("PULLUP True")), - Subsignal("clk", Pins("K18")), + Subsignal("cmd", Pins("L13"), Misc("PULLUP True")), + Subsignal("clk", Pins("K18")), IOStandard("LVCMOS33"), Misc("SLEW=FAST") ), # hdmi in ("hdmi_in", 0, - Subsignal("clk_p", Pins("L19"), IOStandard("TMDS_33"), Inverted()), - Subsignal("clk_n", Pins("L20"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_p", Pins("L19"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_n", Pins("L20"), IOStandard("TMDS_33"), Inverted()), Subsignal("data0_p", Pins("K21"), IOStandard("TMDS_33"), Inverted()), Subsignal("data0_n", Pins("K22"), IOStandard("TMDS_33"), Inverted()), Subsignal("data1_p", Pins("J20"), IOStandard("TMDS_33"), Inverted()), @@ -146,22 +146,22 @@ _io = [ ), ("hdmi_in", 1, - Subsignal("clk_p", Pins("Y18"), IOStandard("TMDS_33"), Inverted()), - Subsignal("clk_n", Pins("Y19"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_p", Pins("Y18"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_n", Pins("Y19"), IOStandard("TMDS_33"), Inverted()), Subsignal("data0_p", Pins("AA18"), IOStandard("TMDS_33")), Subsignal("data0_n", Pins("AB18"), IOStandard("TMDS_33")), Subsignal("data1_p", Pins("AA19"), IOStandard("TMDS_33"), Inverted()), Subsignal("data1_n", Pins("AB20"), IOStandard("TMDS_33"), Inverted()), Subsignal("data2_p", Pins("AB21"), IOStandard("TMDS_33"), Inverted()), Subsignal("data2_n", Pins("AB22"), IOStandard("TMDS_33"), Inverted()), - Subsignal("scl", Pins("W17"), IOStandard("LVCMOS33"), Inverted()), - Subsignal("sda", Pins("R17"), IOStandard("LVCMOS33")), + Subsignal("scl", Pins("W17"), IOStandard("LVCMOS33"), Inverted()), + Subsignal("sda", Pins("R17"), IOStandard("LVCMOS33")), ), # hdmi out ("hdmi_out", 0, - Subsignal("clk_p", Pins("W19"), Inverted(), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("W20"), Inverted(), IOStandard("TMDS_33")), + Subsignal("clk_p", Pins("W19"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_n", Pins("W20"), IOStandard("TMDS_33"), Inverted()), Subsignal("data0_p", Pins("W21"), IOStandard("TMDS_33")), Subsignal("data0_n", Pins("W22"), IOStandard("TMDS_33")), Subsignal("data1_p", Pins("U20"), IOStandard("TMDS_33")), @@ -171,8 +171,8 @@ _io = [ ), ("hdmi_out", 1, - Subsignal("clk_p", Pins("G21"), IOStandard("TMDS_33"), Inverted()), - Subsignal("clk_n", Pins("G22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_p", Pins("G21"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_n", Pins("G22"), IOStandard("TMDS_33"), Inverted()), Subsignal("data0_p", Pins("E22"), IOStandard("TMDS_33"), Inverted()), Subsignal("data0_n", Pins("D22"), IOStandard("TMDS_33"), Inverted()), Subsignal("data1_p", Pins("C22"), IOStandard("TMDS_33"), Inverted()), @@ -180,13 +180,12 @@ _io = [ Subsignal("data2_p", Pins("B21"), IOStandard("TMDS_33"), Inverted()), Subsignal("data2_n", Pins("A21"), IOStandard("TMDS_33"), Inverted()), ), - ] # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk50" + default_clk_name = "clk50" default_clk_period = 1e9/50e6 def __init__(self, device="xc7a35t"): diff --git a/litex/boards/platforms/nexys4ddr.py b/litex/boards/platforms/nexys4ddr.py index 1eec8891..b52ca649 100644 --- a/litex/boards/platforms/nexys4ddr.py +++ b/litex/boards/platforms/nexys4ddr.py @@ -32,11 +32,11 @@ _io = [ ("user_sw", 5, Pins("T18"), IOStandard("LVCMOS33")), ("user_sw", 6, Pins("U18"), IOStandard("LVCMOS33")), ("user_sw", 7, Pins("R13"), IOStandard("LVCMOS33")), - ("user_sw", 8, Pins("T8"), IOStandard("LVCMOS33")), - ("user_sw", 9, Pins("U8"), IOStandard("LVCMOS33")), + ("user_sw", 8, Pins("T8"), IOStandard("LVCMOS33")), + ("user_sw", 9, Pins("U8"), IOStandard("LVCMOS33")), ("user_sw", 10, Pins("R16"), IOStandard("LVCMOS33")), ("user_sw", 11, Pins("T13"), IOStandard("LVCMOS33")), - ("user_sw", 12, Pins("H6"), IOStandard("LVCMOS33")), + ("user_sw", 12, Pins("H6"), IOStandard("LVCMOS33")), ("user_sw", 13, Pins("U12"), IOStandard("LVCMOS33")), ("user_sw", 14, Pins("U11"), IOStandard("LVCMOS33")), ("user_sw", 15, Pins("V10"), IOStandard("LVCMOS33")), @@ -63,15 +63,17 @@ _io = [ Subsignal("mosi", Pins("C1"), Misc("PULLUP True")), Subsignal("cs_n", Pins("D2"), Misc("PULLUP True")), Subsignal("miso", Pins("C2"), Misc("PULLUP True")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") + Misc("SLEW=FAST"), + IOStandard("LVCMOS33"), ), ("sdcard", 0, - Subsignal("rst", Pins("E2"), Misc("PULLUP True")), + Subsignal("rst", Pins("E2"), Misc("PULLUP True")), Subsignal("data", Pins("C2 E1 F1 D2"), Misc("PULLUP True")), - Subsignal("cmd", Pins("C1"), Misc("PULLUP True")), - Subsignal("clk", Pins("B1")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") + Subsignal("cmd", Pins("C1"), Misc("PULLUP True")), + Subsignal("clk", Pins("B1")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS33"), ), ("ddram", 0, @@ -79,10 +81,10 @@ _io = [ "M4 P4 M6 T1 L3 P5 M2 N1", "L4 N5 R2 K5 N6"), IOStandard("SSTL18_II")), - Subsignal("ba", Pins("P2 P3 R1"), IOStandard("SSTL18_II")), + Subsignal("ba", Pins("P2 P3 R1"), IOStandard("SSTL18_II")), Subsignal("ras_n", Pins("N4"), IOStandard("SSTL18_II")), Subsignal("cas_n", Pins("L1"), IOStandard("SSTL18_II")), - Subsignal("we_n", Pins("N2"), IOStandard("SSTL18_II")), + Subsignal("we_n", Pins("N2"), IOStandard("SSTL18_II")), Subsignal("dm", Pins("T6 U1"), IOStandard("SSTL18_II")), Subsignal("dq", Pins( "R7 V6 R8 U7 V7 R6 U6 R5", @@ -93,9 +95,9 @@ _io = [ Subsignal("dqs_n", Pins("V9 V2"), IOStandard("DIFF_SSTL18_II")), Subsignal("clk_p", Pins("L6"), IOStandard("DIFF_SSTL18_II")), Subsignal("clk_n", Pins("L5"), IOStandard("DIFF_SSTL18_II")), - Subsignal("cke", Pins("M1"), IOStandard("SSTL18_II")), - Subsignal("odt", Pins("M3"), IOStandard("SSTL18_II")), - Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")), + Subsignal("cke", Pins("M1"), IOStandard("SSTL18_II")), + Subsignal("odt", Pins("M3"), IOStandard("SSTL18_II")), + Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")), Misc("SLEW=FAST"), ), @@ -105,15 +107,15 @@ _io = [ ), ("eth", 0, - Subsignal("rst_n", Pins("B3")), + Subsignal("rst_n", Pins("B3")), Subsignal("rx_data", Pins("C11 D10")), - Subsignal("crs_dv", Pins("D9")), - Subsignal("tx_en", Pins("B9")), + Subsignal("crs_dv", Pins("D9")), + Subsignal("tx_en", Pins("B9")), Subsignal("tx_data", Pins("A10 A8")), - Subsignal("mdc", Pins("C9")), - Subsignal("mdio", Pins("A9")), - Subsignal("rx_er", Pins("C10")), - Subsignal("int_n", Pins("D8")), + Subsignal("mdc", Pins("C9")), + Subsignal("mdio", Pins("A9")), + Subsignal("rx_er", Pins("C10")), + Subsignal("int_n", Pins("D8")), IOStandard("LVCMOS33") ), ] @@ -121,7 +123,7 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk100" + default_clk_name = "clk100" default_clk_period = 1e9/100e6 def __init__(self): @@ -130,6 +132,3 @@ class Platform(XilinxPlatform): def create_programmer(self): return VivadoProgrammer() - - def do_finalize(self, fragment): - XilinxPlatform.do_finalize(self, fragment) diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py index 4a58f54e..dad949b8 100644 --- a/litex/boards/platforms/nexys_video.py +++ b/litex/boards/platforms/nexys_video.py @@ -60,10 +60,10 @@ _io = [ "M2 M5 M3 M1 L6 P1 N3 N2", "M6 R1 L5 N5 N4 P2 P6"), IOStandard("SSTL15")), - Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")), + Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")), Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")), Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")), Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")), Subsignal("dq", Pins( "G2 H4 H5 J1 K1 H3 H2 J5", @@ -72,10 +72,10 @@ _io = [ Misc("IN_TERM=UNTUNED_SPLIT_50")), Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")), Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("J6"), IOStandard("SSTL15")), - Subsignal("odt", Pins("K4"), IOStandard("SSTL15")), + Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")), + Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")), + Subsignal("cke", Pins("J6"), IOStandard("SSTL15")), + Subsignal("odt", Pins("K4"), IOStandard("SSTL15")), Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")), Misc("SLEW=FAST"), ), @@ -86,46 +86,46 @@ _io = [ IOStandard("LVCMOS25") ), ("eth", 0, - Subsignal("rst_n", Pins("U7"), IOStandard("LVCMOS33")), - Subsignal("int_n", Pins("Y14")), - Subsignal("mdio", Pins("Y16")), - Subsignal("mdc", Pins("AA16")), - Subsignal("rx_ctl", Pins("W10")), + Subsignal("rst_n", Pins("U7"), IOStandard("LVCMOS33")), + Subsignal("int_n", Pins("Y14")), + Subsignal("mdio", Pins("Y16")), + Subsignal("mdc", Pins("AA16")), + Subsignal("rx_ctl", Pins("W10")), Subsignal("rx_data", Pins("AB16 AA15 AB15 AB11")), - Subsignal("tx_ctl", Pins("V10")), + Subsignal("tx_ctl", Pins("V10")), Subsignal("tx_data", Pins("Y12 W12 W11 Y11")), IOStandard("LVCMOS25") ), ("hdmi_in", 0, - Subsignal("clk_p", Pins("V4"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("W4"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("Y3"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("AA3"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("W2"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("Y2"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("U2"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("V2"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("Y4"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("AB5"), IOStandard("LVCMOS33")), - Subsignal("hpd_en", Pins("AB12"), IOStandard("LVCMOS25")), - Subsignal("cec", Pins("AA5"), IOStandard("LVCMOS33")), # FIXME - Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME + Subsignal("clk_p", Pins("V4"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("W4"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("Y3"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("AA3"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("W2"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("Y2"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("U2"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("V2"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("Y4"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("AB5"), IOStandard("LVCMOS33")), + Subsignal("hpd_en", Pins("AB12"), IOStandard("LVCMOS25")), + Subsignal("cec", Pins("AA5"), IOStandard("LVCMOS33")), # FIXME + Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME ), ("hdmi_out", 0, - Subsignal("clk_p", Pins("T1"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("U1"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("W1"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("Y1"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("AA1"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("AB1"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("AB3"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("AB2"), IOStandard("TMDS_33")), - Subsignal("scl", Pins("U3"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("V3"), IOStandard("LVCMOS33")), - Subsignal("cec", Pins("AA4"), IOStandard("LVCMOS33")), # FIXME - Subsignal("hdp", Pins("AB13"), IOStandard("LVCMOS25")), # FIXME + Subsignal("clk_p", Pins("T1"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("U1"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("W1"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("Y1"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("AA1"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("AB1"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("AB3"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("AB2"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("U3"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("V3"), IOStandard("LVCMOS33")), + Subsignal("cec", Pins("AA4"), IOStandard("LVCMOS33")), # FIXME + Subsignal("hdp", Pins("AB13"), IOStandard("LVCMOS25")), # FIXME ), ] @@ -133,84 +133,84 @@ _io = [ _connectors = [ ("LPC", { - "DP0_C2M_P": "D7", - "DP0_C2M_N": "C7", - "DP0_M2C_P": "D9", - "DP0_M2C_N": "C9", - "GBTCLK0_M2C_P": "F10", - "GBTCLK0_M2C_N": "E10", - "LA01_CC_P": "J20", - "LA01_CC_N": "J21", - "LA05_P": "M21", - "LA05_N": "L21", - "LA09_P": "H20", - "LA09_N": "G20", - "LA13_P": "K17", - "LA13_N": "J17", - "LA17_CC_P": "B17", - "LA17_CC_N": "B18", - "LA23_P": "B21", - "LA23_N": "A21", - "LA26_P": "F18", - "LA26_N": "E18", - "CLK0_M2C_P": "J19", - "CLK0_M2C_N": "A19", - "LA02_P": "M18", - "LA02_N": "L18", - "LA04_P": "N20", - "LA04_N": "M20", - "LA07_P": "M13", - "LA07_N": "L13", - "LA11_P": "L14", - "LA11_N": "L15", - "LA15_P": "L16", - "LA15_N": "K16", - "LA19_P": "A18", - "LA19_N": "A19", - "LA21_P": "E19", - "LA21_N": "D19", - "LA24_P": "B15", - "LA24_N": "B16", - "LA28_P": "C13", - "LA28_N": "B13", - "LA30_P": "A13", - "LA30_N": "A14", - "LA32_P": "A15", - "LA32_N": "A16", - "LA06_P": "N22", - "LA06_N": "M22", - "LA10_P": "K21", - "LA10_N": "K22", - "LA14_P": "J22", - "LA14_N": "H22", - "LA18_CC_P": "D17", - "LA18_CC_N": "C17", - "LA27_P": "B20", - "LA27_N": "A20", - "CLK1_M2C_P": "C18", - "CLK1_M2C_N": "C19", - "LA00_CC_P": "K18", - "LA00_CC_N": "K19", - "LA03_P": "N18", - "LA03_N": "N19", - "LA08_P": "M15", - "LA08_N": "M16", - "LA12_P": "L19", - "LA12_N": "L20", - "LA16_P": "G17", - "LA16_N": "G18", - "LA20_P": "F19", - "LA20_N": "F20", - "LA22_P": "E21", - "LA22_N": "D21", - "LA25_P": "F16", - "LA25_N": "E17", - "LA29_P": "C14", - "LA29_N": "C15", - "LA31_P": "E13", - "LA31_N": "E14", - "LA33_P": "F13", - "LA33_N": "F14", + "DP0_C2M_P" : "D7", + "DP0_C2M_N" : "C7", + "DP0_M2C_P" : "D9", + "DP0_M2C_N" : "C9", + "GBTCLK0_M2C_P" : "F10", + "GBTCLK0_M2C_N" : "E10", + "LA01_CC_P" : "J20", + "LA01_CC_N" : "J21", + "LA05_P" : "M21", + "LA05_N" : "L21", + "LA09_P" : "H20", + "LA09_N" : "G20", + "LA13_P" : "K17", + "LA13_N" : "J17", + "LA17_CC_P" : "B17", + "LA17_CC_N" : "B18", + "LA23_P" : "B21", + "LA23_N" : "A21", + "LA26_P" : "F18", + "LA26_N" : "E18", + "CLK0_M2C_P" : "J19", + "CLK0_M2C_N" : "A19", + "LA02_P" : "M18", + "LA02_N" : "L18", + "LA04_P" : "N20", + "LA04_N" : "M20", + "LA07_P" : "M13", + "LA07_N" : "L13", + "LA11_P" : "L14", + "LA11_N" : "L15", + "LA15_P" : "L16", + "LA15_N" : "K16", + "LA19_P" : "A18", + "LA19_N" : "A19", + "LA21_P" : "E19", + "LA21_N" : "D19", + "LA24_P" : "B15", + "LA24_N" : "B16", + "LA28_P" : "C13", + "LA28_N" : "B13", + "LA30_P" : "A13", + "LA30_N" : "A14", + "LA32_P" : "A15", + "LA32_N" : "A16", + "LA06_P" : "N22", + "LA06_N" : "M22", + "LA10_P" : "K21", + "LA10_N" : "K22", + "LA14_P" : "J22", + "LA14_N" : "H22", + "LA18_CC_P" : "D17", + "LA18_CC_N" : "C17", + "LA27_P" : "B20", + "LA27_N" : "A20", + "CLK1_M2C_P" : "C18", + "CLK1_M2C_N" : "C19", + "LA00_CC_P" : "K18", + "LA00_CC_N" : "K19", + "LA03_P" : "N18", + "LA03_N" : "N19", + "LA08_P" : "M15", + "LA08_N" : "M16", + "LA12_P" : "L19", + "LA12_N" : "L20", + "LA16_P" : "G17", + "LA16_N" : "G18", + "LA20_P" : "F19", + "LA20_N" : "F20", + "LA22_P" : "E21", + "LA22_N" : "D21", + "LA25_P" : "F16", + "LA25_N" : "E17", + "LA29_P" : "C14", + "LA29_N" : "C15", + "LA31_P" : "E13", + "LA31_N" : "E14", + "LA33_P" : "F13", + "LA33_N" : "F14", } ) ] @@ -218,7 +218,7 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): - default_clk_name = "clk100" + default_clk_name = "clk100" default_clk_period = 1e9/100e6 def __init__(self): diff --git a/litex/boards/platforms/tinyfpga_bx.py b/litex/boards/platforms/tinyfpga_bx.py index d01f784a..4cfe9638 100644 --- a/litex/boards/platforms/tinyfpga_bx.py +++ b/litex/boards/platforms/tinyfpga_bx.py @@ -20,17 +20,17 @@ _io = [ ("spiflash", 0, Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), - Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), + Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), Subsignal("mosi", Pins("G6"), IOStandard("LVCMOS33")), Subsignal("miso", Pins("H7"), IOStandard("LVCMOS33")), - Subsignal("wp", Pins("H4"), IOStandard("LVCMOS33")), + Subsignal("wp", Pins("H4"), IOStandard("LVCMOS33")), Subsignal("hold", Pins("J8"), IOStandard("LVCMOS33")) ), ("spiflash4x", 0, Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), - Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), - Subsignal("dq", Pins("G6 H7 H4 J8"), IOStandard("LVCMOS33")) + Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), + Subsignal("dq", Pins("G6 H7 H4 J8"), IOStandard("LVCMOS33")) ), ("clk16", 0, Pins("B2"), IOStandard("LVCMOS33")) @@ -42,7 +42,7 @@ _connectors = [ # A2-H2, Pins 1-13 # H9-A6, Pins 14-24 # G1-J2, Pins 25-31 - ("GPIO", "A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2 H9 D9 D8 C9 A9 B8 A8 B7 A7 B6 A6"), + ("GPIO", "A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2 H9 D9 D8 C9 A9 B8 A8 B7 A7 B6 A6"), ("EXTRA", "G1 J3 J4 G9 J9 E8 J2") ] @@ -58,7 +58,7 @@ serial = [ # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): - default_clk_name = "clk16" + default_clk_name = "clk16" default_clk_period = 1e9/16e6 def __init__(self): diff --git a/litex/boards/platforms/ulx3s.py b/litex/boards/platforms/ulx3s.py index fe9f93cc..20640fc3 100644 --- a/litex/boards/platforms/ulx3s.py +++ b/litex/boards/platforms/ulx3s.py @@ -29,7 +29,8 @@ _io = [ Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")), Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")), - IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST") + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), ), ("sdram_clock", 0, Pins("F19"), diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index ccf289e9..1725c196 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -10,7 +10,7 @@ from litex.build.lattice.programmer import LatticeProgrammer _io = [ ("clk100", 0, Pins("P3"), IOStandard("LVDS")), - ("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")), + ("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")), ("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")), @@ -21,10 +21,10 @@ _io = [ ("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")), ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), - ("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")), - ("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")), - ("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")), - ("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")), + ("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")), + ("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")), + ("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")), + ("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")), ("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")), ("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")), ("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")), @@ -39,14 +39,14 @@ _io = [ Subsignal("cs_n", Pins("R2")), Subsignal("mosi", Pins("W2")), Subsignal("miso", Pins("V2")), - Subsignal("wp", Pins("Y2")), + Subsignal("wp", Pins("Y2")), Subsignal("hold", Pins("W1")), IOStandard("LVCMOS33"), ), ("spiflash4x", 0, # clock needs to be accessed through USRMCLK Subsignal("cs_n", Pins("R2")), - Subsignal("dq", Pins("W2 V2 Y2 W1")), + Subsignal("dq", Pins("W2 V2 Y2 W1")), IOStandard("LVCMOS33") ), @@ -55,21 +55,23 @@ _io = [ "P2 C4 E5 F5 B3 F4 B5 E4", "C5 E3 D5 B4 C3"), IOStandard("SSTL135_I")), - Subsignal("ba", Pins("P5 N3 M3"), IOStandard("SSTL135_I")), + Subsignal("ba", Pins("P5 N3 M3"), IOStandard("SSTL135_I")), Subsignal("ras_n", Pins("P1"), IOStandard("SSTL135_I")), Subsignal("cas_n", Pins("L1"), IOStandard("SSTL135_I")), - Subsignal("we_n", Pins("M1"), IOStandard("SSTL135_I")), - Subsignal("cs_n", Pins("K1"), IOStandard("SSTL135_I")), + Subsignal("we_n", Pins("M1"), IOStandard("SSTL135_I")), + Subsignal("cs_n", Pins("K1"), IOStandard("SSTL135_I")), Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")), Subsignal("dq", Pins( "L5 F1 K4 G1 L4 H1 G2 J3", "D1 C1 E2 C2 F3 A2 E1 B1"), IOStandard("SSTL135_I"), Misc("TERMINATION=75")), - Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")), + Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), + Misc("TERMINATION=OFF"), + Misc("DIFFRESISTOR=100")), Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")), - Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")), - Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")), + Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")), + Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")), Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")), Misc("SLEWRATE=FAST"), ), @@ -80,12 +82,12 @@ _io = [ IOStandard("LVCMOS25") ), ("eth", 0, - Subsignal("rst_n", Pins("U17")), - Subsignal("mdio", Pins("U18")), - Subsignal("mdc", Pins("T18")), - Subsignal("rx_ctl", Pins("U19")), + Subsignal("rst_n", Pins("U17")), + Subsignal("mdio", Pins("U18")), + Subsignal("mdc", Pins("T18")), + Subsignal("rx_ctl", Pins("U19")), Subsignal("rx_data", Pins("T20 U20 T19 R18")), - Subsignal("tx_ctl", Pins("R20")), + Subsignal("tx_ctl", Pins("R20")), Subsignal("tx_data", Pins("N19 N20 P18 P20")), IOStandard("LVCMOS25") ), @@ -96,12 +98,12 @@ _io = [ IOStandard("LVCMOS25") ), ("eth", 1, - Subsignal("rst_n", Pins("F20")), - Subsignal("mdio", Pins("H20")), - Subsignal("mdc", Pins("G19")), - Subsignal("rx_ctl", Pins("F19")), + Subsignal("rst_n", Pins("F20")), + Subsignal("mdio", Pins("H20")), + Subsignal("mdc", Pins("G19")), + Subsignal("rx_ctl", Pins("F19")), Subsignal("rx_data", Pins("G18 G16 H18 H17")), - Subsignal("tx_ctl", Pins("E19")), + Subsignal("tx_ctl", Pins("E19")), Subsignal("tx_data", Pins("J17 J16 D19 D20")), IOStandard("LVCMOS25") ), @@ -115,15 +117,15 @@ _io = [ ("pcie_x1", 0, Subsignal("clk_p", Pins("Y11")), Subsignal("clk_n", Pins("Y12")), - Subsignal("rx_p", Pins("Y5")), - Subsignal("rx_n", Pins("Y6")), - Subsignal("tx_p", Pins("W4")), - Subsignal("tx_n", Pins("W5")), + Subsignal("rx_p", Pins("Y5")), + Subsignal("rx_n", Pins("Y6")), + Subsignal("tx_p", Pins("W4")), + Subsignal("tx_n", Pins("W5")), Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")), ), - ("refclk_en", 0, Pins("C12"), IOStandard("LVCMOS33")), - ("refclk_rst_n", 0, Pins("R1"), IOStandard("LVCMOS33")), + ("refclk_en", 0, Pins("C12"), IOStandard("LVCMOS33")), + ("refclk_rst_n", 0, Pins("R1"), IOStandard("LVCMOS33")), ("refclk", 0, Subsignal("p", Pins("Y11")), Subsignal("n", Pins("Y12")), @@ -148,19 +150,20 @@ _ecp5_soc_hat_io = [ ("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins( - "C6 E15 A16 B16 D15 C15 B15 E12", - "D12 B10 C7 A9 C10")), + "C6 E15 A16 B16 D15 C15 B15 E12", + "D12 B10 C7 A9 C10")), Subsignal("dq", Pins( - "B19 B12 B9 E6 D6 E7 D7 B11", + "B19 B12 B9 E6 D6 E7 D7 B11", "C14 A14 E13 D13 C13 B13 A13 A12")), - Subsignal("we_n", Pins("E9")), + Subsignal("we_n", Pins("E9")), Subsignal("ras_n", Pins("B8")), Subsignal("cas_n", Pins("D9")), - Subsignal("cs_n", Pins("C8")), - Subsignal("cke", Pins("D11")), - Subsignal("ba", Pins("D8 E8")), - Subsignal("dm", Pins("B6 D14")), - IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST") + Subsignal("cs_n", Pins("C8")), + Subsignal("cke", Pins("D11")), + Subsignal("ba", Pins("D8 E8")), + Subsignal("dm", Pins("B6 D14")), + Misc("SLEWRATE=FAST"), + IOStandard("LVCMOS33"), ), ] @@ -215,7 +218,7 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): - default_clk_name = "clk100" + default_clk_name = "clk100" default_clk_period = 1e9/100e6 def __init__(self, **kwargs): -- 2.30.2