From def4ad19eaded4a94c98dc25f2b7f7e335b5333a Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Mon, 16 Nov 2015 13:53:23 +0000 Subject: [PATCH] [i386]Migrate reduction optabs to reduc__scal * config/i386/sse.md (reduc_splus_v8df): Rename to... (reduc_plus_scal_v8df): ...here; reduce to temp and extract scalar. (reduc_splus_v4df): Rename to... (reduc_plus_scal_v4df): ...here; reduce to temp and extract scalar. (reduc_splus_v2df): Rename to... (reduc_plus_scal_v2df): ...here; reduce to temp and extract scalar. (reduc_splus_v16sf): Rename to... (reduc_plus_scal_v16sf): ...here; reduce to temp and extract scalar. (reduc_splus_v8sf): Rename to... (reduc_plus_scal_v8sf): ...here; reduce to temp and extract scalar. (reduc_splus_v4sf): Rename to... (reduc_plus_scal_v4sf): ...here; reduce to temp and extract scalar. (reduc__, all 3 variants): Rename each to... (reduc__scal_): ...here; reduce to temp and extract scalar. (reduc_umin_v8hf): Rename to... (reduc_umin_scal_v8hf): ...here; reduce to temp and extract scalar. From-SVN: r230423 --- gcc/ChangeLog | 26 ++++++++++++++ gcc/config/i386/sse.md | 82 ++++++++++++++++++++++++++---------------- 2 files changed, 77 insertions(+), 31 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8fb0728c49f..d106f52a88f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,29 @@ +2015-11-16 Alan Lawrence + + * config/i386/sse.md (reduc_splus_v8df): Rename to... + (reduc_plus_scal_v8df): ...here; reduce to temp and extract scalar. + + (reduc_splus_v4df): Rename to... + (reduc_plus_scal_v4df): ...here; reduce to temp and extract scalar. + + (reduc_splus_v2df): Rename to... + (reduc_plus_scal_v2df): ...here; reduce to temp and extract scalar. + + (reduc_splus_v16sf): Rename to... + (reduc_plus_scal_v16sf): ...here; reduce to temp and extract scalar. + + (reduc_splus_v8sf): Rename to... + (reduc_plus_scal_v8sf): ...here; reduce to temp and extract scalar. + + (reduc_splus_v4sf): Rename to... + (reduc_plus_scal_v4sf): ...here; reduce to temp and extract scalar. + + (reduc__, all 3 variants): Rename each to... + (reduc__scal_): ...here; reduce to temp and extract scalar. + + (reduc_umin_v8hf): Rename to... + (reduc_umin_scal_v8hf): ...here; reduce to temp and extract scalar. + 2015-11-16 Kirill Yukhin * omp-low.c (pass_omp_simd_clone::gate): If target allows - call diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index aad6a0ddd98..71d78f77e88 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2441,73 +2441,85 @@ (set_attr "prefix_rep" "1,*") (set_attr "mode" "V4SF")]) -(define_expand "reduc_splus_v8df" - [(match_operand:V8DF 0 "register_operand") +(define_expand "reduc_plus_scal_v8df" + [(match_operand:DF 0 "register_operand") (match_operand:V8DF 1 "register_operand")] "TARGET_AVX512F" { - ix86_expand_reduc (gen_addv8df3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (V8DFmode); + ix86_expand_reduc (gen_addv8df3, tmp, operands[1]); + emit_insn (gen_vec_extractv8df (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v4df" - [(match_operand:V4DF 0 "register_operand") +(define_expand "reduc_plus_scal_v4df" + [(match_operand:DF 0 "register_operand") (match_operand:V4DF 1 "register_operand")] "TARGET_AVX" { rtx tmp = gen_reg_rtx (V4DFmode); rtx tmp2 = gen_reg_rtx (V4DFmode); + rtx vec_res = gen_reg_rtx (V4DFmode); emit_insn (gen_avx_haddv4df3 (tmp, operands[1], operands[1])); emit_insn (gen_avx_vperm2f128v4df3 (tmp2, tmp, tmp, GEN_INT (1))); - emit_insn (gen_addv4df3 (operands[0], tmp, tmp2)); + emit_insn (gen_addv4df3 (vec_res, tmp, tmp2)); + emit_insn (gen_vec_extractv4df (operands[0], vec_res, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v2df" - [(match_operand:V2DF 0 "register_operand") +(define_expand "reduc_plus_scal_v2df" + [(match_operand:DF 0 "register_operand") (match_operand:V2DF 1 "register_operand")] "TARGET_SSE3" { - emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1])); + rtx tmp = gen_reg_rtx (V2DFmode); + emit_insn (gen_sse3_haddv2df3 (tmp, operands[1], operands[1])); + emit_insn (gen_vec_extractv2df (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v16sf" - [(match_operand:V16SF 0 "register_operand") +(define_expand "reduc_plus_scal_v16sf" + [(match_operand:SF 0 "register_operand") (match_operand:V16SF 1 "register_operand")] "TARGET_AVX512F" { - ix86_expand_reduc (gen_addv16sf3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (V16SFmode); + ix86_expand_reduc (gen_addv16sf3, tmp, operands[1]); + emit_insn (gen_vec_extractv16sf (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v8sf" - [(match_operand:V8SF 0 "register_operand") +(define_expand "reduc_plus_scal_v8sf" + [(match_operand:SF 0 "register_operand") (match_operand:V8SF 1 "register_operand")] "TARGET_AVX" { rtx tmp = gen_reg_rtx (V8SFmode); rtx tmp2 = gen_reg_rtx (V8SFmode); + rtx vec_res = gen_reg_rtx (V8SFmode); emit_insn (gen_avx_haddv8sf3 (tmp, operands[1], operands[1])); emit_insn (gen_avx_haddv8sf3 (tmp2, tmp, tmp)); emit_insn (gen_avx_vperm2f128v8sf3 (tmp, tmp2, tmp2, GEN_INT (1))); - emit_insn (gen_addv8sf3 (operands[0], tmp, tmp2)); + emit_insn (gen_addv8sf3 (vec_res, tmp, tmp2)); + emit_insn (gen_vec_extractv8sf (operands[0], vec_res, const0_rtx)); DONE; }) -(define_expand "reduc_splus_v4sf" - [(match_operand:V4SF 0 "register_operand") +(define_expand "reduc_plus_scal_v4sf" + [(match_operand:SF 0 "register_operand") (match_operand:V4SF 1 "register_operand")] "TARGET_SSE" { + rtx vec_res = gen_reg_rtx (V4SFmode); if (TARGET_SSE3) { rtx tmp = gen_reg_rtx (V4SFmode); emit_insn (gen_sse3_haddv4sf3 (tmp, operands[1], operands[1])); - emit_insn (gen_sse3_haddv4sf3 (operands[0], tmp, tmp)); + emit_insn (gen_sse3_haddv4sf3 (vec_res, tmp, tmp)); } else - ix86_expand_reduc (gen_addv4sf3, operands[0], operands[1]); + ix86_expand_reduc (gen_addv4sf3, vec_res, operands[1]); + emit_insn (gen_vec_extractv4sf (operands[0], vec_res, const0_rtx)); DONE; }) @@ -2521,43 +2533,51 @@ (V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F")]) -(define_expand "reduc__" +(define_expand "reduc__scal_" [(smaxmin:REDUC_SMINMAX_MODE - (match_operand:REDUC_SMINMAX_MODE 0 "register_operand") + (match_operand: 0 "register_operand") (match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))] "" { - ix86_expand_reduc (gen_3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (mode); + ix86_expand_reduc (gen_3, tmp, operands[1]); + emit_insn (gen_vec_extract (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc__" +(define_expand "reduc__scal_" [(umaxmin:VI_AVX512BW - (match_operand:VI_AVX512BW 0 "register_operand") + (match_operand: 0 "register_operand") (match_operand:VI_AVX512BW 1 "register_operand"))] "TARGET_AVX512F" { - ix86_expand_reduc (gen_3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (mode); + ix86_expand_reduc (gen_3, tmp, operands[1]); + emit_insn (gen_vec_extract (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc__" +(define_expand "reduc__scal_" [(umaxmin:VI_256 - (match_operand:VI_256 0 "register_operand") + (match_operand: 0 "register_operand") (match_operand:VI_256 1 "register_operand"))] "TARGET_AVX2" { - ix86_expand_reduc (gen_3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (mode); + ix86_expand_reduc (gen_3, tmp, operands[1]); + emit_insn (gen_vec_extract (operands[0], tmp, const0_rtx)); DONE; }) -(define_expand "reduc_umin_v8hi" +(define_expand "reduc_umin_scal_v8hi" [(umin:V8HI - (match_operand:V8HI 0 "register_operand") + (match_operand:HI 0 "register_operand") (match_operand:V8HI 1 "register_operand"))] "TARGET_SSE4_1" { - ix86_expand_reduc (gen_uminv8hi3, operands[0], operands[1]); + rtx tmp = gen_reg_rtx (V8HImode); + ix86_expand_reduc (gen_uminv8hi3, tmp, operands[1]); + emit_insn (gen_vec_extractv8hi (operands[0], tmp, const0_rtx)); DONE; }) -- 2.30.2