From df12e8ca7c3f8565a158bd35ad8eee35c75a8da5 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sat, 24 Sep 2022 17:51:55 +0300 Subject: [PATCH] power_insn: support SEA specifier --- src/openpower/decoder/power_insn.py | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 4805f2dc..47dd6136 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1470,6 +1470,14 @@ class PredicateWidthBaseRM(WidthBaseRM, PredicateBaseRM): pass +class SEABaseRM(BaseRM): + def specifiers(self, record): + if self.SEA: + yield "sea" + + yield from super().specifiers(record=record) + + class NormalBaseRM(PredicateWidthBaseRM): """ Normal mode @@ -1638,14 +1646,14 @@ class LDSTIdxBaseRM(PredicateWidthBaseRM): pass -class LDSTIdxSimpleRM(DZBaseRM, SZBaseRM, LDSTIdxBaseRM): +class LDSTIdxSimpleRM(SEABaseRM, DZBaseRM, SZBaseRM, LDSTIdxBaseRM): """ld/st index: simple mode""" SEA: BaseRM.mode[2] dz: BaseRM.mode[3] sz: BaseRM.mode[4] -class LDSTIdxStrideRM(DZBaseRM, SZBaseRM, LDSTIdxBaseRM): +class LDSTIdxStrideRM(SEABaseRM, DZBaseRM, SZBaseRM, LDSTIdxBaseRM): """ld/st index: strided (scalar only source)""" SEA: BaseRM.mode[2] dz: BaseRM.mode[3] @@ -1895,7 +1903,7 @@ class RM(BaseRM): # concatenate mode 5-bit with Rc (LSB) then do a mask/map search # mode Rc mask Rc member table = ( - (0b000000, 0b111000, "simple"), # simple (no Rc) + (0b000000, 0b110000, "simple"), # simple (no Rc) (0b010000, 0b110000, "stride"), # strided, (no Rc) (0b100000, 0b110000, "sat"), # saturation (no Rc) (0b110001, 0b110001, "prrc1"), # predicate, Rc=1 -- 2.30.2