From df1a1d30ea18a15359a4bc40361097e0c94b1c97 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 30 Oct 2023 06:55:35 +0000
Subject: [PATCH]

---
 openpower/sv/cookbook/remap_matrix.mdwn | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/openpower/sv/cookbook/remap_matrix.mdwn b/openpower/sv/cookbook/remap_matrix.mdwn
index 68ba24a49..868b3bbf9 100644
--- a/openpower/sv/cookbook/remap_matrix.mdwn
+++ b/openpower/sv/cookbook/remap_matrix.mdwn
@@ -19,13 +19,17 @@ result matrices to the actual index inside the scalar register file.
 
 The matrix multiply looks like this:
 
+```
     mat_X * mat_Y = mat_Z
+```
 
 When multiplying non-square matrices (rows != columns), to determine the
 dimension of the result when matrix X has `a` rows and `b` columns and matrix
 Y has `b` rows and `c` columns:
 
+```
     X_axb * Y_bxc = Z_axc
+```
 
 The result matrix will have number of rows of the first matrix, and number of
 columns of the second matrix.
@@ -163,9 +167,9 @@ register.
 
 * SVP64 assembler example:
 [unit test](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;hb=30f2d8a8e92ad2939775f19e6a0f387499e9842b#l56)
-* SVREMAP and SVSHAPE instructions defined in:
+* svremap and svshape instructions defined in:
 [[sv/rfc/ls009]
-* Multiple-Add Low Doubleword instruction pseudo-code (OpenPOWER ISA 3.0C
+* Multiple-Add Low Doubleword instruction pseudo-code (Power ISA 3.0C
 Book I, section 3.3.9): [[openpower/isa/fixedarith]]
 
 *(Need to check if first arg of svremap correct, then one shown works with
@@ -177,15 +181,15 @@ ISACaller)*
 
 ## svshape
 
-The `svshape` instruction is a convenient way to access the SHAPE Special
+The `svshape` instruction is a convenient way to access the `SVSHAPE` Special
 Purpose Registers (SPRs), which were added alongside the SVP64 looping
-system for complex element indexing. Without having SHAPE SPRs, only the most
+system for complex element indexing. Without having "Re-shaping" SPRs, only the most
 basic, consecuting indexing of register elements (0,1,2,3...) would
 be possible.
 
-### SHAPE Remapping SPRs
+### SVSHAPE Remapping SPRs
 
-* See [[sv/remap]] for the full break down of SPRs SHAPE0-3.
+* See [[sv/remap]] for the full break down of SPRs `SVSHAPE0-3`.
 
 For Matrix Multiply, SHAPE0 SPR is used:
 
@@ -242,9 +246,9 @@ have no more than 127 elements in total.
 (Larger matrices can be split into tiles to circumvent this issue, out
 of scope of this document).
 - `svshape` instruction only provides part of the Matrix REMAP capability.
-For rotation and mirroring, SVSHAPE SPRs must be programmed directly (thus
+For rotation and mirroring, `SVSHAPE` SPRs must be programmed directly (thus
 requiring more assembler instructions). Future revisions of SVP64 will
-provide more comprehensive capacity, mitigating the need to write to SVSHAPE
+provide more comprehensive capacity, mitigating the need to write to `SVSHAPE`
 SPRs directly.
 
 Going back to the assembler instruction used to setup the shape for matrix
@@ -257,7 +261,7 @@ multiply:
 breakdown:
 
 - SVxd=2, SVyd=2, SVzd=3
-- SVRM=0 (Matrix mode, uses SHAPE0 SPR)
+- SVRM=0 (Matrix mode, uses `SVSHAPE0` SPR)
 - 
 
 ## SVREMAP
@@ -265,3 +269,6 @@ breakdown:
 
 ## Appendix
 
+
+[[!tag svp64_cookbook ]]
+
-- 
2.30.2