From df271280bc596d26430655337c5998fd24a2f050 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 16 Nov 2020 14:57:23 +0000 Subject: [PATCH] clarify cbank --- openpower/sv/16_bit_compressed.mdwn | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn index c130ac559..8773f9384 100644 --- a/openpower/sv/16_bit_compressed.mdwn +++ b/openpower/sv/16_bit_compressed.mdwn @@ -191,6 +191,8 @@ is "nop" * for (RA|0) when RA=0 the input is a zero immediate, meaning that sub. becomes neg. * RT is implicitly RB: "add RT(=RB), RA, RB" +* Opcode 0b010.0 RA=0 is not missing from the above: + it is a system-wide instruction, "cbank" (section below) ### Logical @@ -294,8 +296,8 @@ Example: CBank=0b001 is heavily optimised to A/Video Encode/Decode. | 16-bit mode | | 10-bit mode | - | 0 1 | 2 3 4 | | 567.8 | 9 a b | c d e | f | - | Bank2 | | 010.0 | CBank | 0 0 0 | M | cbank + | 0 | 1 2 3 4 | | 567.8 | 9 a b | c d e | f | + | N | Bank2 | | 010.0 | CBank | 0 0 0 | M | cbank **not available** in 10-bit mode: -- 2.30.2