From df37931703b2dbacb69227e2bbe0eb51f38ad87b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 7 Feb 2016 17:04:28 -0800 Subject: [PATCH] Serialize simulator on ERET This guarantees interrupts will eventually be taken. --- riscv/decode.h | 6 ++++++ riscv/insns/sret.h | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/riscv/decode.h b/riscv/decode.h index 1dfeac1..f8437ca 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -198,6 +198,12 @@ private: npc = sext_xlen(x); \ } while(0) +#define set_pc_and_serialize(x) \ + do { set_pc(x); /* check alignment */ \ + npc = PC_SERIALIZE; \ + STATE.pc = (x); \ + } while(0) + #define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */ /* Convenience wrappers to simplify softfloat code sequences */ diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h index eacf5be..c3561d3 100644 --- a/riscv/insns/sret.h +++ b/riscv/insns/sret.h @@ -1,8 +1,8 @@ require_privilege(PRV_S); switch (STATE.prv) { - case PRV_S: set_pc(p->get_state()->sepc); break; - case PRV_M: set_pc(p->get_state()->mepc); break; + case PRV_S: set_pc_and_serialize(p->get_state()->sepc); break; + case PRV_M: set_pc_and_serialize(p->get_state()->mepc); break; default: abort(); } -- 2.30.2