From df3c7f1b985df6be598c5f4b965ad06034e83846 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 14 Aug 2022 00:12:31 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 3d4e37ebf..7f08c1b9a 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -205,6 +205,8 @@ on context after decoding of the Scalar suffix: | Field Name | Field bits | Description | |------------|------------|----------------------------------------| | ELWIDTH | `4:5` | Element Width | +| PACK | `4` | Pack subvectors | +| UNPACK | `5` | Unpack subvectoes | | ELWIDTH_SRC | `6:7` | Element Width for Source | | EXTRA | `10:18` | Register Extra encoding | | MODE | `19:23` | changes Vector behaviour | @@ -212,6 +214,7 @@ on context after decoding of the Scalar suffix: * MODE changes the behaviour of the SV operation (result saturation, mapreduce) * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width +* PACK and UNPACK apply to Subvector structure packing * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR). * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix. @@ -471,18 +474,6 @@ augmented to 7 bits in length. `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2. -## RM-2P-1S1D-PU - -| Field Name | Field bits | Description | -|------------|------------|----------------------------| -| Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) | -| Rsrc_EXTRA2 | `12:13` | extends Rsrc (R\*\_EXTRA2 Encoding) | -| PACK_en | `14` | Enable pack | -| UNPACK_en | `15` | Enable unpack | -| MASK_SRC | `16:18` | Execution Mask for Source | - -for [[sv/mv.vec]], [[sv/mv.swizzle]] and also LD/ST (without index) - ## RM-1P-2S1D single-predicate, three registers (2 read, 1 write) -- 2.30.2