From df3d22c026d63533ae73e6695bcd814f533b3c11 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 31 May 2020 12:28:38 +0100 Subject: [PATCH] write cr0 when op.write_cr.ok is set --- src/soc/fu/common_output_stage.py | 2 +- src/soc/fu/compunits/test/test_alu_compunit.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index dfc2cd63..1faa1ee6 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -63,7 +63,7 @@ class CommonOutputStage(PipeModBase): comb += self.o.o.data.eq(o) comb += self.o.o.ok.eq(self.i.o.ok) comb += self.o.cr0.data.eq(cr0) - comb += self.o.cr0.ok.eq((op.rc.rc & op.rc.rc_ok) | is_cmp | is_cmpeqb) + comb += self.o.cr0.ok.eq(op.write_cr.ok) # CR0 to be set comb += self.o.ctx.eq(self.i.ctx) diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index 093c5fc7..049a276e 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -230,6 +230,7 @@ class TestRunner(FHDLTestCase): cridx = yield dec2.e.write_cr.data if rc: + self.assertEqual(cridx_ok, 1, code) self.assertEqual(cridx, 0, code) if cridx_ok: -- 2.30.2