From df3f003ecd4710ee971b625cc9226a463adfa7db Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 9 Sep 2018 02:10:50 +0200 Subject: [PATCH] soc_sdram: update with litedram --- litex/soc/integration/soc_sdram.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index 238ede4c..30548cef 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -15,8 +15,12 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"] class ControllerInjector(Module, AutoCSR): def __init__(self, phy, geom_settings, timing_settings, **kwargs): - self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits, - phy.settings.dfi_databits, phy.settings.nphases) + self.submodules.dfii = dfii.DFIInjector( + geom_settings.addressbits, + geom_settings.bankbits, + phy.settings.nranks, + phy.settings.dfi_databits, + phy.settings.nphases) self.comb += self.dfii.master.connect(phy.dfi) self.submodules.controller = controller = core.LiteDRAMController( -- 2.30.2