From df7ebe0ccaccf83f472c7871c3b56c57b785ecbb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 25 Sep 2020 13:19:58 +0100 Subject: [PATCH] ls180 pinouts --- src/spec/base.py | 9 +++--- src/spec/gen.py | 2 +- src/spec/ifaceprint.py | 8 ++++- src/spec/ls180.py | 63 ++++++++++++++++++++++++++-------------- src/spec/pinfunctions.py | 62 ++++++++++++++++++++++++++------------- 5 files changed, 96 insertions(+), 48 deletions(-) diff --git a/src/spec/base.py b/src/spec/base.py index 9993f19..a03ad93 100644 --- a/src/spec/base.py +++ b/src/spec/base.py @@ -2,21 +2,22 @@ from spec.interfaces import Pinouts from spec.ifaceprint import display, display_fns, check_functions from spec.ifaceprint import display_fixed +from collections import OrderedDict class PinSpec(Pinouts): def __init__(self, pinbanks, fixedpins, function_names, fast=None): self.fastbus = fast or {} - self.pinbanks = {} + self.pinbanks = OrderedDict() self.muxwidths = {} for bank, (sz, muxwidth) in pinbanks.items(): self.pinbanks[bank] = sz self.muxwidths[bank] = muxwidth self.fixedpins = fixedpins self.function_names = function_names - bankspec = {} + bankspec = OrderedDict() self.offs = 0 - pkeys = sorted(self.pinbanks.keys()) + pkeys = self.pinbanks.keys() print self.pinbanks for kn in pkeys: bankspec[kn] = self.offs @@ -43,7 +44,7 @@ auto-generated by [[pinouts.py]] [[!toc ]] """) - bk = sorted(self.pinbanks.keys()) + bk = self.pinbanks.keys() for bank in bk: of.write( "\n## Bank %s (%d pins, width %d)\n\n" % diff --git a/src/spec/gen.py b/src/spec/gen.py index 492ba53..a392264 100644 --- a/src/spec/gen.py +++ b/src/spec/gen.py @@ -44,7 +44,7 @@ def specgen(of, pth, pinouts, bankspec, muxwidths, pinbanks, fixedpins, with open(os.path.join(pth, '%s.txt' % k.lower()), 'w') as g: if len(s0.pingroup) == 1: # only one function, grouped higher for ks in s.keys(): # grouped by interface - assert False, "TODO, single-function" + #assert False, "TODO, single-function" fntype = 'inout' # XXX TODO k = s[ks].suffix k_ = k.lower() diff --git a/src/spec/ifaceprint.py b/src/spec/ifaceprint.py index d0f50d7..4e72d51 100644 --- a/src/spec/ifaceprint.py +++ b/src/spec/ifaceprint.py @@ -111,6 +111,7 @@ def check_functions(of, title, bankspec, fns, pins, required, eint, pwm, print "fn_idx", fnidx print "fnspec", pins.fnspec.keys() + print "required", required for name in required: of.write("## %s\n\n" % name) if descriptions and name in descriptions: @@ -158,7 +159,9 @@ def check_functions(of, title, bankspec, fns, pins, required, eint, pwm, pinidx = sorted(pinfound.keys()) + fname = None removedcount = 0 + print ("pinidx", pinidx) for pin_ in pinidx: fname, pin_, bank, pin, mux = pinfound[pin_] if fname in found: @@ -172,7 +175,10 @@ def check_functions(of, title, bankspec, fns, pins, required, eint, pwm, print fns if removedcount != count: - print ("not all found", name, removedcount, count, title, found, + if fname is None: + print "no match between required and available pins" + else: + print ("not all found", name, removedcount, count, title, found, fns[fname]) print ("pins found", pinfound) diff --git a/src/spec/ls180.py b/src/spec/ls180.py index 51be042..5d751d6 100644 --- a/src/spec/ls180.py +++ b/src/spec/ls180.py @@ -1,18 +1,19 @@ #!/usr/bin/env python -# see https://bugs.libre-soc.org/show_bug.cgi?id=303 +# see https://bugs.libre-soc.org/show_bug.cgi?id=304 from spec.base import PinSpec from spec.ifaceprint import display, display_fns, check_functions from spec.ifaceprint import display_fixed - +from collections import OrderedDict def pinspec(): - pinbanks = { - 'A': (16, 4), - 'B': (16, 4), - 'C': (16, 4), - } + pinbanks = OrderedDict(( + ('N', (32, 2)), + ('E', (32, 2)), + ('S', (32, 2)), + ('W', (32, 2)), + )) fixedpins = { 'CTRL_SYS': [ 'TEST', @@ -33,6 +34,7 @@ def pinspec(): 'VDD_GPIOB', 'GND_GPIOB', ]} + fixedpins = {} function_names = { 'PWM': 'PWM (pulse-width modulation)', 'MSPI2': 'SPI (Serial Peripheral Interface) Master 1', @@ -40,25 +42,43 @@ def pinspec(): 'UART3': 'UART (TX/RX) 2', 'MMC1': 'SD/MMC 1', 'MMC2': 'SD/MMC 2', - 'LPC1': 'Low Pincount Interface 1', - 'LPC2': 'Low Pincount Interface 2', + #'LPC1': 'Low Pincount Interface 1', + #'LPC2': 'Low Pincount Interface 2', } ps = PinSpec(pinbanks, fixedpins, function_names) - ps.gpio("", ('A', 0), 0, 0, 16) + ps.vss("", ('N', 0), 0, 0, 1) + ps.vdd("", ('N', 1), 0, 0, 1) + ps.sdram1("", ('N', 2), 0, 0, 30) + ps.vss("", ('N', 30), 0, 0, 1) + ps.vdd("", ('N', 31), 0, 0, 1) + + ps.vss("", ('E', 0), 0, 1, 1) + ps.sdram2("", ('E', 1), 0, 0, 12) + ps.vdd("", ('E', 13), 0, 1, 1) + ps.gpio("", ('E', 14), 0, 8, 8) + ps.vss("", ('E', 23), 0, 1, 1) + ps.jtag("", ('E', 24), 0, 0, 4) + ps.vdd("", ('E', 31), 0, 1, 1) + + ps.vss("", ('S', 0), 0, 1, 1) + ps.clk("", ('S', 1), 0, 0, 1) + ps.rst("", ('S', 2), 0, 0, 1) + ps.mspi("0", ('S', 3), 0) + ps.uart("0", ('S', 7), 0) + ps.vdd("", ('S', 31), 0, 1, 1) - ps.pwm("", ('B', 0), 0, 0, 2) - ps.eint("", ('B', 2), 0, 0, 6) - ps.mspi("2", ('B', 8), 0) - ps.uart("1", ('B', 12), 0) - ps.uart("3", ('B', 14), 0) - ps.i2c("1", ('C', 0), 0) - ps.i2c("2", ('C', 2), 0) - ps.lpc("1", ('C', 4), 0) - ps.lpc("2", ('C', 10), 1) + ps.vss("", ('W', 0), 0, 1, 1) + ps.pwm("", ('W', 1), 0, 0, 2) + ps.eint("", ('W', 3), 0, 0, 3) + ps.mspi("1", ('W', 6), 0) + ps.sdmmc("0", ('W', 10), 0) + ps.vdd("", ('W', 31), 0, 1, 1) + #ps.mspi("0", ('W', 8), 0) + #ps.mspi("1", ('W', 8), 0) - #ps.mquadspi("1", ('B', 0), 0) + #ps.mquadspi("1", ('S', 0), 0) # Scenarios below can be spec'd out as either "find first interface" # by name/number e.g. SPI1, or as "find in bank/mux" which must be @@ -67,8 +87,7 @@ def pinspec(): # using "BM:Name". Pins are removed in-order as listed from # lists (interfaces, EINTs, PWMs) from available pins. - ls180 = ['ULPI0/8', 'ULPI1', 'MMC1', 'MMC2', 'SD0', 'UART0', 'LPC1', - 'LPC2', + ls180 = ['ULPI0/8', 'ULPI1', 'MMC0', 'MMC2', 'SD0', 'UART0', 'TWI0', 'MSPI0', 'B3:SD1', ] ls180_eint = [] ls180_pwm = []#['B0:PWM_0'] diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index e46be8d..b7318dd 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -79,10 +79,13 @@ def nspi(suffix, bank, iosize, masteronly=True): else: qpins = ['CK*', 'NSS*'] inout = [] - for i in range(iosize): - pname = "IO%d*" % i - qpins.append(pname) - inout.append(pname) + if iosize == 2: + qpins += ['MOSI+', 'MISO-'] + else: + for i in range(iosize): + pname = "IO%d*" % i + qpins.append(pname) + inout.append(pname) return (qpins, inout) @@ -173,35 +176,35 @@ def flexbus2(suffix, bank): return (buspins, buspins) -def sdram1(suffix, bank): +def sdram1(suffix, bank, n_adr=10): buspins = [] inout = [] - for i in range(8): - pname = "SDRDQM%d+" % i + for i in range(1): + pname = "DQM%d+" % i buspins.append(pname) for i in range(8): - pname = "SDRD%d*" % i + pname = "D%d*" % i buspins.append(pname) inout.append(pname) - for i in range(12): - buspins.append("SDRAD%d+" % i) + for i in range(n_adr): + buspins.append("AD%d+" % i) for i in range(2): - buspins.append("SDRBA%d+" % i) - buspins += ['SDRCLK+', 'SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+', - 'SDRCSn0+'] + buspins.append("BA%d+" % i) + buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+', + 'CSn0+'] return (buspins, inout) def sdram2(suffix, bank): buspins = [] inout = [] - for i in range(1, 6): - buspins.append("SDRCSn%d+" % i) - for i in range(8, 16): - pname = "SDRDQM%d*" % i + for i in range(10, 13): + buspins.append("SDRAD%d+" % i) + for i in range(1, 2): + pname = "DQM%d*" % i buspins.append(pname) for i in range(8, 16): - pname = "SDRD%d*" % i + pname = "D%d*" % i buspins.append(pname) inout.append(pname) return (buspins, inout) @@ -210,9 +213,13 @@ def sdram2(suffix, bank): def sdram3(suffix, bank): buspins = [] inout = [] - for i in range(12, 13): + for i in range(1, 6): + buspins.append("CSn%d+" % i) + for i in range(13, 14): buspins.append("SDRAD%d+" % i) - for i in range(8, 64): + for i in range(1, 4): + pname = "DQM%d*" % i + for i in range(8, 32): pname = "SDRD%d*" % i buspins.append(pname) inout.append(pname) @@ -260,6 +267,17 @@ def pwm(suffix, bank): def gpio(suffix, bank): return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), []) +def vss(suffix, bank): + return (RangePin("-"), []) + +def vdd(suffix, bank): + return (RangePin("-"), []) + +def clk(suffix, bank): + return (RangePin("-"), []) + +def rst(suffix, bank): + return (RangePin("-"), []) # list functions by name here @@ -283,6 +301,10 @@ pinspec = (('IIS', i2s), ('SDR', sdram1), ('SDR', sdram2), ('SDR', sdram3), + ('VSS', vss), + ('VDD', vdd), + ('CLK', clk), + ('RST', rst), ('EINT', eint), ('PWM', pwm), ('GPIO', gpio), -- 2.30.2