From df83048b6a6586a28b2096c3674fcf1498a7d90f Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 23 Jul 2022 14:29:45 -0300 Subject: [PATCH] Do not invert DDR3 CS pin on Icarus testbench It seems that IcarusECPIX5Platform does handle PinsN correctly. --- gram/simulation/simsoctb.v | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v index 7818b4e..388d1a7 100644 --- a/gram/simulation/simsoctb.v +++ b/gram/simulation/simsoctb.v @@ -43,8 +43,6 @@ module simsoctb; wire [1:0] dram_tdqs_n; wire dram_rst; - // anything here with "_n" has to be inverted. nmigen platforms - // sort that out by inverting (with PinsN) ddr3 #( .check_strict_timing(0) ) ram_chip ( @@ -52,7 +50,7 @@ module simsoctb; .ck(dram_ck), .ck_n(~dram_ck), .cke(dram_cke), - .cs_n(~dram_cs_n), + .cs_n(dram_cs_n), .ras_n(dram_ras_n), .cas_n(dram_cas_n), .we_n(dram_we_n), -- 2.30.2