From df93b8f37bea53917d67e87ce2190981bc2ef667 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 10 Oct 2021 11:35:20 +0100 Subject: [PATCH] big rename PartitionedSignal to SimdSignal (shorter) https://bugs.libre-soc.org/show_bug.cgi?id=713#c58 --- src/ieee754/fsgnj/fsgnj.py | 2 +- src/ieee754/part/formal/proof_partition.py | 6 +-- src/ieee754/part/partsig.py | 44 +++++++++---------- src/ieee754/part/test/test_partsig.py | 32 +++++++------- src/ieee754/part_ass/assign.py | 14 +++--- src/ieee754/part_cat/cat.py | 10 ++--- src/ieee754/part_repl/repl.py | 14 +++--- src/ieee754/partitioned_signal_tester.py | 8 ++-- src/ieee754/test_partitioned_signal_tester.py | 12 ++--- 9 files changed, 71 insertions(+), 71 deletions(-) diff --git a/src/ieee754/fsgnj/fsgnj.py b/src/ieee754/fsgnj/fsgnj.py index d9be3472..b5bf674d 100644 --- a/src/ieee754/fsgnj/fsgnj.py +++ b/src/ieee754/fsgnj/fsgnj.py @@ -40,7 +40,7 @@ class FSGNJPipeMod(PipeModBase): b = self.i.b # Calculate the sign bit, with a chain of muxes. has to be done - # this way due to (planned) use of PartitionedSignal. decreases + # this way due to (planned) use of SimdSignal. decreases # readability slightly, but hey. # Handle opcodes 0b00 and 0b01, copying or inverting the sign bit of B diff --git a/src/ieee754/part/formal/proof_partition.py b/src/ieee754/part/formal/proof_partition.py index f2ef3074..99b42aaf 100644 --- a/src/ieee754/part/formal/proof_partition.py +++ b/src/ieee754/part/formal/proof_partition.py @@ -41,7 +41,7 @@ from nmutil.formaltest import FHDLTestCase from nmutil.gtkw import write_gtkw from ieee754.part_mul_add.partpoints import PartitionPoints -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal class PartitionedPattern(Elaboratable): @@ -347,7 +347,7 @@ class OpDriver(Elaboratable): # setup inputs and outputs operands = list() for i in range(nops): - inp = PartitionedSignal(points, width, name=f"i_{i+1}") + inp = SimdSignal(points, width, name=f"i_{i+1}") inp.set_module(m) operands.append(inp) if part_out: @@ -359,7 +359,7 @@ class OpDriver(Elaboratable): output = Signal(out_width) # perform the operation on the partitioned signals result = self.op(*operands) - if isinstance(result, PartitionedSignal): + if isinstance(result, SimdSignal): comb += output.eq(result.sig) else: # handle operations that return plain Signals diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py index d6e39f48..bbad0893 100644 --- a/src/ieee754/part/partsig.py +++ b/src/ieee754/part/partsig.py @@ -9,7 +9,7 @@ is fully open will be identical to Signal. when partitions are closed, the class turns into a SIMD variant of Signal. *this is dynamic*. the basic fundamental idea is: write code once, and if you want a SIMD -version of it, use PartitionedSignal in place of Signal. job done. +version of it, use SimdSignal in place of Signal. job done. this however requires the code to *not* be designed to use nmigen.If, nmigen.Case, or other constructs: only Mux and other logic. @@ -35,16 +35,16 @@ from nmigen.hdl.ast import UserValue, Shape def getsig(op1): - if isinstance(op1, PartitionedSignal): + if isinstance(op1, SimdSignal): op1 = op1.sig return op1 def applyop(op1, op2, op): - if isinstance(op1, PartitionedSignal): - result = PartitionedSignal.like(op1) + if isinstance(op1, SimdSignal): + result = SimdSignal.like(op1) else: - result = PartitionedSignal.like(op2) + result = SimdSignal.like(op2) result.m.d.comb += result.sig.eq(op(getsig(op1), getsig(op2))) return result @@ -57,7 +57,7 @@ for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor', 'bool', 'all']: # Prototype https://bugs.libre-soc.org/show_bug.cgi?id=713#c53 -# this provides a "compatibility" layer with existing PartitionedSignal +# this provides a "compatibility" layer with existing SimdSignal # behaviour. the idea is that this interface defines which "combinations" # of partition selections are relevant, and as an added bonus it says # which partition lanes are completely irrelevant (padding, blank). @@ -97,7 +97,7 @@ class ElWidthPartType: # TODO decide name return 0 # TODO -class PartitionedSignal(UserValue): +class SimdSignal(UserValue): # XXX ################################################### XXX # XXX Keep these functions in the same order as ast.Value XXX # XXX ################################################### XXX @@ -121,9 +121,9 @@ class PartitionedSignal(UserValue): @staticmethod def like(other, *args, **kwargs): - """Builds a new PartitionedSignal with the same PartitionPoints and + """Builds a new SimdSignal with the same PartitionPoints and Signal properties as the other""" - result = PartitionedSignal(PartitionPoints(other.partpoints)) + result = SimdSignal(PartitionPoints(other.partpoints)) result.sig = Signal.like(other.sig, *args, **kwargs) result.m = other.m return result @@ -142,15 +142,15 @@ class PartitionedSignal(UserValue): def __Cat__(self, *args, src_loc_at=0): args = [self] + list(args) for sig in args: - assert isinstance(sig, PartitionedSignal), \ - "All PartitionedSignal.__Cat__ arguments must be " \ - "a PartitionedSignal. %s is not." % repr(sig) + assert isinstance(sig, SimdSignal), \ + "All SimdSignal.__Cat__ arguments must be " \ + "a SimdSignal. %s is not." % repr(sig) return PCat(self.m, args, self.ptype) def __Mux__(self, val1, val2): # print ("partsig mux", self, val1, val2) assert len(val1) == len(val2), \ - "PartitionedSignal width sources must be the same " \ + "SimdSignal width sources must be the same " \ "val1 == %d, val2 == %d" % (len(val1), len(val2)) return PMux(self.m, self.partpoints, self, val1, val2, self.ptype) @@ -168,7 +168,7 @@ class PartitionedSignal(UserValue): # unary ops that do not require partitioning def __invert__(self): - result = PartitionedSignal.like(self) + result = SimdSignal.like(self) self.m.d.comb += result.sig.eq(~self.sig) return result @@ -190,7 +190,7 @@ class PartitionedSignal(UserValue): comb += pa.a.eq(op1) comb += pa.b.eq(op2) comb += pa.carry_in.eq(carry) - result = PartitionedSignal.like(self) + result = SimdSignal.like(self) comb += result.sig.eq(pa.output) return result, pa.carry_out @@ -203,7 +203,7 @@ class PartitionedSignal(UserValue): comb += pa.a.eq(op1) comb += pa.b.eq(~op2) comb += pa.carry_in.eq(carry) - result = PartitionedSignal.like(self) + result = SimdSignal.like(self) comb += result.sig.eq(pa.output) return result, pa.carry_out @@ -262,8 +262,8 @@ class PartitionedSignal(UserValue): #def __check_shamt(self): # TODO: detect if the 2nd operand is a Const, a Signal or a - # PartitionedSignal. if it's a Const or a Signal, a global shift - # can occur. if it's a PartitionedSignal, that's much more interesting. + # SimdSignal. if it's a Const or a Signal, a global shift + # can occur. if it's a SimdSignal, that's much more interesting. def ls_op(self, op1, op2, carry, shr_flag=0): op1 = getsig(op1) if isinstance(op2, Const) or isinstance(op2, Signal): @@ -274,7 +274,7 @@ class PartitionedSignal(UserValue): op2 = getsig(op2) pa = PartitionedDynamicShift(len(op1), self.partpoints) # else: - # TODO: case where the *shifter* is a PartitionedSignal but + # TODO: case where the *shifter* is a SimdSignal but # the thing *being* Shifted is a scalar (Signal, expression) # https://bugs.libre-soc.org/show_bug.cgi?id=718 setattr(self.m.submodules, self.get_modname('ls'), pa) @@ -339,11 +339,11 @@ class PartitionedSignal(UserValue): setattr(self.m.submodules, self.get_modname(opname), pa) comb = self.m.d.comb comb += pa.opcode.eq(optype) # set opcode - if isinstance(op1, PartitionedSignal): + if isinstance(op1, SimdSignal): comb += pa.a.eq(op1.sig) else: comb += pa.a.eq(op1) - if isinstance(op2, PartitionedSignal): + if isinstance(op2, SimdSignal): comb += pa.b.eq(op2.sig) else: comb += pa.b.eq(op2) @@ -389,7 +389,7 @@ class PartitionedSignal(UserValue): def __new_sign(self, signed): shape = Shape(len(self), signed=signed) - result = PartitionedSignal.like(self, shape=shape) + result = SimdSignal.like(self, shape=shape) self.m.d.comb += result.sig.eq(self.sig) return result diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py index f5294a84..dcf0231c 100644 --- a/src/ieee754/part/test/test_partsig.py +++ b/src/ieee754/part/test/test_partsig.py @@ -6,7 +6,7 @@ from nmigen import Signal, Module, Elaboratable, Mux, Cat, Shape, Repl from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.cli import rtlil -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal from ieee754.part_mux.part_mux import PMux from random import randint @@ -49,8 +49,8 @@ def create_simulator(module, traces, test_name): class TestAddMod2(Elaboratable): def __init__(self, width, partpoints): self.partpoints = partpoints - self.a = PartitionedSignal(partpoints, width) - self.b = PartitionedSignal(partpoints, width) + self.a = SimdSignal(partpoints, width) + self.b = SimdSignal(partpoints, width) self.bsig = Signal(width) self.add_output = Signal(width) self.ls_output = Signal(width) # left shift @@ -65,7 +65,7 @@ class TestAddMod2(Elaboratable): self.lt_output = Signal(len(partpoints)+1) self.le_output = Signal(len(partpoints)+1) self.mux_sel2 = Signal(len(partpoints)+1) - self.mux_sel2 = PartitionedSignal(partpoints, len(partpoints)) + self.mux_sel2 = SimdSignal(partpoints, len(partpoints)) self.mux2_out = Signal(width) self.carry_in = Signal(len(partpoints)+1) self.add_carry_out = Signal(len(partpoints)+1) @@ -114,10 +114,10 @@ class TestAddMod2(Elaboratable): class TestMuxMod(Elaboratable): def __init__(self, width, partpoints): self.partpoints = partpoints - self.a = PartitionedSignal(partpoints, width) - self.b = PartitionedSignal(partpoints, width) + self.a = SimdSignal(partpoints, width) + self.b = SimdSignal(partpoints, width) self.mux_sel = Signal(len(partpoints)+1) - self.mux_sel2 = PartitionedSignal(partpoints, len(partpoints)+1) + self.mux_sel2 = SimdSignal(partpoints, len(partpoints)+1) self.mux_out2 = Signal(width) def elaborate(self, platform): @@ -137,8 +137,8 @@ class TestMuxMod(Elaboratable): class TestCatMod(Elaboratable): def __init__(self, width, partpoints): self.partpoints = partpoints - self.a = PartitionedSignal(partpoints, width) - self.b = PartitionedSignal(partpoints, width*2) + self.a = SimdSignal(partpoints, width) + self.b = SimdSignal(partpoints, width*2) self.cat_out = Signal(width*3) def elaborate(self, platform): @@ -155,7 +155,7 @@ class TestCatMod(Elaboratable): class TestReplMod(Elaboratable): def __init__(self, width, partpoints): self.partpoints = partpoints - self.a = PartitionedSignal(partpoints, width) + self.a = SimdSignal(partpoints, width) self.repl_sel = Signal(len(partpoints)+1) self.repl_out = Signal(width*2) @@ -176,8 +176,8 @@ class TestAssMod(Elaboratable): if scalar: self.a = Signal(width) else: - self.a = PartitionedSignal(partpoints, width) - self.ass_out = PartitionedSignal(partpoints, out_shape) + self.a = SimdSignal(partpoints, width) + self.ass_out = SimdSignal(partpoints, out_shape) def elaborate(self, platform): m = Module() @@ -194,8 +194,8 @@ class TestAssMod(Elaboratable): class TestAddMod(Elaboratable): def __init__(self, width, partpoints): self.partpoints = partpoints - self.a = PartitionedSignal(partpoints, width) - self.b = PartitionedSignal(partpoints, width) + self.a = SimdSignal(partpoints, width) + self.b = SimdSignal(partpoints, width) self.bsig = Signal(width) self.add_output = Signal(width) self.ls_output = Signal(width) # left shift @@ -662,7 +662,7 @@ class TestAssign(unittest.TestCase): self.run_tst(16, out_width, sign, scalar) -class TestPartitionedSignal(unittest.TestCase): +class TestSimdSignal(unittest.TestCase): def test(self): width = 16 part_mask = Signal(3) # divide into 4-bits @@ -1001,7 +1001,7 @@ class TestPartitionedSignal(unittest.TestCase): sim.run() -# TODO: adapt to PartitionedSignal. perhaps a different style? +# TODO: adapt to SimdSignal. perhaps a different style? ''' from nmigen.tests.test_hdl_ast import SignedEnum def test_matches(self) diff --git a/src/ieee754/part_ass/assign.py b/src/ieee754/part_ass/assign.py index abb59962..2a79cbbc 100644 --- a/src/ieee754/part_ass/assign.py +++ b/src/ieee754/part_ass/assign.py @@ -19,7 +19,7 @@ from nmigen.back.pysim import Simulator, Settle from nmutil.extend import ext from ieee754.part_mul_add.partpoints import PartitionPoints -from ieee754.part.partsig import PartitionedSignal +from ieee754.part.partsig import SimdSignal def get_runlengths(pbit, size): @@ -46,22 +46,22 @@ class PartitionedAssign(Elaboratable): def __init__(self, shape, assign, ctx): """Create a ``PartitionedAssign`` operator """ - # work out the length (total of all PartitionedSignals) + # work out the length (total of all SimdSignals) self.assign = assign self.ptype = ctx self.shape = shape mask = ctx.get_mask() - self.output = PartitionedSignal(mask, self.shape, reset_less=True) + self.output = SimdSignal(mask, self.shape, reset_less=True) self.partition_points = self.output.partpoints self.mwidth = len(self.partition_points)+1 def get_chunk(self, y, numparts): x = self.assign - if not isinstance(x, PartitionedSignal): + if not isinstance(x, SimdSignal): # assume Scalar. totally different rules end = numparts * (len(x) // self.mwidth) return x[:end] - # PartitionedSignal: start at partition point + # SimdSignal: start at partition point keys = [0] + list(x.partpoints.keys()) + [len(x)] # get current index and increment it (for next Assign chunk) upto = y[0] @@ -109,7 +109,7 @@ class PartitionedAssign(Elaboratable): return m def ports(self): - if isinstance(self.assign, PartitionedSignal): + if isinstance(self.assign, SimdSignal): return [self.assign.lower(), self.output.lower()] return [self.assign, self.output.lower()] @@ -118,7 +118,7 @@ if __name__ == "__main__": from ieee754.part.test.test_partsig import create_simulator m = Module() mask = Signal(3) - a = PartitionedSignal(mask, 32) + a = SimdSignal(mask, 32) m.submodules.ass = ass = PartitionedAssign(signed(48), a, a.ptype) omask = (1<