From df9869d547bc2d099f3d515d8aa901174482d547 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Jul 2020 23:59:34 +0100 Subject: [PATCH] first attempt running cxxsim --- src/soc/fu/shift_rot/test/test_pipe_caller.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index 6e48cb2c..bbd496ba 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -1,5 +1,10 @@ from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle +from nmigen.back.pysim import Delay, Settle +cxxsim = True +if cxxsim: + from nmigen.sim.cxxsim import Simulator +else: + from nmigen.back.pysim import Simulator from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest @@ -256,9 +261,13 @@ class TestRunner(FHDLTestCase): break sim.add_sync_process(process) - with sim.write_vcd("simulator.vcd", "simulator.gtkw", - traces=[]): + print (dir(sim)) + if cxxsim: sim.run() + else: + with sim.write_vcd("simulator.vcd", "simulator.gtkw", + traces=[]): + sim.run() def check_alu_outputs(self, alu, dec2, sim, code): -- 2.30.2