From dfa8e758c2c7ddf6942c216ba7c59083592a6a21 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Wed, 8 May 2019 03:06:15 +0200 Subject: [PATCH] radeonsi/gfx10: disable clear state Acked-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_pipe.c | 9 +++++---- src/gallium/drivers/radeonsi/si_state.c | 4 ---- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index d1a4fb2325e..2ad164a50ac 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1082,10 +1082,11 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, } /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs - * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. - * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/ - sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 && - sscreen->info.is_amdgpu; + * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. + * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */ + sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 && + sscreen->info.chip_class <= GFX9 && + sscreen->info.is_amdgpu; sscreen->has_distributed_tess = sscreen->info.chip_class >= GFX8 && diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 90d332dcebf..b55a398740d 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5391,10 +5391,6 @@ static void si_init_config(struct si_context *sctx) bool has_clear_state = sscreen->has_clear_state; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - /* GFX6, radeon kernel disabled CLEAR_STATE. */ - assert(has_clear_state || sscreen->info.chip_class == GFX6 || - !sscreen->info.is_amdgpu); - if (!pm4) return; -- 2.30.2