From dfbd499a6231ec3419b9ce403afebf1e524d2e12 Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Fri, 3 Apr 2020 13:24:01 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

---
 7d/e4456e9c8aa69a0914dbb07ea60d356eff6fd5 | 81 +++++++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 7d/e4456e9c8aa69a0914dbb07ea60d356eff6fd5

diff --git a/7d/e4456e9c8aa69a0914dbb07ea60d356eff6fd5 b/7d/e4456e9c8aa69a0914dbb07ea60d356eff6fd5
new file mode 100644
index 0000000..fee6508
--- /dev/null
+++ b/7d/e4456e9c8aa69a0914dbb07ea60d356eff6fd5
@@ -0,0 +1,81 @@
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+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Fri, 03 Apr 2020 13:24:01 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
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+Message-ID: <bug-276-13-mfBF4PQi0I@http.bugs.libre-riscv.org/>
+In-Reply-To: <bug-276-13@http.bugs.libre-riscv.org/>
+References: <bug-276-13@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
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-- 
2.30.2