From dfbdccdb54f17b90c6707ad6d877f4de8d22e738 Mon Sep 17 00:00:00 2001 From: Geoff Keating Date: Sun, 14 May 2000 21:42:32 +0000 Subject: [PATCH] rs6000.c (logical_operand): Rewrite to take MODE into account. * config/rs6000/rs6000.c (logical_operand): Rewrite to take MODE into account. (logical_u_operand): Delete. (non_logical_cint_operand): Rewrite to take MODE into account. (non_logical_u_cint_operand): Delete. (boolean_operator): New function. (print_operand): Add new %q operand. * config/rs6000/rs6000.h (PREDICATE_CODES): Add boolean_operator, remove logical_u_operand and non_logical_u_cint_operand, update logical_operand and non_logical_cint_operand. * config/rs6000/rs6000.md: Rewrite the patterns for performing logical operations to use %q. From-SVN: r33899 --- gcc/ChangeLog | 13 + gcc/config/rs6000/rs6000-protos.h | 1 + gcc/config/rs6000/rs6000.c | 133 ++-- gcc/config/rs6000/rs6000.h | 9 +- gcc/config/rs6000/rs6000.md | 1054 +++++++---------------------- 5 files changed, 334 insertions(+), 876 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 99793e2fe61..f9c8770b264 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,18 @@ 2000-05-14 Geoffrey Keating + * config/rs6000/rs6000.c (logical_operand): Rewrite to take MODE + into account. + (logical_u_operand): Delete. + (non_logical_cint_operand): Rewrite to take MODE into account. + (non_logical_u_cint_operand): Delete. + (boolean_operator): New function. + (print_operand): Add new %q operand. + * config/rs6000/rs6000.h (PREDICATE_CODES): Add boolean_operator, + remove logical_u_operand and non_logical_u_cint_operand, + update logical_operand and non_logical_cint_operand. + * config/rs6000/rs6000.md: Rewrite the patterns for performing + logical operations to use %q. + * config/rs6000/rs6000.md (movsi): Don't modify RTL in-place. (movdi): Make similar to movsi. * config/rs6000/rs6000.h (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): There diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 05201afafca..46415ea560a 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -75,6 +75,7 @@ extern int store_multiple_operation PARAMS ((rtx, enum machine_mode)); extern int branch_comparison_operator PARAMS ((rtx, enum machine_mode)); extern int scc_comparison_operator PARAMS ((rtx, enum machine_mode)); extern int trap_comparison_operator PARAMS ((rtx, enum machine_mode)); +extern int boolean_operator PARAMS ((rtx, enum machine_mode)); extern int includes_lshift_p PARAMS ((rtx, rtx)); extern int includes_rshift_p PARAMS ((rtx, rtx)); extern int registers_ok_for_quad_peep PARAMS ((rtx, rtx)); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 7a8f1b74e7d..700064d0145 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -949,43 +949,22 @@ logical_operand (op, mode) register rtx op; enum machine_mode mode; { - return (gpc_reg_operand (op, mode) - || (GET_CODE (op) == CONST_INT -#if HOST_BITS_PER_WIDE_INT != 32 - && INTVAL (op) > 0 - && INTVAL (op) < ((HOST_WIDE_INT) 1 << 32) -#endif - && ((INTVAL (op) & GET_MODE_MASK (mode) - & (~ (HOST_WIDE_INT) 0xffff)) == 0 - || (INTVAL (op) & GET_MODE_MASK (mode) - & (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) == 0))); -} - -/* Return 1 if the operand is a non-special register or a 32-bit constant - that can be used as the operand of an OR or XOR insn on the RS/6000. */ - -int -logical_u_operand (op, mode) - register rtx op; - enum machine_mode mode; -{ - return (gpc_reg_operand (op, mode) - || (GET_CODE (op) == CONST_INT - && INTVAL (op) > 0 -#if HOST_BITS_PER_WIDE_INT != 32 - && INTVAL (op) < ((HOST_WIDE_INT) 1 << 32) -#endif - && ((INTVAL (op) & GET_MODE_MASK (mode) - & (~ (HOST_WIDE_INT) 0xffff)) == 0 - || (INTVAL (op) & GET_MODE_MASK (mode) - & (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) == 0)) -#if HOST_BITS_PER_WIDE_INT == 32 - || (GET_CODE (op) == CONST_DOUBLE - && CONST_DOUBLE_HIGH (op) == 0 + if (gpc_reg_operand (op, mode)) + return 1; + if (GET_CODE (op) == CONST_INT) + { + unsigned HOST_WIDE_INT cval = INTVAL (op) & GET_MODE_MASK (mode); + return ((cval & (~ (HOST_WIDE_INT) 0xffff)) == 0 + || (cval & (~ (HOST_WIDE_INT) 0xffff0000u)) == 0); + } + else if (GET_CODE (op) == CONST_DOUBLE) + { + return (CONST_DOUBLE_HIGH (op) == 0 && ((CONST_DOUBLE_LOW (op) - & (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) == 0)) -#endif - ); + & (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) == 0)); + } + else + return 0; } /* Return 1 if C is a constant that is not a logical operand (as @@ -996,40 +975,8 @@ non_logical_cint_operand (op, mode) register rtx op; enum machine_mode mode; { - return (GET_CODE (op) == CONST_INT -#if HOST_BITS_PER_WIDE_INT != 32 - && INTVAL (op) < ((HOST_WIDE_INT) 1 << 32) -#endif - && (INTVAL (op) & GET_MODE_MASK (mode) & - (~ (HOST_WIDE_INT) 0xffff)) != 0 - && (INTVAL (op) & GET_MODE_MASK (mode) & - (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) != 0); -} - -/* Return 1 if C is an unsigned 32-bit constant that is not a - logical operand (as above). */ - -int -non_logical_u_cint_operand (op, mode) - register rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; -{ - return ((GET_CODE (op) == CONST_INT - && INTVAL (op) > 0 -#if HOST_BITS_PER_WIDE_INT != 32 - && INTVAL (op) < ((HOST_WIDE_INT) 1 << 32) -#endif - && (INTVAL (op) & GET_MODE_MASK (mode) - & (~ (HOST_WIDE_INT) 0xffff)) != 0 - && (INTVAL (op) & GET_MODE_MASK (mode) - & (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) != 0) -#if HOST_BITS_PER_WIDE_INT == 32 - || (GET_CODE (op) == CONST_DOUBLE - && CONST_DOUBLE_HIGH (op) == 0 - && (CONST_DOUBLE_LOW (op) & (~ (HOST_WIDE_INT) 0xffff)) != 0 - && (CONST_DOUBLE_LOW (op) - & (~ (unsigned HOST_WIDE_INT) 0xffff0000u)) != 0)); -#endif + return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) + && ! logical_operand (op, mode)); } /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the @@ -2963,6 +2910,15 @@ trap_comparison_operator (op, mode) return (GET_RTX_CLASS (GET_CODE (op)) == '<' || GET_CODE (op) == EQ || GET_CODE (op) == NE); } + +int +boolean_operator (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + enum rtx_code code = GET_CODE (op); + return (code == AND || code == IOR || code == XOR); +} /* Return 1 if ANDOP is a mask that has no bits on that are not in the mask required to convert the result of a rotate insn into a shift @@ -3630,6 +3586,43 @@ print_operand (file, x, code) fprintf (file, "%d", REGNO (XEXP (x, 0))); return; + case 'q': + /* This outputs the logical code corresponding to a boolean + expression. The expression may have one or both operands + negated (if one, only the first one). */ + { + int neg, op; + const char *const *t; + const char *s; + enum rtx_code code = GET_CODE (x); + static const char * const tbl[3][3] = { + { "and", "andc", "nor" }, + { "or", "orc", "nand" }, + { "xor", "eqv", "xor" } }; + + if (code == AND) + t = tbl[0]; + else if (code == IOR) + t = tbl[1]; + else if (code == XOR) + t = tbl[2]; + else + output_operand_lossage ("invalid %%q value"); + + if (GET_CODE (XEXP (x, 0)) != NOT) + s = t[0]; + else + { + if (GET_CODE (XEXP (x, 1)) == NOT) + s = t[2]; + else + s = t[1]; + } + + fputs (s, file); + } + return; + case 'R': /* X is a CR register. Print the mask for `mtcrf'. */ if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 9959ab503d0..c2fbb331da2 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2726,10 +2726,8 @@ do { \ {"non_add_cint_operand", {CONST_INT}}, \ {"and_operand", {SUBREG, REG, CONST_INT}}, \ {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ - {"logical_operand", {SUBREG, REG, CONST_INT}}, \ - {"logical_u_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ - {"non_logical_cint_operand", {CONST_INT}}, \ - {"non_logical_u_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ + {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ + {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ {"mask_operand", {CONST_INT}}, \ {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \ {"count_register_operand", {REG}}, \ @@ -2748,7 +2746,8 @@ do { \ {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \ GT, LEU, LTU, GEU, GTU}}, \ {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \ - GT, LEU, LTU, GEU, GTU}}, + GT, LEU, LTU, GEU, GTU}}, \ + {"boolean_operator", {AND, IOR, XOR}}, /* uncomment for disabling the corresponding default options */ /* #define MACHINE_no_sched_interblock */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1f54ec1358a..f58e6a1ead5 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2540,6 +2540,11 @@ [(set_attr "type" "idiv")]) ;; Logical instructions +;; The logical instructions are mostly combined by using match_operator, +;; but the plain AND insns are somewhat different because there is no +;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all +;; those rotate-and-mask operations. Thus, the AND insns come first. + (define_insn "andsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") @@ -2655,92 +2660,6 @@ } }") -(define_insn "*iorsi3_internal1" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") - (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") - (match_operand:SI 2 "logical_operand" "r,K,L")))] - "" - "@ - or %0,%1,%2 - {oril|ori} %0,%1,%b2 - {oriu|oris} %0,%1,%u2" - [(set_attr "length" "4,4,4")]) - -(define_insn "*iorsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] - "! TARGET_POWERPC64" - "@ - or. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ior:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*iorsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ior:SI (match_dup 1) - (match_dup 2)))] - "! TARGET_POWERPC64" - "@ - or. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ior:SI (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -;; Split an IOR that we can't do in one insn into two insns, each of which -;; does one 16-bit part. This is used by combine. - -(define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "non_logical_cint_operand" "")))] - "" - [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) - (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] -" -{ - operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); - operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); -}") - (define_expand "xorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -2762,419 +2681,224 @@ } }") -(define_insn "*xorsi3_internal1" +(define_insn "*boolsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") - (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") - (match_operand:SI 2 "logical_operand" "r,K,L")))] + (match_operator:SI 3 "boolean_operator" + [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") + (match_operand:SI 2 "logical_operand" "r,K,L")]))] "" "@ - xor %0,%1,%2 - {xoril|xori} %0,%1,%b2 - {xoriu|xoris} %0,%1,%u2" - [(set_attr "length" "4,4,4")]) + %q3 %0,%1,%2 + {%q3il|%q3i} %0,%1,%b2 + {%q3iu|%q3is} %0,%1,%u2") -(define_insn "*xorsi3_internal2" +(define_insn "*boolsi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] "! TARGET_POWERPC64" "@ - xor. %3,%1,%2 + %q4. %3,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (clobber (match_scratch:SI 3 ""))] "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (xor:SI (match_dup 1) - (match_dup 2))) + [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") -(define_insn "*xorsi3_internal3" +(define_insn "*boolsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (xor:SI (match_dup 1) - (match_dup 2)))] + (match_dup 4))] "! TARGET_POWERPC64" "@ - xor. %0,%1,%2 + %q4. %0,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (xor:SI (match_dup 1) (match_dup 2)))] + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (match_operator:SI 4 "boolean_operator" + [(match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (match_dup 4))] "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (xor:SI (match_dup 1) - (match_dup 2))) + [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -;; Split an XOR that we can't do in one insn into two insns, each of which -;; does one 16-bit part. This is used by combine. +;; Split an logical operation that we can't do in one insn into two insns, +;; each of which does one 16-bit part. This is used by combine. (define_split [(set (match_operand:SI 0 "gpc_reg_operand" "") - (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "non_logical_cint_operand" "")))] + (match_operator:SI 3 "boolean_operator" + [(match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "non_logical_cint_operand" "")]))] "" - [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) - (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (match_dup 5))] " { - operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); - operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); + rtx i; + i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); + operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, + operands[1], i); + i = GEN_INT (INTVAL (operands[2]) & 0xffff); + operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, + operands[0], i); }") -(define_insn "*eqvsi3_internal1" +(define_insn "*boolcsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r"))))] - "" - "eqv %0,%1,%2") - -(define_insn "*eqvsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] - "! TARGET_POWERPC64" - "@ - eqv. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (not:SI (xor:SI (match_dup 1) - (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*eqvsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (not:SI (xor:SI (match_dup 1) (match_dup 2))))] - "! TARGET_POWERPC64" - "@ - eqv. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_short_operand" ""))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (not:SI (xor:SI (match_dup 1) - (match_dup 2))))] - "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (not:SI (xor:SI (match_dup 1) - (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "*andcsi3_internal1" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")))] + (match_operator:SI 3 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "logical_operand" "r")]))] "" - "andc %0,%2,%1") + "%q3 %0,%2,%1") -(define_insn "*andcsi3_internal2" +(define_insn "*boolcsi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] "! TARGET_POWERPC64" "@ - andc. %3,%2,%1 + %q4. %3,%2,%1 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")]) + (const_int 0))) (clobber (match_scratch:SI 3 ""))] "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (and:SI (not:SI (match_dup 1)) - (match_dup 2))) + [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") -(define_insn "*andcsi3_internal3" +(define_insn "*boolcsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (not:SI (match_dup 1)) - (match_dup 2)))] - "! TARGET_POWERPC64" - "@ - andc. %0,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (not:SI (match_dup 1)) - (match_dup 2)))] - "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (and:SI (not:SI (match_dup 1)) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "*iorcsi3_internal1" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")))] - "" - "orc %0,%2,%1") - -(define_insn "*iorcsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (match_dup 4))] "! TARGET_POWERPC64" "@ - orc. %3,%2,%1 + %q4. %0,%2,%1 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ior:SI (not:SI (match_dup 1)) - (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*iorcsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) - (match_operand:SI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] - "! TARGET_POWERPC64" - "@ - orc. %0,%2,%1 - #" - [(set_attr "type" "compare")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (match_operand:SI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (not:SI (match_dup 1)) - (match_dup 2)))] + (match_dup 4))] "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ior:SI (not:SI (match_dup 1)) - (match_dup 2))) + [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -(define_insn "*nandsi3_internal1" +(define_insn "*boolccsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] + (match_operator:SI 3 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "logical_operand" "r"))]))] "" - "nand %0,%1,%2") + "%q3 %0,%1,%2") -(define_insn "*nandsi3_internal2" +(define_insn "*boolccsi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) + (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] "! TARGET_POWERPC64" "@ - nand. %3,%1,%2 + %q4. %3,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]) + (const_int 0))) (clobber (match_scratch:SI 3 ""))] "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ior:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2)))) + [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") -(define_insn "*nandsi3_internal3" +(define_insn "*boolccsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) + (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (ior:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2))))] - "! TARGET_POWERPC64" - "@ - nand. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (ior:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2))))] - "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ior:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "*norsi3_internal1" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] - "" - "nor %0,%1,%2") - -(define_insn "*norsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r"))] + (match_dup 4))] "! TARGET_POWERPC64" "@ - nor. %3,%1,%2 + %q4. %0,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (and:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*norsi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) + (compare:CC (match_operator:SI 4 "boolean_operator" + [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) + (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2))))] - "! TARGET_POWERPC64" - "@ - nor. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2))))] + (match_dup 4))] "! TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (and:SI (not:SI (match_dup 1)) - (not:SI (match_dup 2)))) + [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] @@ -7336,574 +7060,302 @@ (define_expand "iordi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_u_cint_operand" "")))] + (match_operand:DI 2 "reg_or_cint_operand" "")))] "TARGET_POWERPC64" " { - if (GET_CODE (operands[2]) == CONST_INT - && ! logical_u_operand (operands[2], DImode)) + if (non_logical_cint_operand (operands[2], DImode)) { - HOST_WIDE_INT value = INTVAL (operands[2]); - rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) - ? operands[0] : gen_reg_rtx (DImode)); - - emit_insn (gen_iordi3 (tmp, operands[1], - GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); - emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); - DONE; - } - else if (GET_CODE (operands[2]) == CONST_DOUBLE - && ! logical_u_operand (operands[2], DImode)) - { - HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); + HOST_WIDE_INT value; rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (DImode)); - emit_insn (gen_iordi3 (tmp, operands[1], - immed_double_const (value - & (~ (HOST_WIDE_INT) 0xffff), - 0, DImode))); + if (GET_CODE (operands[2]) == CONST_INT) + { + value = INTVAL (operands[2]); + emit_insn (gen_iordi3 (tmp, operands[1], + GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); + } + else if (GET_CODE (operands[2]) == CONST_DOUBLE) + { + value = CONST_DOUBLE_LOW (operands[2]); + emit_insn (gen_iordi3 (tmp, operands[1], + immed_double_const (value + & (~ (HOST_WIDE_INT) 0xffff), + 0, DImode))); + } emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; } }") -(define_insn "*iordi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") - (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r") - (match_operand:DI 2 "logical_u_operand" "r,K,JF")))] - "TARGET_POWERPC64" - "@ - or %0,%1,%2 - ori %0,%1,%b2 - oris %0,%1,%u2") - -(define_insn "*iordi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] - "TARGET_POWERPC64" - "@ - or. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ior:DI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*iordi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (ior:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64" - "@ - or. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ior:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ior:DI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -;; Split an IOR that we can't do in one insn into two insns, each of which -;; does one 16-bit part. This is used by combine. - -(define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "non_logical_u_cint_operand" "")))] - "TARGET_POWERPC64" - [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3))) - (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))] -" -{ - if (GET_CODE (operands[2]) == CONST_DOUBLE) - { - HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); - operands[3] = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), - 0, DImode); - operands[4] = GEN_INT (value & 0xffff); - } - else - { - operands[3] = GEN_INT (INTVAL (operands[2]) - & (~ (HOST_WIDE_INT) 0xffff)); - operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); - } -}") - (define_expand "xordi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_u_cint_operand" "")))] + (match_operand:DI 2 "reg_or_cint_operand" "")))] "TARGET_POWERPC64" " { - if (GET_CODE (operands[2]) == CONST_INT - && ! logical_u_operand (operands[2], DImode)) + if (non_logical_cint_operand (operands[2], DImode)) { - HOST_WIDE_INT value = INTVAL (operands[2]); - rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) - ? operands[0] : gen_reg_rtx (DImode)); - - emit_insn (gen_xordi3 (tmp, operands[1], - GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); - emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); - DONE; - } - else if (GET_CODE (operands[2]) == CONST_DOUBLE - && ! logical_u_operand (operands[2], DImode)) - { - HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); + HOST_WIDE_INT value; rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (DImode)); - emit_insn (gen_xordi3 (tmp, operands[1], - immed_double_const (value - & (~ (HOST_WIDE_INT) 0xffff), - 0, DImode))); + if (GET_CODE (operands[2]) == CONST_INT) + { + value = INTVAL (operands[2]); + emit_insn (gen_xordi3 (tmp, operands[1], + GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); + } + else if (GET_CODE (operands[2]) == CONST_DOUBLE) + { + value = CONST_DOUBLE_LOW (operands[2]); + emit_insn (gen_xordi3 (tmp, operands[1], + immed_double_const (value + & (~ (HOST_WIDE_INT) 0xffff), + 0, DImode))); + } emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; } }") -(define_insn "*xordi3_internal1" +(define_insn "*booldi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") - (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r") - (match_operand:DI 2 "logical_u_operand" "r,K,JF")))] + (match_operator:DI 3 "boolean_operator" + [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") + (match_operand:DI 2 "logical_operand" "r,K,JF")]))] "TARGET_POWERPC64" "@ - xor %0,%1,%2 - xori %0,%1,%b2 - xoris %0,%1,%u2") + %q3 %0,%1,%2 + %q3i %0,%1,%b2 + %q3is %0,%1,%u2") -(define_insn "*xordi3_internal2" +(define_insn "*booldi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(match_operand:DI 1 "gpc_reg_operand" "%r,r") + (match_operand:DI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_POWERPC64" "@ - xor. %3,%1,%2 + %q4. %3,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(match_operand:DI 1 "gpc_reg_operand" "%r,r") + (match_operand:DI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (clobber (match_scratch:DI 3 ""))] "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (xor:DI (match_dup 1) (match_dup 2))) + [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") -(define_insn "*xordi3_internal3" +(define_insn "*booldi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(match_operand:DI 1 "gpc_reg_operand" "%r,r") + (match_operand:DI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (xor:DI (match_dup 1) (match_dup 2)))] + (match_dup 4))] "TARGET_POWERPC64" "@ - xor. %0,%1,%2 + %q4. %0,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (xor:DI (match_dup 1) (match_dup 2)))] + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (match_operator:DI 4 "boolean_operator" + [(match_operand:DI 1 "gpc_reg_operand" "%r,r") + (match_operand:DI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (match_dup 4))] "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (xor:DI (match_dup 1) (match_dup 2))) + [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -;; Split an XOR that we can't do in one insn into two insns, each of which -;; does one 16-bit part. This is used by combine. +;; Split an logical operation that we can't do in one insn into two insns, +;; each of which does one 16-bit part. This is used by combine. (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") - (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "non_logical_u_cint_operand" "")))] + (match_operator:DI 3 "boolean_operator" + [(match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "non_logical_cint_operand" "")]))] "TARGET_POWERPC64" - [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3))) - (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))] + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (match_dup 5))] " { + rtx i3,i4; + if (GET_CODE (operands[2]) == CONST_DOUBLE) { HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); - operands[3] = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), + i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), 0, DImode); - operands[4] = GEN_INT (value & 0xffff); + i4 = GEN_INT (value & 0xffff); } else { - operands[3] = GEN_INT (INTVAL (operands[2]) + i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); - operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); + i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); } + operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, + operands[1], i3); + operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, + operands[0], i4); }") -(define_insn "*eqvdi3_internal1" +(define_insn "*boolcdi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") - (match_operand:DI 2 "gpc_reg_operand" "r"))))] - "TARGET_POWERPC64" - "eqv %0,%1,%2") - -(define_insn "*eqvdi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] - "TARGET_POWERPC64" - "@ - eqv. %3,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (not:DI (xor:DI (match_dup 1) (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*eqvdi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (not:DI (xor:DI (match_dup 1) (match_dup 2))))] - "TARGET_POWERPC64" - "@ - eqv. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (not:DI (xor:DI (match_dup 1) (match_dup 2))))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (not:DI (xor:DI (match_dup 1) (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "*andcdi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) - (match_operand:DI 2 "gpc_reg_operand" "r")))] + (match_operator:DI 3 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (match_operand:DI 2 "logical_operand" "r")]))] "TARGET_POWERPC64" - "andc %0,%2,%1") + "%q3 %0,%1,%2") -(define_insn "*andcdi3_internal2" +(define_insn "*boolcdi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) + (match_operand:DI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_POWERPC64" "@ - andc. %3,%2,%1 + %q4. %3,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (match_operand:DI 2 "gpc_reg_operand" "r")]) + (const_int 0))) (clobber (match_scratch:DI 3 ""))] "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (and:DI (not:DI (match_dup 1)) (match_dup 2))) + [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") -(define_insn "*andcdi3_internal3" +(define_insn "*boolcdi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) + (match_operand:DI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (and:DI (not:DI (match_dup 1)) (match_dup 2)))] + (match_dup 4))] "TARGET_POWERPC64" "@ - andc. %0,%2,%1 + %q4. %0,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (not:DI (match_dup 1)) (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (and:DI (not:DI (match_dup 1)) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "*iorcdi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) - (match_operand:DI 2 "gpc_reg_operand" "r")))] - "TARGET_POWERPC64" - "orc %0,%2,%1") - -(define_insn "*iorcdi3_inernal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] - "TARGET_POWERPC64" - "@ - orc. %3,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ior:DI (not:DI (match_dup 1)) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*iorcdi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) - (match_operand:DI 2 "gpc_reg_operand" "r,r")) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) + (match_operand:DI 2 "gpc_reg_operand" "r,r")]) + (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (ior:DI (not:DI (match_dup 1)) (match_dup 2)))] - "TARGET_POWERPC64" - "@ - orc. %0,%2,%1 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (match_operand:DI 2 "gpc_reg_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ior:DI (not:DI (match_dup 1)) (match_dup 2)))] + (match_dup 4))] "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ior:DI (not:DI (match_dup 1)) (match_dup 2))) + [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") -(define_insn "*nanddi3_internal1" +(define_insn "*boolccdi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] + (match_operator:DI 3 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (not:DI (match_operand:DI 2 "logical_operand" "r"))]))] "TARGET_POWERPC64" - "nand %0,%1,%2") + "%q3 %0,%1,%2") -(define_insn "*nanddi3_internal2" +(define_insn "*boolccdi3_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) + (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) + (const_int 0))) (clobber (match_scratch:DI 3 "=r,r"))] "TARGET_POWERPC64" "@ - nand. %3,%1,%2 + %q4. %3,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) + (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]) + (const_int 0))) (clobber (match_scratch:DI 3 ""))] "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2)))) + [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") -(define_insn "*nanddi3_internal3" +(define_insn "*boolccdi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) + (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) + (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] - "TARGET_POWERPC64" - "@ - nand. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2)))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_insn "*nordi3_internal1" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] - "TARGET_POWERPC64" - "nor %0,%1,%2") - -(define_insn "*nordi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r"))] + (match_dup 4))] "TARGET_POWERPC64" "@ - nor. %3,%1,%2 + %q4. %0,%1,%2 #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2)))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*nordi3_internal3" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))) - (const_int 0))) + (compare:CC (match_operator:DI 4 "boolean_operator" + [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) + (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) + (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] - "TARGET_POWERPC64" - "@ - nor. %0,%1,%2 - #" - [(set_attr "type" "compare") - (set_attr "length" "4,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) - (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] + (match_dup 4))] "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2)))) + [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") - + ;; Now define ways of moving data around. ;; Elf specific ways of loading addresses for non-PIC code. -- 2.30.2