From dfdd8edb91a9b0bb7fa3ae3b7b4f1cc95d047d81 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 Apr 2020 13:00:34 +0100 Subject: [PATCH] convert power_decoder2 Data to Record-based --- src/soc/decoder/power_decoder2.py | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 5524ce1e..63da5497 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -3,7 +3,7 @@ based on Anton Blanchard microwatt decode2.vhdl """ -from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl +from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record from nmigen.cli import rtlil from soc.decoder.power_decoder import create_pdecode @@ -61,16 +61,17 @@ class DecodeA(Elaboratable): return m -class Data: - def __init__(self, width, name): - - self.data = Signal(width, name=name, reset_less=True) - self.ok = Signal(name="%s_ok" % name, reset_less=True) +class Data(Record): - def eq(self, rhs): - return [self.data.eq(rhs.data), - self.ok.eq(rhs.ok)] + def __init__(self, width, name): + name_ok = "%s_ok" % name + layout = ((name, width), (name_ok, 1)) + Record.__init__(self, layout) + self.data = getattr(self, name) # convenience + self.ok = getattr(self, name_ok) # convenience + self.data.reset_less = True # grrr + self.reset_less = True # grrr def ports(self): return [self.data, self.ok] @@ -343,6 +344,7 @@ class Decode2ToExecute1Type: self.imm_data.ports() # + self.xerc.ports() + class PowerDecode2(Elaboratable): def __init__(self, dec): -- 2.30.2