From e04530e0c42fe9e1322a9877cb68860669a5f3f3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 24 Sep 2018 01:15:33 +0200 Subject: [PATCH] test/test_targets: update and reorganize targets --- test/test_targets.py | 41 ++++++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/test/test_targets.py b/test/test_targets.py index 591353ec..37c174b6 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -18,27 +18,42 @@ def build_test(socs): class TestTargets(unittest.TestCase): - def test_arty(self): - from litex.boards.targets.arty import BaseSoC, MiniSoC - errors = build_test([BaseSoC(), MiniSoC()]) - self.assertEqual(errors, 0) - + # altera boards def test_de0nano(self): from litex.boards.targets.de0nano import BaseSoC errors = build_test([BaseSoC()]) self.assertEqual(errors, 0) - def test_kc705(self): - from litex.boards.targets.kc705 import BaseSoC, MiniSoC - errors = build_test([BaseSoC(), MiniSoC()]) - self.assertEqual(errors, 0) - + # xilinx boards def test_minispartan6(self): from litex.boards.targets.minispartan6 import BaseSoC errors = build_test([BaseSoC()]) self.assertEqual(errors, 0) + def test_arty(self): + from litex.boards.targets.arty import BaseSoC, EthernetSoC + errors = build_test([BaseSoC(), EthernetSoC()]) + self.assertEqual(errors, 0) + + def test_nexys4ddr(self): + from litex.boards.targets.nexys4ddr import BaseSoC + errors = build_test([BaseSoC()]) + self.assertEqual(errors, 0) + def test_nexys_video(self): - from litex.boards.targets.nexys_video import BaseSoC, MiniSoC - errors = build_test([BaseSoC(), MiniSoC()]) - self.assertEqual(errors, 0) \ No newline at end of file + from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC + errors = build_test([BaseSoC(), EthernetSoC()]) + self.assertEqual(errors, 0) + + def test_genesys2(self): + from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC + errors = build_test([BaseSoC(), EthernetSoC()]) + self.assertEqual(errors, 0) + + def test_kc705(self): + from litex.boards.targets.kc705 import BaseSoC, EthernetSoC + errors = build_test([BaseSoC(), EthernetSoC()]) + self.assertEqual(errors, 0) + + # lattice boards + -- 2.30.2