From e0641eb5dea0ba6c5cc7f196201edd040f99c52a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 23 Sep 2021 15:05:12 +0100 Subject: [PATCH] add load-immediate unit test --- src/openpower/decoder/isa/test_caller_fp.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py index 6dc4fd90..f5789d86 100644 --- a/src/openpower/decoder/isa/test_caller_fp.py +++ b/src/openpower/decoder/isa/test_caller_fp.py @@ -38,6 +38,22 @@ class DecoderTestCase(FHDLTestCase): print("FPR 1", sim.fpr(1)) self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64)) + def test_fpload_imm(self): + """>>> lst = ["lfs 1, 8(1)", + ] + """ + lst = ["lfs 1, 8(1)", + ] + initial_mem = {0x0000: (0x42013333, 8), + 0x0008: (0x42026666, 8), + 0x0020: (0x1828384822324252, 8), + } + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_mem=initial_mem) + print("FPR 1", sim.fpr(1)) + self.assertEqual(sim.fpr(1), SelectableInt(0x40404cccc0000000, 64)) + def test_fpload2(self): """>>> lst = ["lfsx 1, 0, 0", ] -- 2.30.2