From e089b99dee2b6507ec008486da5fd1f43b7296eb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Oct 2018 10:56:30 +0100 Subject: [PATCH] allow 4 CSR entries to be set at a time, on RV64 --- riscv/processor.cc | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index b95c030..d87da25 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -374,10 +374,16 @@ void processor_t::set_csr(int which, reg_t val) fprintf(stderr, "set REGCFG %d %lx\n", tbidx, val); // lower 16 bits go into even, upper into odd... state.sv_csrs[tbidx].u = get_field(val, 0xffff); - state.sv_csrs[tbidx+1].u = get_field(val, 0xffff0000); + state.sv_csrs[tbidx+1].u = get_field(val, 0xffff<<16); + int clroffset = 0; + if (xlen == 64) + { + state.sv_csrs[tbidx+2].u = get_field(val, 0xffff<<32); + state.sv_csrs[tbidx+3].u = get_field(val, 0xffff<<48); + } // clear out all CSRs above the one(s) being set: this ensures that // when it comes to context-switching, it's clear what needs to be saved - for (int i = tbidx+2; i < 16; i++) + for (int i = tbidx+clroffset; i < 16; i++) { fprintf(stderr, "clr REGCFG %d\n", i); state.sv_csrs[i].u = 0; @@ -429,7 +435,13 @@ void processor_t::set_csr(int which, reg_t val) int tbidx = (which - CSR_SVPREDCFG0) * 2; state.sv_pred_csrs[tbidx].u = get_field(val, 0xffff); state.sv_pred_csrs[tbidx+1].u = get_field(val, 0xffff0000); - for (int i = tbidx+2; i < 16; i++) + int clroffset = 0; + if (xlen == 64) + { + state.sv_pred_csrs[tbidx+2].u = get_field(val, 0xffff<<32); + state.sv_pred_csrs[tbidx+3].u = get_field(val, 0xffff<<48); + } + for (int i = tbidx+clroffset; i < 16; i++) { state.sv_pred_csrs[i].u = 0; } -- 2.30.2