From e0a4e25f938953201fef2bf702e2e709451200f4 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 22 Jun 2009 15:39:37 -0700 Subject: [PATCH] i965: Fix packed depth/stencil textures to be Y-tiled as well. Fixes shadowtex.c. And an assert is added to catch this sooner next time. --- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 ++ src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 4784254bc7d..67c39e509c5 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -244,6 +244,8 @@ static void emit_depthbuffer(struct brw_context *brw) return; } + assert(region->tiling != I915_TILING_X); + BEGIN_BATCH(len, IGNORE_CLIPRECTS); OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 660d7e5350b..1ef2fe86d1f 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -115,7 +115,8 @@ intel_miptree_create(struct intel_context *intel, if (intel->use_texture_tiling && compress_byte == 0 && intel->intelScreen->kernel_exec_fencing) { if (IS_965(intel->intelScreen->deviceID) && - internal_format == GL_DEPTH_COMPONENT) + (internal_format == GL_DEPTH_COMPONENT || + internal_format == GL_DEPTH_STENCIL_EXT)) tiling = I915_TILING_Y; else tiling = I915_TILING_X; -- 2.30.2