From e0bcb57d3d0b905502502733ffd9b9531d2cc8df Mon Sep 17 00:00:00 2001
From: Jan Kowalewski <jkowalewski@antmicro.com>
Date: Thu, 13 Feb 2020 16:41:11 +0100
Subject: [PATCH] wishbone: add extracting module signals to the top

---
 litex/soc/interconnect/wishbone.py | 54 ++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index a77d60cc..a1f6d249 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -13,6 +13,7 @@ from migen.genlib.misc import split, displacer, chooser, WaitTimer
 from migen.genlib.fsm import FSM, NextState
 
 from litex.soc.interconnect import csr
+from litex.build.generic_platform import *
 
 # TODO: rewrite without FlipFlop
 
@@ -69,6 +70,59 @@ class Interface(Record):
         yield from self._do_transaction()
         return (yield self.dat_r)
 
+    def _signals_in_channels(self, channels):
+        for channel_name in channels:
+            s = getattr(self, channel_name)
+            for l in _layout:
+                if l[0] == channel_name:
+                    yield channel_name, s.nbits, l[2]
+
+    def to_pads(self, bus_name='wb'):
+        wb_bus = {}
+        for name, width, direction in self._signals_in_channels(['adr', 'dat_w', 'dat_r',
+                                                                'sel', 'cyc', 'stb', 'ack',
+                                                                'we', 'cti', 'bte', 'err']):
+            signal_name = name
+            wb_bus[signal_name] = width
+
+        signals = []
+        for pad in wb_bus:
+            signals.append(Subsignal(pad, Pins(wb_bus[pad])))
+
+        pads = [
+                (bus_name , 0) + tuple(signals)
+                ]
+        print(pads)
+        return pads
+
+    def connect_to_pads(self, module, platform, bus_name, mode='master'):
+
+        def _get_signals(pads, name):
+            signal_name = name
+            wb_signal = getattr(self, signal_name)
+            pads_signal = getattr(pads, signal_name)
+            return pads_signal, wb_signal
+
+        wb_pads = self.to_pads(bus_name)
+        platform.add_extension(wb_pads)
+        pads = platform.request(bus_name)
+
+        for name, width, direction in self._signals_in_channels(['adr', 'dat_w', 'dat_r',
+                                                                           'sel', 'cyc', 'stb', 'ack',
+                                                                           'we', 'cti', 'bte', 'err']):
+            pads_signal, wb_signal = _get_signals(pads, name)
+
+            if mode == 'master':
+                if direction == DIR_M_TO_S:
+                    module.comb += pads_signal.eq(wb_signal)
+                else:
+                    module.comb += wb_signal.eq(pads_signal)
+            else:
+                if direction == DIR_S_TO_M:
+                    module.comb += pads_signal.eq(wb_signal)
+                else:
+                    module.comb += wb_signal.eq(pads_signal)
+
 
 class InterconnectPointToPoint(Module):
     def __init__(self, master, slave):
-- 
2.30.2