From e0c867db5349a00e0041a0a50a9ababdc3a170fe Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 4 Feb 2014 23:00:48 +0100 Subject: [PATCH] presentation progress --- manual/PRESENTATION_ExSyn.tex | 65 +++++++++++++++++++++++++++++++- manual/PRESENTATION_Intro.tex | 71 +++++++++++++++++++---------------- manual/PRESENTATION_Prog.tex | 2 +- 3 files changed, 104 insertions(+), 34 deletions(-) diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index a889069b4..4c19c48b9 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -423,7 +423,70 @@ more advanced ABC features. It is also possible to write the design with \subsection{Other special-purpose mapping commands} \begin{frame}{\subsecname} -TBD +\begin{block}{\tt dfflibmap} +This command maps the internal register cell types to the register types +described in a liberty file. +\end{block} + +\bigskip +\begin{block}{\tt hilomap} +Some architectures require special driver cells for driving a constant hi or lo +value. This command replaces simple constants with instances of such driver cells. +\end{block} + +\bigskip +\begin{block}{\tt iopadmap} +Top-level input/outputs must usually be implemented using special I/O-pad cells. +This command inserts this cells to the design. +\end{block} +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{Example Synthesis Script} + +\begin{frame}[fragile]{\subsecname} +\begin{columns} +\column[t]{4cm} +\begin{lstlisting}[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont] +# read and elaborate design +read_verilog cpu_top.v cpu_ctrl.v cpu_regs.v +read_verilog -D WITH_MULT cpu_alu.v +hierarchy -check -top cpu_top + +# high-level synthesis +proc; opt; memory -nomap;; fsm; opt + +# substitute block rams +techmap -map map_rams.v + +# map remaining memories +memory_map + +# low-level synthesis +techmap; opt; flatten;; abc -lut6 +techmap -map map_xl_cells.v + +# add clock buffers +select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d +iopadmap -inpad BUFGP O:I @xl_clocks + +# add io buffers +select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d +iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks + +# write synthesis results +write_edif synth.edif +\end{lstlisting} +\column[t]{6cm} +\begin{block}{Teaser / Outlook} +\small\parbox{6cm}{ +This script contains some constructs that have not been explained +so far, such as the weird {\tt select} expressions at the end of +the script. They are only one of the topics covered in Section 3 +``Advanced Synthesis'' of this presentation.} +\end{block} +\end{columns} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 30565405b..1d0a60619 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -247,6 +247,23 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Example Problem} + +\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v} +\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v} +\end{frame} + +\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib} +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib} +\end{columns} +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + \subsection{Example Synthesis Script} \begin{frame}[t]{\subsecname} @@ -256,8 +273,8 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des \begin{minipage}[t]{6cm} \tt\scriptsize \# read design\\ -\boxalert<1>{read\_verilog mydesign.v}\\ -\boxalert<2>{hierarchy -check -top mytop} +\boxalert<1>{read\_verilog counter.v}\\ +\boxalert<2>{hierarchy -check -top counter} \medskip \# the high-level stuff\\ @@ -291,8 +308,8 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des \vskip1cm \begin{block}{Command: \tt -\only<1>{read\_verilog mydesign.v}% -\only<2>{hierarchy -check -top mytop}% +\only<1>{read\_verilog counter.v}% +\only<2>{hierarchy -check -top counter}% \only<3>{proc}% \only<4>{opt}% \only<5>{memory}% @@ -306,46 +323,49 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des \only<13>{clean}% \only<14>{write\_verilog synth.v}} \only<1>{ - TBD + Read Verilog source file and convert to internal representation. }% \only<2>{ - TBD + Elaborate the design hierarchy. Should alsways be the first + command after reading the design. }% \only<3>{ - TBD + Convert ``processes'' (the internal representation of behavioral + Verilog code) into multiplexers and registers. }% \only<4>{ - TBD + Perform some basic optimizations and cleanups. }% \only<5>{ - TBD + Analyze memories and create circuits to implement them. }% \only<6>{ - TBD + Perform some basic optimizations and cleanups. }% \only<7>{ - TBD + Analyze and optimize finite state machines. }% \only<8>{ - TBD + Perform some basic optimizations and cleanups. }% \only<9>{ - TBD + Map coarse-grain RTL cells (adders, etc.) to fine-grain + logic gates (AND, OR, NOT, etc.). }% \only<10>{ - TBD + Perform some basic optimizations and cleanups. }% \only<11>{ - TBD + Map registers to available hardware flip-flops. }% \only<12>{ - TBD + Map logix to available hardware gates. }% \only<13>{ - TBD + Clean up the design (just the last step of {\tt opt}). }% \only<14>{ - TBD + Write final synthesis result to output file. }% \end{block} @@ -355,19 +375,6 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des \subsection{Running the Synthesis Script} -\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v} -\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v} -\end{frame} - -\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib} -\begin{columns} -\column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib} -\column[t]{5cm} -\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib} -\end{columns} -\end{frame} - \begin{frame}[t, fragile]{\subsecname{} -- Step 1/4} \begin{verbatim} read_verilog counter.v @@ -409,7 +416,7 @@ clean %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{More Yosys Commands} +\subsection{Yosys Commands} \begin{frame}[fragile]{\subsecname{} 1/3} Command reference: diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index 5b74a5e75..250d2c373 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -93,6 +93,6 @@ if (module->processes.size() != 0 || module->memories.size() != 0) \end{lstlisting} \bigskip -So we only discuss this version of RTLIL in this presentation. +For simplicity we only discuss this version of RTLIL in this presentation. \end{frame} -- 2.30.2