From e111348c41612bd1188edff4429097a7c55b6628 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 11 Oct 2022 15:05:58 +0100
Subject: [PATCH] add Post-increment version of fixedstore.mdwn

---
 openpower/isa/pifixedload.mdwn  |   2 +-
 openpower/isa/pifixedstore.mdwn | 141 ++++++++++++++++++++++++++++++++
 2 files changed, 142 insertions(+), 1 deletion(-)
 create mode 100644 openpower/isa/pifixedstore.mdwn

diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn
index 3f74981d..b5671cbc 100644
--- a/openpower/isa/pifixedload.mdwn
+++ b/openpower/isa/pifixedload.mdwn
@@ -4,7 +4,7 @@
 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
 
 <!-- Note that these pages also define equivalent store instructions, -->
-<!-- these are described in fixedstore.mdwn -->
+<!-- these are described in pifixedstore.mdwn -->
 
 
 
diff --git a/openpower/isa/pifixedstore.mdwn b/openpower/isa/pifixedstore.mdwn
new file mode 100644
index 00000000..a8060e56
--- /dev/null
+++ b/openpower/isa/pifixedstore.mdwn
@@ -0,0 +1,141 @@
+<!-- This defines DRAFT instructions described in SV -->
+
+<!-- This defines instructions that store from a register to RAM -->
+<!-- Effective Address is always RA, and the usual EA is stored late in RA -->
+
+# Store Byte with Update
+
+D-Form
+
+* stbu RS,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(D)
+    ea <- (RA)
+    MEM(ra, 1) <- (RS)[XLEN-8:XLEN-1]
+    RA <- EA
+
+Special Registers Altered:
+
+    None
+
+# Store Byte with Update Indexed
+
+X-Form
+
+* stbux RS,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA) + (RB)
+    ea <- (RA)
+    MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
+    RA <- EA
+
+Special Registers Altered:
+
+    None
+
+# Store Halfword with Update
+
+D-Form
+
+* sthu RS,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(D)
+    ea <- (RA)
+    MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
+    RA <- EA
+
+Special Registers Altered:
+
+    None
+
+# Store Halfword with Update Indexed
+
+X-Form
+
+* sthux RS,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA) + (RB)
+    ea <- (RA)
+    MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
+    RA <- EA
+
+Special Registers Altered:
+
+    None
+
+# Store Word with Update
+
+D-Form
+
+* stwu RS,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(D)
+    ea <- (RA)
+    MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
+    RA <- EA
+
+Special Registers Altered:
+
+    None
+
+# Store Word with Update Indexed
+
+X-Form
+
+* stwux RS,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA) + (RB)
+    ea <- (RA)
+    MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
+    RA <- EA
+
+Special Registers Altered:
+
+    None
+
+# Store Doubleword with Update
+
+DS-Form
+
+* stdu RS,DS(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(DS || 0b00)
+    ea <- (RA)
+    MEM(ea, 8) <- (RS)
+    RA <- EA
+
+Special Registers Altered:
+
+    None
+
+# Store Doubleword with Update Indexed
+
+X-Form
+
+* stdux RS,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA) + (RB)
+    ea <- (RA)
+    MEM(ea, 8) <- (RS)
+    RA <- EA
+
+Special Registers Altered:
+
+    None
+
-- 
2.30.2