From e1319924aa95cd55869a22e122b4c2344c7d3feb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 19 Apr 2017 10:37:59 +0200 Subject: [PATCH] soc: move uart to a single file --- litex/soc/cores/{uart/core.py => uart.py} | 7 +++++++ litex/soc/cores/uart/__init__.py | 1 - litex/soc/cores/uart/bridge.py | 10 ---------- 3 files changed, 7 insertions(+), 11 deletions(-) rename litex/soc/cores/{uart/core.py => uart.py} (94%) delete mode 100644 litex/soc/cores/uart/__init__.py delete mode 100644 litex/soc/cores/uart/bridge.py diff --git a/litex/soc/cores/uart/core.py b/litex/soc/cores/uart.py similarity index 94% rename from litex/soc/cores/uart/core.py rename to litex/soc/cores/uart.py index b295b562..56ead529 100644 --- a/litex/soc/cores/uart/core.py +++ b/litex/soc/cores/uart.py @@ -5,6 +5,7 @@ from litex.gen.genlib.cdc import MultiReg from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr_eventmanager import * from litex.soc.interconnect import stream +from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge class RS232PHYRX(Module): @@ -176,3 +177,9 @@ class UART(Module, AutoCSR): # Generate RX IRQ when tx_fifo becomes non-empty self.ev.rx.trigger.eq(~rx_fifo.source.valid) ] + + +class UARTWishboneBridge(WishboneStreamingBridge): + def __init__(self, pads, clk_freq, baudrate=115200): + self.submodules.phy = RS232PHY(pads, clk_freq, baudrate) + WishboneStreamingBridge.__init__(self, self.phy, clk_freq) diff --git a/litex/soc/cores/uart/__init__.py b/litex/soc/cores/uart/__init__.py deleted file mode 100644 index 848ae419..00000000 --- a/litex/soc/cores/uart/__init__.py +++ /dev/null @@ -1 +0,0 @@ -from litex.soc.cores.uart.core import UART, RS232PHY, RS232PHYModel diff --git a/litex/soc/cores/uart/bridge.py b/litex/soc/cores/uart/bridge.py deleted file mode 100644 index 6f47779a..00000000 --- a/litex/soc/cores/uart/bridge.py +++ /dev/null @@ -1,10 +0,0 @@ -from litex.gen import * - -from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge -from litex.soc.cores.uart.core import RS232PHY - - -class UARTWishboneBridge(WishboneStreamingBridge): - def __init__(self, pads, clk_freq, baudrate=115200): - self.submodules.phy = RS232PHY(pads, clk_freq, baudrate) - WishboneStreamingBridge.__init__(self, self.phy, clk_freq) -- 2.30.2