From e1338f267fa5670fc02a450774fa89b42e990883 Mon Sep 17 00:00:00 2001 From: Chad Versace Date: Mon, 6 Apr 2015 06:54:30 -0700 Subject: [PATCH] i965: Refactor brw_is_hiz_depth_format() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Every caller of this function uses it to determine if the current miptree needs a hiz buffer to be allocated. Strangely, the function doesn't take a miptree argument. So, this function effectively decides if and when a miptree's hiz buffer gets allocated without inspecting the miptree itself. Luckily, the driver behaves correctly despite the brw_is_hiz_depth_format's quirk. I will soon make some changes to the miptree that will require inspecting the miptree to determine if it needs a hiz buffer. So this patch renames brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer and gives it a miptree parameter. This patch shouldn't change any behavior. Reviewed-by: Kenneth Graunke Reviewed-by: Tapani Pälli Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 1 - .../drivers/dri/i965/brw_surface_formats.c | 19 -------------- src/mesa/drivers/dri/i965/intel_fbo.c | 4 +-- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 26 +++++++++++++++++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 +++- 5 files changed, 30 insertions(+), 25 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 6c168a33eba..0bd0ed1faf8 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1681,7 +1681,6 @@ void brw_upload_abo_surfaces(struct brw_context *brw, struct brw_stage_prog_data *prog_data); /* brw_surface_formats.c */ -bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format); bool brw_render_target_supported(struct brw_context *brw, struct gl_renderbuffer *rb); uint32_t brw_depth_format(struct brw_context *brw, mesa_format format); diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index 7524ad9675d..c7fb7073381 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -798,22 +798,3 @@ brw_depth_format(struct brw_context *brw, mesa_format format) unreachable("Unexpected depth format."); } } - -/** Can HiZ be enabled on a depthbuffer of the given format? */ -bool -brw_is_hiz_depth_format(struct brw_context *brw, mesa_format format) -{ - if (!brw->has_hiz) - return false; - - switch (format) { - case MESA_FORMAT_Z_FLOAT32: - case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: - case MESA_FORMAT_Z24_UNORM_X8_UINT: - case MESA_FORMAT_Z24_UNORM_S8_UINT: - case MESA_FORMAT_Z_UNORM16: - return true; - default: - return false; - } -} diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 2cf4771d539..7babd29aa09 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -561,7 +561,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw, intel_renderbuffer_set_draw_offset(irb); - if (mt->hiz_buf == NULL && brw_is_hiz_depth_format(brw, rb->Format)) { + if (intel_miptree_wants_hiz_buffer(brw, mt)) { intel_miptree_alloc_hiz(brw, mt); if (!mt->hiz_buf) return false; @@ -1032,7 +1032,7 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw, INTEL_MIPTREE_TILING_ANY, false); - if (brw_is_hiz_depth_format(brw, new_mt->format)) { + if (intel_miptree_wants_hiz_buffer(brw, new_mt)) { intel_miptree_alloc_hiz(brw, new_mt); } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index a90646038ba..492338b657e 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -403,7 +403,8 @@ intel_miptree_create_layout(struct brw_context *brw, if (!for_bo && _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL && (brw->must_use_separate_stencil || - (brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) { + (brw->has_separate_stencil && + intel_miptree_wants_hiz_buffer(brw, mt)))) { const bool force_all_slices_at_each_lod = brw->gen == 6; mt->stencil_mt = intel_miptree_create(brw, mt->target, @@ -843,7 +844,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw, if (!mt) goto fail; - if (brw_is_hiz_depth_format(brw, format)) { + if (intel_miptree_wants_hiz_buffer(brw, mt)) { ok = intel_miptree_alloc_hiz(brw, mt); if (!ok) goto fail; @@ -1681,6 +1682,27 @@ intel_hiz_miptree_buf_create(struct brw_context *brw, return buf; } +bool +intel_miptree_wants_hiz_buffer(struct brw_context *brw, + struct intel_mipmap_tree *mt) +{ + if (!brw->has_hiz) + return false; + + if (mt->hiz_buf != NULL) + return false; + + switch (mt->format) { + case MESA_FORMAT_Z_FLOAT32: + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + case MESA_FORMAT_Z24_UNORM_X8_UINT: + case MESA_FORMAT_Z24_UNORM_S8_UINT: + case MESA_FORMAT_Z_UNORM16: + return true; + default: + return false; + } +} bool intel_miptree_alloc_hiz(struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 3c41893212a..0cb64d2fef1 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -632,12 +632,15 @@ intel_miptree_copy_teximage(struct brw_context *brw, * functions on a miptree without HiZ. In that case, each function is a no-op. */ +bool +intel_miptree_wants_hiz_buffer(struct brw_context *brw, + struct intel_mipmap_tree *mt); + /** * \brief Allocate the miptree's embedded HiZ miptree. * \see intel_mipmap_tree:hiz_mt * \return false if allocation failed */ - bool intel_miptree_alloc_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt); -- 2.30.2