From e15ca74031516c916d3449497908e9f51cf1d515 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 17 Apr 2022 12:05:29 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 4a45b1db0..ffd9a30b9 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -941,7 +941,17 @@ required.* Some operations in the Power ISA already target two 64-bit scalar registers: `lq` for example. Some mathematical algorithms are more efficient when there are two outputs rather than one. 64-bit multiply -for example produces a 128 bit result +for example actually internally produces a 128 bit result, which clearly +cannot be stored in a single 64 bit register. Some ISAs recommend +"macro op fusion": the practice of setting a convention whereby if +two commonly used instructions (mullo, mulhi) use the same ALU but +one selects the low part of an identical operation and the other +selects the high part, then optimised micro-architectures may +"fuse" those two instructions together, using Micro-coding techniques, +internally. + +Macro-op fusion would be perfect for Scalar Multiply Lo/Hi if it +was not for SVP64 Horizontal-First Loops. * [[isa/svfixedarith]] * [[isa/svfparith]] -- 2.30.2