From e15f96e77fe3d54bd5e2fa00b92f2a63ab2e34be Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 15 Sep 2021 13:12:17 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index e2b202ea1..fddef9352 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -72,7 +72,7 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations: | / | / | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | | / | / | 00 | 1 | 1 CRM | parallel reduce mode (mapreduce), SUBVL=1 | | / | / | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | -|dz |SNZ| 01/10 | inv | CR-bit | Ffirst 3-bit mode | +|sz |SNZ| 01/10 | inv | CR-bit | Ffirst 3-bit mode | |sz |SNZ| 01/10 | inv | dz / | Ffirst 5-bit mode | |sz |SNZ| 11 | inv | CR-bit | 3-bit pred-result CR sel | |sz |SNZ| 11 | inv | dz / | 5-bit pred-result z/nonz | -- 2.30.2