From e17387a51f39673d1c86e6ee312ca3e1936d5fdd Mon Sep 17 00:00:00 2001 From: Dave Brolley Date: Thu, 19 Nov 1998 21:04:00 +0000 Subject: [PATCH] Thu Nov 19 16:02:46 1998 Dave Brolley * fr30-opc.c: Regenerated. * fr30-opc.h: Regenerated. * fr30-dis.c: Regenerated. * fr30-asm.c: Regenerated. --- opcodes/ChangeLog | 9 ++ opcodes/fr30-asm.c | 81 +++++++++++ opcodes/fr30-dis.c | 96 ++++++++++++ opcodes/fr30-opc.c | 355 ++++++++++++++++++++++++++++++++++++--------- opcodes/fr30-opc.h | 55 ++++--- 5 files changed, 511 insertions(+), 85 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6bef69ef338..3a1d9ca549f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +start-sanitize-fr30 +Thu Nov 19 16:02:46 1998 Dave Brolley + + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-asm.c: Regenerated. + +end-sanitize-fr30 Thu Nov 19 07:54:15 1998 Doug Evans * mips-opc.c (sync.p,sync.l): Swap insn values. diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c index 0a57766a1c5..78a477c3e10 100644 --- a/opcodes/fr30-asm.c +++ b/opcodes/fr30-asm.c @@ -53,6 +53,39 @@ static const char * insert_insn_normal CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); /* -- assembler routines inserted here */ +/* -- asm.c */ +/* Handle register lists for LDMx and STMx */ + +static const char * +parse_reglist_low (od, strp, opindex, valuep) + CGEN_OPCODE_DESC od; + const char **strp; + int opindex; + unsigned long *valuep; +{ + *valuep = 0; + while (**strp && **strp != ')') + { + ++*strp; + } + + if (!*strp) + return "Register list is not valid"; + + return NULL; +} + +static const char * +parse_reglist_hi (od, strp, opindex, valuep) + CGEN_OPCODE_DESC od; + const char **strp; + int opindex; + unsigned long *valuep; +{ + return parse_reglist_low (od, strp, opindex, valuep); +} + +/* -- */ /* Main entry point for operand parsing. @@ -85,6 +118,18 @@ fr30_cgen_parse_operand (od, opindex, strp, fields) case FR30_OPERAND_RJ : errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_gr, & fields->f_Rj); break; + case FR30_OPERAND_RIC : + errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_gr, & fields->f_Ric); + break; + case FR30_OPERAND_RJC : + errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_gr, & fields->f_Rjc); + break; + case FR30_OPERAND_CRI : + errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_cr, & fields->f_CRi); + break; + case FR30_OPERAND_CRJ : + errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_cr, & fields->f_CRj); + break; case FR30_OPERAND_RS1 : errmsg = cgen_parse_keyword (od, strp, & fr30_cgen_opval_h_dr, & fields->f_Rs1); break; @@ -106,6 +151,9 @@ fr30_cgen_parse_operand (od, opindex, strp, fields) case FR30_OPERAND_U4 : errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U4, &fields->f_u4); break; + case FR30_OPERAND_U4C : + errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U4C, &fields->f_u4c); + break; case FR30_OPERAND_M4 : errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_M4, &fields->f_m4); break; @@ -151,9 +199,18 @@ fr30_cgen_parse_operand (od, opindex, strp, fields) case FR30_OPERAND_LABEL12 : errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_LABEL12, &fields->f_rel12); break; + case FR30_OPERAND_REGLIST_LOW : + errmsg = parse_reglist_low (od, strp, FR30_OPERAND_REGLIST_LOW, &fields->f_reglist_low); + break; + case FR30_OPERAND_REGLIST_HI : + errmsg = parse_reglist_hi (od, strp, FR30_OPERAND_REGLIST_HI, &fields->f_reglist_hi); + break; case FR30_OPERAND_CC : errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_CC, &fields->f_cc); break; + case FR30_OPERAND_CCC : + errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_CCC, &fields->f_ccc); + break; default : /* xgettext:c-format */ @@ -197,6 +254,18 @@ fr30_cgen_insert_operand (od, opindex, fields, buffer, pc) case FR30_OPERAND_RJ : errmsg = insert_normal (od, fields->f_Rj, 0|(1<f_Ric, 0|(1<f_Rjc, 0|(1<f_CRi, 0|(1<f_CRj, 0|(1<f_Rs1, 0|(1<f_u4, 0|(1<f_u4c, 0|(1<f_m4; @@ -303,9 +375,18 @@ fr30_cgen_insert_operand (od, opindex, fields, buffer, pc) errmsg = insert_normal (od, value, 0|(1<f_reglist_low, 0|(1<f_reglist_hi, 0|(1<f_cc, 0|(1<f_ccc, 0|(1<fprintf_func) (info->stream, "r%i", index + offset); + + for (index = 1; index <= 7; ++index) + { + mask <<= 1; + if (value & mask) + (*info->fprintf_func) (info->stream, ",r%i", index + offset); + } +} + +static void +print_reglist_hi (od, dis_info, value, attrs, pc, length) + CGEN_OPCODE_DESC od; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + print_register_list (dis_info, value, 8); +} + +static void +print_reglist_low (od, dis_info, value, attrs, pc, length) + CGEN_OPCODE_DESC od; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + print_register_list (dis_info, value, 0); +} + +/* -- */ /* Main entry point for operand extraction. @@ -95,6 +143,18 @@ fr30_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc) case FR30_OPERAND_RJ : length = extract_normal (od, ex_info, insn_value, 0|(1<f_Rj); break; + case FR30_OPERAND_RIC : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_Ric); + break; + case FR30_OPERAND_RJC : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_Rjc); + break; + case FR30_OPERAND_CRI : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_CRi); + break; + case FR30_OPERAND_CRJ : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_CRj); + break; case FR30_OPERAND_RS1 : length = extract_normal (od, ex_info, insn_value, 0|(1<f_Rs1); break; @@ -116,6 +176,9 @@ fr30_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc) case FR30_OPERAND_U4 : length = extract_normal (od, ex_info, insn_value, 0|(1<f_u4); break; + case FR30_OPERAND_U4C : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_u4c); + break; case FR30_OPERAND_M4 : { long value; @@ -211,9 +274,18 @@ fr30_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc) fields->f_rel12 = value; } break; + case FR30_OPERAND_REGLIST_LOW : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_reglist_low); + break; + case FR30_OPERAND_REGLIST_HI : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_reglist_hi); + break; case FR30_OPERAND_CC : length = extract_normal (od, ex_info, insn_value, 0|(1<f_cc); break; + case FR30_OPERAND_CCC : + length = extract_normal (od, ex_info, insn_value, 0|(1<f_ccc); + break; default : /* xgettext:c-format */ @@ -257,6 +329,18 @@ fr30_cgen_print_operand (od, opindex, info, fields, attrs, pc, length) case FR30_OPERAND_RJ : print_keyword (od, info, & fr30_cgen_opval_h_gr, fields->f_Rj, 0|(1<f_Ric, 0|(1<f_Rjc, 0|(1<f_CRi, 0|(1<f_CRj, 0|(1<f_Rs1, 0|(1<f_u4, 0|(1<f_u4c, 0|(1<f_m4, 0|(1<f_rel12, 0|(1<f_reglist_low, 0|(1<f_reglist_hi, 0|(1<f_cc, 0|(1<f_ccc, 0|(1<f_Rj; break; + case FR30_OPERAND_RIC : + value = fields->f_Ric; + break; + case FR30_OPERAND_RJC : + value = fields->f_Rjc; + break; + case FR30_OPERAND_CRI : + value = fields->f_CRi; + break; + case FR30_OPERAND_CRJ : + value = fields->f_CRj; + break; case FR30_OPERAND_RS1 : value = fields->f_Rs1; break; @@ -2256,6 +2391,9 @@ fr30_cgen_get_int_operand (opindex, fields) case FR30_OPERAND_U4 : value = fields->f_u4; break; + case FR30_OPERAND_U4C : + value = fields->f_u4c; + break; case FR30_OPERAND_M4 : value = fields->f_m4; break; @@ -2301,9 +2439,18 @@ fr30_cgen_get_int_operand (opindex, fields) case FR30_OPERAND_LABEL12 : value = fields->f_rel12; break; + case FR30_OPERAND_REGLIST_LOW : + value = fields->f_reglist_low; + break; + case FR30_OPERAND_REGLIST_HI : + value = fields->f_reglist_hi; + break; case FR30_OPERAND_CC : value = fields->f_cc; break; + case FR30_OPERAND_CCC : + value = fields->f_ccc; + break; default : /* xgettext:c-format */ @@ -2330,6 +2477,18 @@ fr30_cgen_get_vma_operand (opindex, fields) case FR30_OPERAND_RJ : value = fields->f_Rj; break; + case FR30_OPERAND_RIC : + value = fields->f_Ric; + break; + case FR30_OPERAND_RJC : + value = fields->f_Rjc; + break; + case FR30_OPERAND_CRI : + value = fields->f_CRi; + break; + case FR30_OPERAND_CRJ : + value = fields->f_CRj; + break; case FR30_OPERAND_RS1 : value = fields->f_Rs1; break; @@ -2351,6 +2510,9 @@ fr30_cgen_get_vma_operand (opindex, fields) case FR30_OPERAND_U4 : value = fields->f_u4; break; + case FR30_OPERAND_U4C : + value = fields->f_u4c; + break; case FR30_OPERAND_M4 : value = fields->f_m4; break; @@ -2396,9 +2558,18 @@ fr30_cgen_get_vma_operand (opindex, fields) case FR30_OPERAND_LABEL12 : value = fields->f_rel12; break; + case FR30_OPERAND_REGLIST_LOW : + value = fields->f_reglist_low; + break; + case FR30_OPERAND_REGLIST_HI : + value = fields->f_reglist_hi; + break; case FR30_OPERAND_CC : value = fields->f_cc; break; + case FR30_OPERAND_CCC : + value = fields->f_ccc; + break; default : /* xgettext:c-format */ @@ -2429,6 +2600,18 @@ fr30_cgen_set_int_operand (opindex, fields, value) case FR30_OPERAND_RJ : fields->f_Rj = value; break; + case FR30_OPERAND_RIC : + fields->f_Ric = value; + break; + case FR30_OPERAND_RJC : + fields->f_Rjc = value; + break; + case FR30_OPERAND_CRI : + fields->f_CRi = value; + break; + case FR30_OPERAND_CRJ : + fields->f_CRj = value; + break; case FR30_OPERAND_RS1 : fields->f_Rs1 = value; break; @@ -2450,6 +2633,9 @@ fr30_cgen_set_int_operand (opindex, fields, value) case FR30_OPERAND_U4 : fields->f_u4 = value; break; + case FR30_OPERAND_U4C : + fields->f_u4c = value; + break; case FR30_OPERAND_M4 : fields->f_m4 = value; break; @@ -2495,9 +2681,18 @@ fr30_cgen_set_int_operand (opindex, fields, value) case FR30_OPERAND_LABEL12 : fields->f_rel12 = value; break; + case FR30_OPERAND_REGLIST_LOW : + fields->f_reglist_low = value; + break; + case FR30_OPERAND_REGLIST_HI : + fields->f_reglist_hi = value; + break; case FR30_OPERAND_CC : fields->f_cc = value; break; + case FR30_OPERAND_CCC : + fields->f_ccc = value; + break; default : /* xgettext:c-format */ @@ -2521,6 +2716,18 @@ fr30_cgen_set_vma_operand (opindex, fields, value) case FR30_OPERAND_RJ : fields->f_Rj = value; break; + case FR30_OPERAND_RIC : + fields->f_Ric = value; + break; + case FR30_OPERAND_RJC : + fields->f_Rjc = value; + break; + case FR30_OPERAND_CRI : + fields->f_CRi = value; + break; + case FR30_OPERAND_CRJ : + fields->f_CRj = value; + break; case FR30_OPERAND_RS1 : fields->f_Rs1 = value; break; @@ -2542,6 +2749,9 @@ fr30_cgen_set_vma_operand (opindex, fields, value) case FR30_OPERAND_U4 : fields->f_u4 = value; break; + case FR30_OPERAND_U4C : + fields->f_u4c = value; + break; case FR30_OPERAND_M4 : fields->f_m4 = value; break; @@ -2587,9 +2797,18 @@ fr30_cgen_set_vma_operand (opindex, fields, value) case FR30_OPERAND_LABEL12 : fields->f_rel12 = value; break; + case FR30_OPERAND_REGLIST_LOW : + fields->f_reglist_low = value; + break; + case FR30_OPERAND_REGLIST_HI : + fields->f_reglist_hi = value; + break; case FR30_OPERAND_CC : fields->f_cc = value; break; + case FR30_OPERAND_CCC : + fields->f_ccc = value; + break; default : /* xgettext:c-format */ diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h index 61b5f2dc511..0eb8b1aee8b 100644 --- a/opcodes/fr30-opc.h +++ b/opcodes/fr30-opc.h @@ -107,6 +107,14 @@ typedef enum h_gr { , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 } H_GR; +/* Enum declaration for coprocessor registers. */ +typedef enum h_cr { + H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3 + , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7 + , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11 + , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15 +} H_CR; + /* Enum declaration for dedicated registers. */ typedef enum h_dr { H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP @@ -135,13 +143,15 @@ typedef enum h_r15 { /* Enum declaration for fr30 operand types. */ typedef enum cgen_operand_type { - FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RS1 + FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC + , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1 , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15 - , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_M4, FR30_OPERAND_U8 - , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9 - , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32 - , FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9 - , FR30_OPERAND_LABEL12, FR30_OPERAND_CC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT + , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_M4 + , FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8 + , FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10 + , FR30_OPERAND_I32, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10 + , FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW, FR30_OPERAND_REGLIST_HI + , FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT , FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT , FR30_OPERAND_MAX } CGEN_OPERAND_TYPE; @@ -215,7 +225,7 @@ typedef enum cgen_insn_type { , FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR , FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS , FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_JMPD - , FR30_INSN_CALL, FR30_INSN_CALLD, FR30_INSN_CALLR, FR30_INSN_CALLRD + , FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL, FR30_INSN_CALLD , FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT, FR30_INSN_INTE , FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ , FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN @@ -225,13 +235,15 @@ typedef enum cgen_insn_type { , FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD, FR30_INSN_BND , FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD, FR30_INSN_BLTD , FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD, FR30_INSN_BLSD - , FR30_INSN_BHID, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B - , FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI - , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH - , FR30_INSN_DMOVR13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_DMOVR15PI, FR30_INSN_LDRES - , FR30_INSN_STRES, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR + , FR30_INSN_BHID, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B + , FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB, FR30_INSN_DMOVR15PI + , FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B, FR30_INSN_DMOV2R13PI + , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_LDRES + , FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD, FR30_INSN_COPST + , FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR , FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB - , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE + , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0, FR30_INSN_LDM1 + , FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER, FR30_INSN_LEAVE , FR30_INSN_XCHB, FR30_INSN_MAX } CGEN_INSN_TYPE; @@ -253,11 +265,17 @@ struct cgen_fields long f_op4; long f_op5; long f_cc; + long f_ccc; long f_Rj; long f_Ri; long f_Rs1; long f_Rs2; + long f_Rjc; + long f_Ric; + long f_CRj; + long f_CRi; long f_u4; + long f_u4c; long f_i4; long f_m4; long f_u8; @@ -274,6 +292,8 @@ struct cgen_fields long f_dir9; long f_dir10; long f_rel12; + long f_reglist_hi; + long f_reglist_low; int length; }; @@ -285,10 +305,10 @@ extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[]; /* Enum declaration for fr30 hardware types. */ typedef enum hw_type { HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT - , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_DR - , HW_H_PS, HW_H_R13, HW_H_R14, HW_H_R15 - , HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT, HW_H_CBIT - , HW_H_IBIT, HW_H_SBIT, HW_MAX + , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR + , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14 + , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT + , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_MAX } HW_TYPE; #define MAX_HW ((int) HW_MAX) @@ -296,6 +316,7 @@ typedef enum hw_type { /* Hardware decls. */ extern CGEN_KEYWORD fr30_cgen_opval_h_gr; +extern CGEN_KEYWORD fr30_cgen_opval_h_cr; extern CGEN_KEYWORD fr30_cgen_opval_h_dr; extern CGEN_KEYWORD fr30_cgen_opval_h_ps; extern CGEN_KEYWORD fr30_cgen_opval_h_r13; -- 2.30.2