From e1ec501d1e5b8199b29c88446075065431faf8af Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 18:29:20 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 677651f86..de6a2eaa0 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -596,7 +596,7 @@ What the designers did however was not to add new Load-Store or Arithmetic instructions to RISC-V, but instead to "mark" registers with a tag. These tags tell the CPU: when you are asked to carry out -an add instruction on r6 and r7, do not take r6 or r7 from the reguster +an add instruction on r6 and r7, do not take r6 or r7 from the register file, instead please perform a Cache-coherent Load-with-Increment on each, using special Address Registers for each. Each new use of r6 therefore brings in an entirely new value *directly from -- 2.30.2