From e1fab8ba2337fd3bdd9c7112fae22d7ab001c2eb Mon Sep 17 00:00:00 2001 From: Oleg Endo Date: Thu, 28 Apr 2016 01:18:13 +0000 Subject: [PATCH] sh-common.c: Remove SH5 support. gcc/ * common/config/sh/sh-common.c: Remove SH5 support. * config/sh/constraints.md: Likewise. * config/sh/config/sh/elf.h: Likewise. * config/sh/linux.h: Likewise. * config/sh/netbsd-elf.h: Likewise. * config/sh/predicates.md: Likewise. * config/sh/sh-c.c: Likewise. * config/sh/sh-protos.h: Likewise. * config/sh/sh.c: Likewise. * config/sh/sh.h: Likewise. * config/sh/sh.md: Likewise. * config/sh/sh.opt: Likewise. * config/sh/sync.md: Likewise. * config/sh/sh64.h: Delete. * config/sh/shmedia.h: Likewise. * config/sh/shmedia.md: Likewise. * config/sh/sshmedia.h: Likewise. * config/sh/t-netbsd-sh5-64: Likewise. * config/sh/t-sh64: Likewise. * config/sh/ushmedia.h: Likewise. From-SVN: r235544 --- gcc/ChangeLog | 23 + gcc/common/config/sh/sh-common.c | 30 - gcc/config/sh/constraints.md | 37 +- gcc/config/sh/elf.h | 5 +- gcc/config/sh/linux.h | 29 +- gcc/config/sh/netbsd-elf.h | 8 - gcc/config/sh/predicates.md | 492 +-- gcc/config/sh/sh-c.c | 9 - gcc/config/sh/sh-protos.h | 4 - gcc/config/sh/sh.c | 2203 +--------- gcc/config/sh/sh.h | 518 +-- gcc/config/sh/sh.md | 6812 +----------------------------- gcc/config/sh/sh.opt | 45 +- gcc/config/sh/sh64.h | 22 - gcc/config/sh/shmedia.h | 30 - gcc/config/sh/shmedia.md | 94 - gcc/config/sh/sshmedia.h | 78 - gcc/config/sh/sync.md | 4 +- gcc/config/sh/t-netbsd-sh5-64 | 1 - gcc/config/sh/t-sh64 | 22 - gcc/config/sh/ushmedia.h | 1091 ----- 21 files changed, 424 insertions(+), 11133 deletions(-) delete mode 100644 gcc/config/sh/sh64.h delete mode 100644 gcc/config/sh/shmedia.h delete mode 100644 gcc/config/sh/shmedia.md delete mode 100644 gcc/config/sh/sshmedia.h delete mode 100644 gcc/config/sh/t-netbsd-sh5-64 delete mode 100644 gcc/config/sh/t-sh64 delete mode 100644 gcc/config/sh/ushmedia.h diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5905a41571c..4f30dd3587f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2016-04-28 Oleg Endo + + * common/config/sh/sh-common.c: Remove SH5 support. + * config/sh/constraints.md: Likewise. + * config/sh/config/sh/elf.h: Likewise. + * config/sh/linux.h: Likewise. + * config/sh/netbsd-elf.h: Likewise. + * config/sh/predicates.md: Likewise. + * config/sh/sh-c.c: Likewise. + * config/sh/sh-protos.h: Likewise. + * config/sh/sh.c: Likewise. + * config/sh/sh.h: Likewise. + * config/sh/sh.md: Likewise. + * config/sh/sh.opt: Likewise. + * config/sh/sync.md: Likewise. + * config/sh/sh64.h: Delete. + * config/sh/shmedia.h: Likewise. + * config/sh/shmedia.md: Likewise. + * config/sh/sshmedia.h: Likewise. + * config/sh/t-netbsd-sh5-64: Likewise. + * config/sh/t-sh64: Likewise. + * config/sh/ushmedia.h: Likewise. + 2016-04-28 Uros Bizjak * config/i386/i386.md (sign_extend to memory peephole2s): Use diff --git a/gcc/common/config/sh/sh-common.c b/gcc/common/config/sh/sh-common.c index b145779c977..ee6e4c9d89b 100644 --- a/gcc/common/config/sh/sh-common.c +++ b/gcc/common/config/sh/sh-common.c @@ -148,36 +148,6 @@ sh_handle_option (struct gcc_options *opts, = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH4A_SINGLE_ONLY; return true; - case OPT_m5_32media: - opts->x_target_flags - = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA; - return true; - - case OPT_m5_32media_nofpu: - opts->x_target_flags - = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_32MEDIA_NOFPU; - return true; - - case OPT_m5_64media: - opts->x_target_flags - = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA; - return true; - - case OPT_m5_64media_nofpu: - opts->x_target_flags - = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_64MEDIA_NOFPU; - return true; - - case OPT_m5_compact: - opts->x_target_flags - = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT; - return true; - - case OPT_m5_compact_nofpu: - opts->x_target_flags - = (opts->x_target_flags & ~MASK_ARCH) | SELECT_SH5_COMPACT_NOFPU; - return true; - default: return true; } diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md index b87ec2264bb..644a0f0c697 100644 --- a/gcc/config/sh/constraints.md +++ b/gcc/config/sh/constraints.md @@ -26,15 +26,12 @@ ;; fldi0 / fldi0 cases ;; Cxx: Constants other than only CONST_INT ;; Ccl: call site label -;; Css: signed 16-bit constant, literal or symbolic -;; Csu: unsigned 16-bit constant, literal or symbolic ;; Csy: label or symbol ;; Cpg: non-explicit constants that can be directly loaded into a general ;; purpose register in PIC code. Like 's' except we don't allow ;; PIC_ADDR_P ;; IJKLMNOP: CONT_INT constants ;; Ixx: signed xx bit -;; J16: 0xffffffff00000000 | 0x00000000ffffffff ;; Jmb: 0x000000FF ;; Jmw: 0x0000FFFF ;; Jhb: 0x80000000 @@ -105,23 +102,13 @@ "R0 register.") ;; Integer constraints -(define_constraint "I06" - "A signed 6-bit constant, as used in SHmedia beqi, bnei and xori." - (and (match_code "const_int") - (match_test "ival >= -32 && ival <= 31"))) - (define_constraint "I08" "A signed 8-bit constant, as used in add, sub, etc." (and (match_code "const_int") (match_test "ival >= -128 && ival <= 127"))) -(define_constraint "I10" - "A signed 10-bit constant, as used in SHmedia andi, ori." - (and (match_code "const_int") - (match_test "ival >= -512 && ival <= 511"))) - (define_constraint "I16" - "A signed 16-bit constant, as used in SHmedia movi." + "A signed 16-bit constant." (and (match_code "const_int") (match_test "ival >= -32768 && ival <= 32767"))) @@ -138,11 +125,6 @@ (match_test "(ival & 255) == 0") (match_test "TARGET_SH2A"))) -(define_constraint "J16" - "0xffffffff00000000 or 0x00000000ffffffff." - (and (match_code "const_int") - (match_test "CONST_OK_FOR_J16 (ival)"))) - (define_constraint "Jmb" "Low byte mask constant 0x000000FF" (and (match_code "const_int") @@ -190,11 +172,6 @@ (and (match_code "const_int") (match_test "ival >= 0 && ival <= 8191"))) -(define_constraint "K16" - "An unsigned 16-bit constant, as used in SHmedia shori." - (and (match_code "const_int") - (match_test "ival >= 0 && ival <= 65535"))) - (define_constraint "P27" "A constant for shift operand 1,2,8 or 16." (and (match_code "const_int") @@ -239,18 +216,6 @@ (and (match_code "unspec") (match_test "XINT (op, 1) == UNSPEC_CALLER"))) -(define_constraint "Css" - "A signed 16-bit constant, literal or symbolic." - (and (match_code "const") - (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") - (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_EXTRACT_S16"))) - -(define_constraint "Csu" - "An unsigned 16-bit constant, literal or symbolic." - (and (match_code "const") - (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") - (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_EXTRACT_U16"))) - (define_constraint "Csy" "A label or a symbol." (ior (match_test "NON_PIC_REFERENCE_P (op)") diff --git a/gcc/config/sh/elf.h b/gcc/config/sh/elf.h index f0f2f41529e..ad2713fcf55 100644 --- a/gcc/config/sh/elf.h +++ b/gcc/config/sh/elf.h @@ -32,7 +32,6 @@ along with GCC; see the file COPYING3. If not see #define DWARF2_ASM_LINE_DEBUG_INFO 1 #undef WCHAR_TYPE -/* #define WCHAR_TYPE (TARGET_SH5 ? "int" : "long int") */ #define WCHAR_TYPE SH_ELF_WCHAR_TYPE #undef WCHAR_TYPE_SIZE @@ -44,10 +43,10 @@ along with GCC; see the file COPYING3. If not see #define LOCAL_LABEL_PREFIX "." #undef SIZE_TYPE -#define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int") +#define SIZE_TYPE ("unsigned int") #undef PTRDIFF_TYPE -#define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int") +#define PTRDIFF_TYPE ("int") /* Pass -ml and -mrelax to the assembler and linker. */ #undef ASM_SPEC diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h index 2a036ac3f4b..09e966b9e49 100644 --- a/gcc/config/sh/linux.h +++ b/gcc/config/sh/linux.h @@ -81,32 +81,6 @@ along with GCC; see the file COPYING3. If not see #undef FUNCTION_PROFILER #define FUNCTION_PROFILER(STREAM,LABELNO) \ do { \ - if (TARGET_SHMEDIA) \ - { \ - fprintf (STREAM, "\tpt\t1f,tr1\n"); \ - fprintf (STREAM, "\taddi.l\tr15,-8,r15\n"); \ - fprintf (STREAM, "\tst.l\tr15,0,r18\n"); \ - if (flag_pic) \ - { \ - const char *gofs = "(datalabel _GLOBAL_OFFSET_TABLE_-(0f-.))"; \ - fprintf (STREAM, "\tmovi\t((%s>>16)&0xffff),r21\n", gofs); \ - fprintf (STREAM, "\tshori\t(%s & 0xffff),r21\n", gofs); \ - fprintf (STREAM, "0:\tptrel/u\tr21,tr0\n"); \ - fprintf (STREAM, "\tmovi\t((mcount@GOTPLT)&0xffff),r22\n"); \ - fprintf (STREAM, "\tgettr\ttr0,r21\n"); \ - fprintf (STREAM, "\tadd.l\tr21,r22,r21\n"); \ - fprintf (STREAM, "\tld.l\tr21,0,r21\n"); \ - fprintf (STREAM, "\tptabs\tr21,tr0\n"); \ - } \ - else \ - fprintf (STREAM, "\tpt\tmcount,tr0\n"); \ - fprintf (STREAM, "\tgettr\ttr1,r18\n"); \ - fprintf (STREAM, "\tblink\ttr0,r63\n"); \ - fprintf (STREAM, "1:\tld.l\tr15,0,r18\n"); \ - fprintf (STREAM, "\taddi.l\tr15,8,r15\n"); \ - } \ - else \ - { \ if (flag_pic) \ { \ fprintf (STREAM, "\tmov.l\t3f,r1\n"); \ @@ -130,7 +104,6 @@ along with GCC; see the file COPYING3. If not see else \ fprintf (STREAM, "1:\t.long\tmcount\n"); \ fprintf (STREAM, "2:\tlds.l\t@r15+,pr\n"); \ - } \ } while (0) /* For SH3 and SH4, we use a slot of the unwind frame which correspond @@ -142,7 +115,7 @@ along with GCC; see the file COPYING3. If not see so as to return itself for 16. */ #undef DBX_REGISTER_NUMBER #define DBX_REGISTER_NUMBER(REGNO) \ - ((! TARGET_SH5 && (REGNO) == 16) ? 16 : SH_DBX_REGISTER_NUMBER (REGNO)) + (((REGNO) == 16) ? 16 : SH_DBX_REGISTER_NUMBER (REGNO)) /* Since libgcc is compiled with -fpic for this target, we can't use __sdivsi3_1 as the division strategy for -O0 and -Os. */ diff --git a/gcc/config/sh/netbsd-elf.h b/gcc/config/sh/netbsd-elf.h index 61db1ed9a97..e6580186110 100644 --- a/gcc/config/sh/netbsd-elf.h +++ b/gcc/config/sh/netbsd-elf.h @@ -67,13 +67,6 @@ along with GCC; see the file COPYING3. If not see #define FUNCTION_PROFILER(STREAM,LABELNO) \ do \ { \ - if (TARGET_SHMEDIA32 || TARGET_SHMEDIA64) \ - { \ - /* FIXME */ \ - sorry ("unimplemented-shmedia profiling"); \ - } \ - else \ - { \ fprintf((STREAM), "\tmov.l\t%sLP%d,r1\n", \ LOCAL_LABEL_PREFIX, (LABELNO)); \ fprintf((STREAM), "\tmova\t%sLP%dr,r0\n", \ @@ -84,7 +77,6 @@ do \ fprintf((STREAM), "%sLP%d:\t.long\t__mcount\n", \ LOCAL_LABEL_PREFIX, (LABELNO)); \ fprintf((STREAM), "%sLP%dr:\n", LOCAL_LABEL_PREFIX, (LABELNO)); \ - } \ } \ while (0) diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md index e3eb59b90d7..e0502138e31 100644 --- a/gcc/config/sh/predicates.md +++ b/gcc/config/sh/predicates.md @@ -17,70 +17,6 @@ ;; along with GCC; see the file COPYING3. If not see ;; . -;; TODO: Add a comment here. -(define_predicate "trapping_target_operand" - (match_code "if_then_else") -{ - rtx cond, mem, res, tar, and_expr; - - if (GET_MODE (op) != PDImode) - return 0; - cond = XEXP (op, 0); - mem = XEXP (op, 1); - res = XEXP (op, 2); - if (!MEM_P (mem) - || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE)) - return 0; - tar = XEXP (res, 0); - if (!rtx_equal_p (XEXP (mem, 0), tar) - || GET_MODE (tar) != Pmode) - return 0; - if (GET_CODE (cond) == CONST) - { - cond = XEXP (cond, 0); - if (!satisfies_constraint_Csy (tar)) - return 0; - if (GET_CODE (tar) == CONST) - tar = XEXP (tar, 0); - } - else if (!arith_reg_operand (tar, VOIDmode) - && ! satisfies_constraint_Csy (tar)) - return 0; - if (GET_CODE (cond) != EQ) - return 0; - and_expr = XEXP (cond, 0); - return (GET_CODE (and_expr) == AND - && rtx_equal_p (XEXP (and_expr, 0), tar) - && CONST_INT_P (XEXP (and_expr, 1)) - && CONST_INT_P (XEXP (cond, 1)) - && INTVAL (XEXP (and_expr, 1)) == 3 - && INTVAL (XEXP (cond, 1)) == 3); -}) - -;; A logical operand that can be used in an shmedia and insn. -(define_predicate "and_operand" - (match_code "subreg,reg,const_int") -{ - if (logical_operand (op, mode)) - return 1; - - /* Check mshflo.l / mshflhi.l opportunities. */ - if (TARGET_SHMEDIA - && mode == DImode - && satisfies_constraint_J16 (op)) - return 1; - - return 0; -}) - -;; Like arith_reg_dest, but this predicate is defined with -;; define_special_predicate, not define_predicate. -(define_special_predicate "any_arith_reg_dest" - (match_code "subreg,reg") -{ - return arith_reg_dest (op, mode); -}) - ;; Like register_operand, but this predicate is defined with ;; define_special_predicate, not define_predicate. (define_special_predicate "any_register_operand" @@ -93,35 +29,7 @@ (define_predicate "arith_operand" (match_code "subreg,reg,const_int,truncate") { - if (arith_reg_operand (op, mode)) - return 1; - - if (TARGET_SHMEDIA) - { - /* FIXME: We should be checking whether the CONST_INT fits in a - signed 16-bit here, but this causes reload_cse to crash when - attempting to transform a sequence of two 64-bit sets of the - same register from literal constants into a set and an add, - when the difference is too wide for an add. */ - if (CONST_INT_P (op) - || satisfies_constraint_Css (op)) - return 1; - else if (GET_CODE (op) == TRUNCATE - && REG_P (XEXP (op, 0)) - && ! system_reg_operand (XEXP (op, 0), VOIDmode) - && (mode == VOIDmode || mode == GET_MODE (op)) - && (GET_MODE_SIZE (GET_MODE (op)) - < GET_MODE_SIZE (GET_MODE (XEXP (op, 0)))) - && (! FP_REGISTER_P (REGNO (XEXP (op, 0))) - || GET_MODE_SIZE (GET_MODE (op)) == 4)) - return register_operand (XEXP (op, 0), VOIDmode); - else - return 0; - } - else if (satisfies_constraint_I08 (op)) - return 1; - - return 0; + return arith_reg_operand (op, mode) || satisfies_constraint_I08 (op); }) ;; Like above, but for DImode destinations: forbid paradoxical DImode @@ -130,10 +38,6 @@ (define_predicate "arith_reg_dest" (match_code "subreg,reg") { - if (mode == DImode && GET_CODE (op) == SUBREG - && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8 - && TARGET_SHMEDIA) - return 0; return arith_reg_operand (op, mode); }) @@ -160,11 +64,7 @@ /* Allow a no-op sign extension - compare LOAD_EXTEND_OP. We allow SImode here, as not using an FP register is just a matter of proper register allocation. */ - if (TARGET_SHMEDIA - && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND - && GET_MODE (XEXP (op, 0)) == SImode - && GET_CODE (XEXP (op, 0)) != SUBREG) - return register_operand (XEXP (op, 0), VOIDmode); + #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars. */ if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND && GET_MODE (XEXP (op, 0)) == HImode @@ -236,47 +136,6 @@ (ior (match_test "INTVAL (op) == 255") (match_test "INTVAL (op) == 65535")))) -;; Returns 1 if OP is a floating point operator with two operands. -(define_predicate "binary_float_operator" - (and (match_code "plus,minus,mult,div") - (match_test "GET_MODE (op) == mode"))) - -;; Returns 1 if OP is a logical operator with two operands. -(define_predicate "binary_logical_operator" - (and (match_code "and,ior,xor") - (match_test "GET_MODE (op) == mode"))) - -;; Return 1 if OP is an address suitable for a cache manipulation operation. -;; MODE has the meaning as in address_operand. -(define_special_predicate "cache_address_operand" - (match_code "plus,reg") -{ - if (GET_CODE (op) == PLUS) - { - if (!REG_P (XEXP (op, 0))) - return 0; - if (!CONST_INT_P (XEXP (op, 1)) - || (INTVAL (XEXP (op, 1)) & 31)) - return 0; - } - else if (!REG_P (op)) - return 0; - return address_operand (op, mode); -}) - -;; Returns 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu. -(define_predicate "cmp_operand" - (match_code "subreg,reg,const_int") -{ - if (satisfies_constraint_N (op)) - return 1; - if (TARGET_SHMEDIA - && mode != DImode && GET_CODE (op) == SUBREG - && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) - return 0; - return arith_reg_operand (op, mode); -}) - ;; Returns true if OP is an operand that can be used as the first operand in ;; the cstoresi4 expander pattern. (define_predicate "cmpsi_operand" @@ -289,53 +148,6 @@ return arith_operand (op, mode); }) -;; Returns true if OP is a comutative float operator. -;; This predicate is currently unused. -;;(define_predicate "commutative_float_operator" -;; (and (match_code "plus,mult") -;; (match_test "GET_MODE (op) == mode"))) - -;; Returns true if OP is a equal or not equal operator. -(define_predicate "equality_comparison_operator" - (match_code "eq,ne")) - -;; Returns true if OP is an arithmetic operand that is zero extended during -;; an operation. -(define_predicate "extend_reg_operand" - (match_code "subreg,reg,truncate") -{ - return (GET_CODE (op) == TRUNCATE - ? arith_operand - : arith_reg_operand) (op, mode); -}) - -;; Like extend_reg_operand, but also allow a constant 0. -(define_predicate "extend_reg_or_0_operand" - (match_code "subreg,reg,truncate,const_int") -{ - return (GET_CODE (op) == TRUNCATE - ? arith_operand - : arith_reg_or_0_operand) (op, mode); -}) - -;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND. -(define_predicate "ext_dest_operand" - (match_code "subreg,reg") -{ - return arith_reg_operand (op, mode); -}) - -;; Returns true if OP can be used as a destination register for shmedia floating -;; point to integer conversions. -(define_predicate "fp_arith_reg_dest" - (match_code "subreg,reg") -{ - if (mode == DImode && GET_CODE (op) == SUBREG - && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8) - return 0; - return fp_arith_reg_operand (op, mode); -}) - ;; Returns true if OP is a floating point register that can be used in floating ;; point arithmetic operations. (define_predicate "fp_arith_reg_operand" @@ -390,12 +202,9 @@ (define_predicate "fpul_operand" (match_code "reg") { - if (TARGET_SHMEDIA) - return fp_arith_reg_operand (op, mode); - - return (REG_P (op) - && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER) - && GET_MODE (op) == mode); + return REG_P (op) + && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER) + && GET_MODE (op) == mode; }) ;; Returns true if OP is a valid fpul input operand for the fsca insn. @@ -467,10 +276,7 @@ ;; Returns 1 if the operand can be used in a zero_extend. (define_predicate "zero_extend_operand" - (ior (and (match_test "TARGET_SHMEDIA") - (match_operand 0 "general_extend_operand")) - (and (match_test "! TARGET_SHMEDIA") - (match_operand 0 "arith_reg_operand")))) + (match_operand 0 "arith_reg_operand")) ;; Returns 1 if OP can be source of a simple move operation. Same as ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as @@ -523,10 +329,6 @@ rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op); rtx x = XEXP (mem_rtx, 0); - if (! ALLOW_INDEXED_ADDRESS - && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) - return false; - if (GET_CODE (x) == PLUS) { rtx y = XEXP (x, 0); @@ -571,15 +373,6 @@ return true; } - if (TARGET_SHMEDIA - && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR) - && sh_rep_vec (op, mode)) - return 1; - if (TARGET_SHMEDIA && 1 - && GET_CODE (op) == SUBREG && GET_MODE (op) == mode - && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op)) - /* FIXME */ abort (); /* return 1; */ - return general_operand (op, mode); }) @@ -615,10 +408,6 @@ /* Only pre dec allowed. */ if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC) return 0; - if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG - && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8 - && ! (reload_in_progress || reload_completed)) - return 0; if (mode == GET_MODE (op) && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))) @@ -626,10 +415,6 @@ rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op); rtx x = XEXP (mem_rtx, 0); - if (! ALLOW_INDEXED_ADDRESS - && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) - return false; - if (GET_CODE (x) == PLUS) { rtx y = XEXP (x, 0); @@ -677,22 +462,6 @@ return general_operand (op, mode); }) -;; Returns 1 if OP is a POST_INC on stack pointer register. -(define_predicate "sh_no_delay_pop_operand" - (match_code "mem") -{ - rtx inside; - inside = XEXP (op, 0); - - if (GET_CODE (op) == MEM && GET_MODE (op) == SImode - && GET_CODE (inside) == POST_INC - && GET_CODE (XEXP (inside, 0)) == REG - && REGNO (XEXP (inside, 0)) == SP_REG) - return 1; - - return 0; -}) - ;; Returns 1 if OP is a MEM that can be source of a simple move operation. (define_predicate "unaligned_load_operand" (match_code "mem") @@ -741,65 +510,11 @@ && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true); }) -;; Returns true if OP is some kind of greater comparision. -(define_predicate "greater_comparison_operator" - (match_code "gt,ge,gtu,geu")) - -;; Returns true if OP is an operand suitable for shmedia reload_inqi and -;; reload_inhi insns. -(define_predicate "inqhi_operand" - (match_code "truncate") -{ - if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op)) - return 0; - op = XEXP (op, 0); - /* Can't use true_regnum here because copy_cost wants to know about - SECONDARY_INPUT_RELOAD_CLASS. */ - return REG_P (op) && FP_REGISTER_P (REGNO (op)); -}) - -;; Returns true if OP is a general purpose integer register. -;; This predicate is currently unused. -;;(define_special_predicate "int_gpr_dest" -;; (match_code "subreg,reg") -;;{ -;; machine_mode op_mode = GET_MODE (op); -;; -;; if (GET_MODE_CLASS (op_mode) != MODE_INT -;; || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD) -;; return 0; -;; if (! reload_completed) -;; return 0; -;; return true_regnum (op) <= LAST_GENERAL_REG; -;;}) - -;; Returns true if OP is some kind of less comparison. -(define_predicate "less_comparison_operator" - (match_code "lt,le,ltu,leu")) - ;; Returns 1 if OP is a valid source operand for a logical operation. (define_predicate "logical_operand" (match_code "subreg,reg,const_int") { - if (TARGET_SHMEDIA - && mode != DImode && GET_CODE (op) == SUBREG - && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) - return 0; - - if (arith_reg_operand (op, mode)) - return 1; - - if (TARGET_SHMEDIA) - { - if (satisfies_constraint_I10 (op)) - return 1; - else - return 0; - } - else if (satisfies_constraint_K08 (op)) - return 1; - - return 0; + return arith_reg_operand (op, mode) || satisfies_constraint_K08 (op); }) ;; Returns true if OP is a valid constant source operand for a logical @@ -813,70 +528,20 @@ (define_predicate "logical_and_operand" (match_code "subreg,reg,const_int") { - if (logical_operand (op, mode)) - return 1; - - if (! TARGET_SHMEDIA - && (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op))) - return 1; - - return 0; + return logical_operand (op, mode) || satisfies_constraint_Jmb (op) + || satisfies_constraint_Jmw (op); }) ;; Returns true if OP is a logical operator. (define_predicate "logical_operator" (match_code "and,ior,xor")) -;; Like arith_reg_operand, but for register source operands of narrow -;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs. (define_predicate "logical_reg_operand" (match_code "subreg,reg") { - if (TARGET_SHMEDIA - && GET_CODE (op) == SUBREG - && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4 - && mode != DImode) - return 0; return arith_reg_operand (op, mode); }) -;; Returns true if OP is a valid bit offset value for the shmedia mextr insns. -(define_predicate "mextr_bit_offset" - (match_code "const_int") -{ - HOST_WIDE_INT i; - - if (!CONST_INT_P (op)) - return 0; - i = INTVAL (op); - return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0; -}) - -;; Returns true if OP is a constant -1, 0 or an zero extended register that -;; can be used as an operator in the *subsi3_media insn. -(define_predicate "minuend_operand" - (match_code "subreg,reg,truncate,const_int") -{ - return op == constm1_rtx || extend_reg_or_0_operand (op, mode); -}) - -;; Returns true if OP is a noncommutative floating point operator. -;; This predicate is currently unused. -;;(define_predicate "noncommutative_float_operator" -;; (and (match_code "minus,div") -;; (match_test "GET_MODE (op) == mode"))) - -;; UNORDERED is only supported on SHMEDIA. - -(define_predicate "sh_float_comparison_operator" - (ior (match_operand 0 "ordered_comparison_operator") - (and (match_test "TARGET_SHMEDIA") - (match_code "unordered")))) - -(define_predicate "shmedia_cbranch_comparison_operator" - (ior (match_operand 0 "equality_comparison_operator") - (match_operand 0 "greater_comparison_operator"))) - ;; Returns true if OP is a constant vector. (define_predicate "sh_const_vec" (match_code "const_vector") @@ -927,16 +592,6 @@ return 1; }) -;; Like register_operand, but take into account that SHMEDIA can use -;; the constant zero like a general register. -(define_predicate "sh_register_operand" - (match_code "reg,subreg,const_int,const_double") -{ - if (op == CONST0_RTX (mode) && TARGET_SHMEDIA) - return 1; - return register_operand (op, mode); -}) - ;; Returns true if OP is a vector which is composed of one element that is ;; repeated. (define_predicate "sh_rep_vec" @@ -972,38 +627,8 @@ { /* Allow T_REG as shift count for dynamic shifts, although it is not really possible. It will then be copied to a general purpose reg. */ - if (! TARGET_SHMEDIA) - return const_int_operand (op, mode) || arith_reg_operand (op, mode) - || (TARGET_DYNSHIFT && t_reg_operand (op, mode)); - - return (CONSTANT_P (op) - ? (CONST_INT_P (op) - ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode) - : nonmemory_operand (op, mode)) - : shift_count_reg_operand (op, mode)); -}) - -;; Returns true if OP is a valid shift count operand in a register which can -;; be used by shmedia shift insns. -(define_predicate "shift_count_reg_operand" - (match_code "subreg,reg,zero_extend,sign_extend") -{ - if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND - || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0)) - && (mode == VOIDmode || mode == GET_MODE (op)) - && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6 - && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT) - { - mode = VOIDmode; - do - op = XEXP (op, 0); - while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND - || GET_CODE (op) == TRUNCATE) - && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6 - && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT); - - } - return arith_reg_operand (op, mode); + return const_int_operand (op, mode) || arith_reg_operand (op, mode) + || (TARGET_DYNSHIFT && t_reg_operand (op, mode)); }) ;; Predicates for matching operands that are constant shift @@ -1029,105 +654,10 @@ (ior (match_test "! satisfies_constraint_P27 (op)") (match_test "satisfies_constraint_M (op)")))) -;; Returns true if OP is some kind of a shift operator. -(define_predicate "shift_operator" - (match_code "ashift,ashiftrt,lshiftrt")) - ;; Returns true if OP is a symbol reference. (define_predicate "symbol_ref_operand" (match_code "symbol_ref")) -;; Same as target_reg_operand, except that label_refs and symbol_refs -;; are accepted before reload. -(define_special_predicate "target_operand" - (match_code "subreg,reg,label_ref,symbol_ref,const,unspec") -{ - if (mode != VOIDmode && mode != Pmode) - return 0; - - if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode) - && satisfies_constraint_Csy (op)) - return ! reload_completed; - - return target_reg_operand (op, mode); -}) - -;; A predicate that accepts pseudos and branch target registers. -(define_special_predicate "target_reg_operand" - (match_code "subreg,reg") -{ - if (mode == VOIDmode - ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode - : mode != GET_MODE (op)) - return 0; - - if (GET_CODE (op) == SUBREG) - op = XEXP (op, 0); - - if (!REG_P (op)) - return 0; - - /* We must protect ourselves from matching pseudos that are virtual - register, because they will eventually be replaced with hardware - registers that aren't branch-target registers. */ - if (REGNO (op) > LAST_VIRTUAL_REGISTER - || TARGET_REGISTER_P (REGNO (op))) - return 1; - - return 0; -}) - -;; Returns true if OP is a valid operand for the shmedia mperm.w insn. -(define_special_predicate "trunc_hi_operand" - (match_code "subreg,reg,truncate") -{ - machine_mode op_mode = GET_MODE (op); - - if (op_mode != SImode && op_mode != DImode - && op_mode != V4HImode && op_mode != V2SImode) - return 0; - return extend_reg_operand (op, mode); -}) - -;; Returns true if OP is an address suitable for an unaligned access -;; instruction. -(define_special_predicate "ua_address_operand" - (match_code "subreg,reg,plus") -{ - if (GET_CODE (op) == PLUS - && (! satisfies_constraint_I06 (XEXP (op, 1)))) - return 0; - return address_operand (op, QImode); -}) - -;; Returns true if OP is a valid offset for an unaligned memory address. -(define_predicate "ua_offset" - (match_code "const_int") -{ - return satisfies_constraint_I06 (op); -}) - -;; Returns true if OP is a floating point operator with one operand. -(define_predicate "unary_float_operator" - (and (match_code "abs,neg,sqrt") - (match_test "GET_MODE (op) == mode"))) - -;; Return 1 if OP is a valid source operand for xor. -(define_predicate "xor_operand" - (match_code "subreg,reg,const_int") -{ - if (CONST_INT_P (op)) - return (TARGET_SHMEDIA - ? (satisfies_constraint_I06 (op) - || (!can_create_pseudo_p () && INTVAL (op) == 0xff)) - : satisfies_constraint_K08 (op)); - if (TARGET_SHMEDIA - && mode != DImode && GET_CODE (op) == SUBREG - && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4) - return 0; - return arith_reg_operand (op, mode); -}) - (define_predicate "bitwise_memory_operand" (match_code "mem") { diff --git a/gcc/config/sh/sh-c.c b/gcc/config/sh/sh-c.c index 4b2266d53af..b854a69c8ce 100644 --- a/gcc/config/sh/sh-c.c +++ b/gcc/config/sh/sh-c.c @@ -119,15 +119,6 @@ sh_cpu_cpp_builtins (cpp_reader* pfile) : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" : "__SH4_NOFPU__"); break; - case PROCESSOR_SH5: - { - builtin_define_with_value ("__SH5__", - TARGET_SHMEDIA64 ? "64" : "32", 0); - builtin_define_with_value ("__SHMEDIA__", - TARGET_SHMEDIA ? "1" : "0", 0); - if (! TARGET_FPU_DOUBLE) - builtin_define ("__SH4_NOFPU__"); - } } if (TARGET_FPU_ANY) builtin_define ("__SH_FPU_ANY__"); diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h index b08120d3737..537ab390797 100644 --- a/gcc/config/sh/sh-protos.h +++ b/gcc/config/sh/sh-protos.h @@ -124,7 +124,6 @@ extern enum rtx_code prepare_cbranch_operands (rtx *, machine_mode mode, extern void expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int); extern bool expand_cbranchdi4 (rtx *operands, enum rtx_code comparison); extern void sh_emit_scc_to_t (enum rtx_code, rtx, rtx); -extern rtx sh_emit_cheap_store_flag (machine_mode, enum rtx_code, rtx, rtx); extern void sh_emit_compare_and_branch (rtx *, machine_mode); extern void sh_emit_compare_and_set (rtx *, machine_mode); extern bool sh_ashlsi_clobbers_t_reg_p (rtx); @@ -140,7 +139,6 @@ extern bool gen_shl_and (rtx, rtx, rtx, rtx); extern int shl_sext_kind (rtx, rtx, int *); extern int shl_sext_length (rtx); extern bool gen_shl_sext (rtx, rtx, rtx, rtx); -extern rtx gen_datalabel_ref (rtx); extern int regs_used (rtx, int); extern void fixup_addr_diff_vecs (rtx_insn *); extern int get_dest_uid (rtx, int); @@ -149,8 +147,6 @@ extern enum tls_model tls_symbolic_operand (rtx, machine_mode); extern bool system_reg_operand (rtx, machine_mode); extern bool reg_unused_after (rtx, rtx_insn *); extern int sh_insn_length_adjustment (rtx_insn *); -extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx); -extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx); extern bool sh_expand_t_scc (rtx *); extern rtx sh_gen_truncate (machine_mode, rtx, int); extern bool sh_vector_mode_supported_p (machine_mode); diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index b18e59b1418..e6680afe070 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -67,15 +67,10 @@ along with GCC; see the file COPYING3. If not see int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; -/* These are some macros to abstract register modes. */ -#define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \ - && ((HOST_WIDE_INT)(VALUE)) <= 511) - -#define CONST_OK_FOR_ADD(size) \ - (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size)) -#define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi)) -#define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3)) -#define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3)) +#define CONST_OK_FOR_ADD(size) CONST_OK_FOR_I08 (size) +#define GEN_MOV (*(gen_movsi)) +#define GEN_ADD3 (*(gen_addsi3)) +#define GEN_SUB3 (*(gen_subsi3)) /* Used to simplify the logic below. Find the attributes wherever they may be. */ @@ -171,8 +166,6 @@ char sh_additional_register_names[ADDREGNAMES_SIZE] \ int assembler_dialect; -static bool shmedia_space_reserved_for_target_registers; - static void split_branches (rtx_insn *); static int branch_dest (rtx); static void print_slot (rtx_sequence *); @@ -239,7 +232,6 @@ static int sh_variable_issue (FILE *, int, rtx_insn *, int); static bool sh_function_ok_for_sibcall (tree, tree); -static bool sh_cannot_modify_jumps_p (void); static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *); static reg_class_t sh_target_reg_class (void); static bool sh_optimize_target_register_callee_saved (bool); @@ -274,13 +266,8 @@ static rtx sh_legitimize_address (rtx, rtx, machine_mode); static rtx sh_delegitimize_address (rtx); static bool sh_cannot_substitute_mem_equiv_p (rtx); static bool sh_legitimize_address_displacement (rtx *, rtx *, machine_mode); -static int shmedia_target_regs_stack_space (HARD_REG_SET *); -static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *); -static int shmedia_target_regs_stack_adjust (HARD_REG_SET *); static int scavenge_reg (HARD_REG_SET *s); struct save_schedule_s; -static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *, - struct save_schedule_s *, int); static rtx sh_struct_value_rtx (tree, int); static rtx sh_function_value (const_tree, const_tree, bool); @@ -312,7 +299,6 @@ static void sh_function_arg_advance (cumulative_args_t, machine_mode, const_tree, bool); static rtx sh_function_arg (cumulative_args_t, machine_mode, const_tree, bool); -static bool sh_scalar_mode_supported_p (machine_mode); static int sh_dwarf_calling_convention (const_tree); static void sh_encode_section_info (tree, rtx, int); static bool sh2a_function_vector_p (tree); @@ -483,8 +469,6 @@ static const struct attribute_spec sh_attribute_table[] = #undef TARGET_LEGITIMIZE_ADDRESS #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address -#undef TARGET_CANNOT_MODIFY_JUMPS_P -#define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p #undef TARGET_CAN_FOLLOW_JUMP #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump #undef TARGET_BRANCH_TARGET_REGISTER_CLASS @@ -573,8 +557,6 @@ static const struct attribute_spec sh_attribute_table[] = #undef TARGET_GIMPLIFY_VA_ARG_EXPR #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr -#undef TARGET_SCALAR_MODE_SUPPORTED_P -#define TARGET_SCALAR_MODE_SUPPORTED_P sh_scalar_mode_supported_p #undef TARGET_VECTOR_MODE_SUPPORTED_P #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p @@ -757,9 +739,6 @@ got_mode_name:; } /* Check that the selection makes sense. */ - if (TARGET_SHMEDIA && ret.type != sh_atomic_model::none) - err_ret ("atomic operations are not supported on SHmedia"); - if (ret.type == sh_atomic_model::soft_gusa && !TARGET_SH3) err_ret ("atomic model %s is only available on SH3 and SH4 targets", ret.name); @@ -859,73 +838,14 @@ sh_option_override (void) assembler_dialect = 1; sh_cpu = PROCESSOR_SH4A; } - if (TARGET_SH5) - { - sh_cpu = PROCESSOR_SH5; - target_flags |= MASK_ALIGN_DOUBLE; - if (TARGET_SHMEDIA_FPU) - target_flags |= MASK_FMOVD; - if (TARGET_SHMEDIA) - { - /* There are no delay slots on SHmedia. */ - flag_delayed_branch = 0; - /* Relaxation isn't yet supported for SHmedia */ - target_flags &= ~MASK_RELAX; - /* After reload, if conversion does little good but can cause - ICEs: - - find_if_block doesn't do anything for SH because we don't - have conditional execution patterns. (We use conditional - move patterns, which are handled differently, and only - before reload). - - find_cond_trap doesn't do anything for the SH because we - don't have conditional traps. - - find_if_case_1 uses redirect_edge_and_branch_force in - the only path that does an optimization, and this causes - an ICE when branch targets are in registers. - - find_if_case_2 doesn't do anything for the SHmedia after - reload except when it can redirect a tablejump - and - that's rather rare. */ - flag_if_conversion2 = 0; - if (! strcmp (sh_div_str, "call")) - sh_div_strategy = SH_DIV_CALL; - else if (! strcmp (sh_div_str, "call2")) - sh_div_strategy = SH_DIV_CALL2; - if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) - sh_div_strategy = SH_DIV_FP; - else if (! strcmp (sh_div_str, "inv")) - sh_div_strategy = SH_DIV_INV; - else if (! strcmp (sh_div_str, "inv:minlat")) - sh_div_strategy = SH_DIV_INV_MINLAT; - else if (! strcmp (sh_div_str, "inv20u")) - sh_div_strategy = SH_DIV_INV20U; - else if (! strcmp (sh_div_str, "inv20l")) - sh_div_strategy = SH_DIV_INV20L; - else if (! strcmp (sh_div_str, "inv:call2")) - sh_div_strategy = SH_DIV_INV_CALL2; - else if (! strcmp (sh_div_str, "inv:call")) - sh_div_strategy = SH_DIV_INV_CALL; - else if (! strcmp (sh_div_str, "inv:fp")) - { - if (TARGET_FPU_ANY) - sh_div_strategy = SH_DIV_INV_FP; - else - sh_div_strategy = SH_DIV_INV; - } - TARGET_CBRANCHDI4 = 0; - /* Assembler CFI isn't yet fully supported for SHmedia. */ - flag_dwarf2_cfi_asm = 0; - } - } - else - { - /* Only the sh64-elf assembler fully supports .quad properly. */ - targetm.asm_out.aligned_op.di = NULL; - targetm.asm_out.unaligned_op.di = NULL; - } - /* User/priviledged mode is supported only on SH3*, SH4* and SH5*. + /* Only the sh64-elf assembler fully supports .quad properly. */ + targetm.asm_out.aligned_op.di = NULL; + targetm.asm_out.unaligned_op.di = NULL; + + /* User/priviledged mode is supported only on SH3* and SH4*. Disable it for everything else. */ - if (! (TARGET_SH3 || TARGET_SH5) && TARGET_USERMODE) + if (!TARGET_SH3 && TARGET_USERMODE) TARGET_USERMODE = false; if (TARGET_SH1) @@ -934,7 +854,7 @@ sh_option_override (void) sh_div_strategy = SH_DIV_CALL_DIV1; else if (! strcmp (sh_div_str, "call-fp") && (TARGET_FPU_DOUBLE || TARGET_FPU_SINGLE_ONLY - || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) + || TARGET_FPU_ANY)) sh_div_strategy = SH_DIV_CALL_FP; else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT) sh_div_strategy = SH_DIV_CALL_TABLE; @@ -951,9 +871,6 @@ sh_option_override (void) /* These have their own way of doing things. */ else if (TARGET_SH2A) sh_div_strategy = SH_DIV_INTRINSIC; - /* ??? Should we use the integer SHmedia function instead? */ - else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) - sh_div_strategy = SH_DIV_CALL_FP; /* SH1 .. SH3 cores often go into small-footprint systems, so default to the smallest implementation available. */ else @@ -967,8 +884,6 @@ sh_option_override (void) sh_divsi3_libfunc = "__sdivsi3_i4"; else if (TARGET_DIVIDE_CALL_TABLE) sh_divsi3_libfunc = "__sdivsi3_i4i"; - else if (TARGET_SH5) - sh_divsi3_libfunc = "__sdivsi3_1"; else sh_divsi3_libfunc = "__sdivsi3"; @@ -1002,8 +917,7 @@ sh_option_override (void) if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) sh_additional_register_names[regno][0] = '\0'; - if ((flag_pic && ! TARGET_PREFERGOT) - || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) + if (flag_pic && ! TARGET_PREFERGOT) flag_no_function_cse = 1; if (targetm.small_register_classes_for_mode_p (VOIDmode)) @@ -1101,31 +1015,15 @@ sh_override_options_after_change (void) result in slightly faster code. Thus, it is set to the smallest alignment possible if not specified by the user. */ if (align_loops == 0) - { - if (TARGET_SH5) - align_loops = 8; - else - align_loops = optimize_size ? 2 : 4; - } + align_loops = optimize_size ? 2 : 4; if (align_jumps == 0) - { - if (TARGET_SHMEDIA) - align_jumps = 1 << CACHE_LOG; - else - align_jumps = 2; - } - else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) - align_jumps = TARGET_SHMEDIA ? 4 : 2; + align_jumps = 2; + else if (align_jumps < 2) + align_jumps = 2; if (align_functions == 0) - { - if (TARGET_SHMEDIA) - align_functions = optimize_size - ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); - else - align_functions = optimize_size ? 2 : 4; - } + align_functions = optimize_size ? 2 : 4; /* The linker relaxation code breaks when a function contains alignments that are larger than that at the start of a @@ -1210,8 +1108,7 @@ sh_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) 'R' print the LSW of a dp value - changes if in little endian 'S' print the MSW of a dp value - changes if in little endian 'T' print the next word of a dp value - same as 'R' in big endian mode. - 'M' SHMEDIA: print an `x' if `m' will print `base,index'. - otherwise: print .b / .w / .l / .s / .d suffix if operand is a MEM. + 'M' print .b / .w / .l / .s / .d suffix if operand is a MEM. 'N' print 'r63' if the operand is (const_int 0). 'd' print a V2SF reg as dN instead of fpN. 'm' print a pair `base,offset' or `base,index', for LD and ST. @@ -1393,27 +1290,16 @@ sh_print_operand (FILE *stream, rtx x, int code) } break; case 'M': - if (TARGET_SHMEDIA) - { - if (MEM_P (x) - && GET_CODE (XEXP (x, 0)) == PLUS - && (REG_P (XEXP (XEXP (x, 0), 1)) - || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG)) - fputc ('x', stream); - } - else + if (MEM_P (x)) { - if (MEM_P (x)) + switch (GET_MODE (x)) { - switch (GET_MODE (x)) - { - case QImode: fputs (".b", stream); break; - case HImode: fputs (".w", stream); break; - case SImode: fputs (".l", stream); break; - case SFmode: fputs (".s", stream); break; - case DFmode: fputs (".d", stream); break; - default: gcc_unreachable (); - } + case QImode: fputs (".b", stream); break; + case HImode: fputs (".w", stream); break; + case SImode: fputs (".l", stream); break; + case SFmode: fputs (".s", stream); break; + case DFmode: fputs (".d", stream); break; + default: gcc_unreachable (); } } break; @@ -1529,15 +1415,6 @@ sh_print_operand (FILE *stream, rtx x, int code) case SIGN_EXTEND: x = XEXP (x, 0); goto reg; - /* FIXME: We need this on SHmedia32 because reload generates - some sign-extended HI or QI loads into DImode registers - but, because Pmode is SImode, the address ends up with a - subreg:SI of the DImode register. Maybe reload should be - fixed so as to apply alter_subreg to such loads? */ - case IF_THEN_ELSE: - gcc_assert (trapping_target_operand (x, VOIDmode)); - x = XEXP (XEXP (x, 2), 0); - goto default_output; case SUBREG: gcc_assert (SUBREG_BYTE (x) == 0 && REG_P (SUBREG_REG (x))); @@ -1593,10 +1470,6 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x) { switch (XINT (x, 1)) { - case UNSPEC_DATALABEL: - fputs ("datalabel ", file); - output_addr_const (file, XVECEXP (x, 0, 0)); - break; case UNSPEC_PIC: /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ output_addr_const (file, XVECEXP (x, 0, 0)); @@ -1642,34 +1515,6 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x) assemble_name (file, name); } break; - case UNSPEC_EXTRACT_S16: - case UNSPEC_EXTRACT_U16: - { - rtx val, shift; - - val = XVECEXP (x, 0, 0); - shift = XVECEXP (x, 0, 1); - fputc ('(', file); - if (shift != const0_rtx) - fputc ('(', file); - if (GET_CODE (val) == CONST - || GET_RTX_CLASS (GET_CODE (val)) != RTX_OBJ) - { - fputc ('(', file); - output_addr_const (file, val); - fputc (')', file); - } - else - output_addr_const (file, val); - if (shift != const0_rtx) - { - fputs (" >> ", file); - output_addr_const (file, shift); - fputc (')', file); - } - fputs (" & 65535)", file); - } - break; case UNSPEC_SYMOFF: output_addr_const (file, XVECEXP (x, 0, 0)); fputc ('-', file); @@ -1732,10 +1577,6 @@ prepare_move_operands (rtx operands[], machine_mode mode) { if (MEM_P (operands[0])) operands[1] = force_reg (Pmode, operands[1]); - else if (TARGET_SHMEDIA - && GET_CODE (operands[1]) == LABEL_REF - && target_reg_operand (operands[0], mode)) - /* It's ok. */; else { temp = (!can_create_pseudo_p () @@ -1764,7 +1605,7 @@ prepare_move_operands (rtx operands[], machine_mode mode) { /* Copy the source to a register if both operands aren't registers. */ if (! register_operand (operands[0], mode) - && ! sh_register_operand (operands[1], mode)) + && ! register_operand (operands[1], mode)) operands[1] = copy_to_mode_reg (mode, operands[1]); if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode)) @@ -2484,60 +2325,6 @@ sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1) mode); } -rtx -sh_emit_cheap_store_flag (machine_mode mode, enum rtx_code code, - rtx op0, rtx op1) -{ - rtx target = gen_reg_rtx (SImode); - rtx tmp; - - gcc_assert (TARGET_SHMEDIA); - switch (code) - { - case EQ: - case GT: - case LT: - case UNORDERED: - case GTU: - case LTU: - tmp = gen_rtx_fmt_ee (code, SImode, op0, op1); - emit_insn (gen_cstore4_media (target, tmp, op0, op1)); - code = NE; - break; - - case NE: - case GE: - case LE: - case ORDERED: - case GEU: - case LEU: - tmp = gen_rtx_fmt_ee (reverse_condition (code), mode, op0, op1); - emit_insn (gen_cstore4_media (target, tmp, op0, op1)); - code = EQ; - break; - - case UNEQ: - case UNGE: - case UNGT: - case UNLE: - case UNLT: - case LTGT: - return NULL_RTX; - - default: - gcc_unreachable (); - } - - if (mode == DImode) - { - rtx t2 = gen_reg_rtx (DImode); - emit_insn (gen_extendsidi2 (t2, target)); - target = t2; - } - - return gen_rtx_fmt_ee (code, VOIDmode, target, const0_rtx); -} - /* Called from the md file, set up the operands of a compare instruction. */ void sh_emit_compare_and_branch (rtx *operands, machine_mode mode) @@ -2845,19 +2632,9 @@ output_far_jump (rtx_insn *insn, rtx op) print_slot (final_sequence); this_jmp.reg = gen_rtx_REG (SImode, 13); - /* We must keep the stack aligned to 8-byte boundaries on SH5. - Fortunately, MACL is fixed and call-clobbered, and we never - need its value across jumps, so save r13 in it instead of in - the stack. */ - if (TARGET_SH5) - output_asm_insn ("lds r13,macl", 0); - else - output_asm_insn ("mov.l r13,@-r15", 0); + output_asm_insn ("mov.l r13,@-r15", 0); output_asm_insn (jump, &this_jmp.lab); - if (TARGET_SH5) - output_asm_insn ("sts macl,r13", 0); - else - output_asm_insn ("mov.l @r15+,r13", 0); + output_asm_insn ("mov.l @r15+,r13", 0); } if (far && flag_pic && TARGET_SH2) { @@ -3049,15 +2826,6 @@ sh_file_start (void) if (TARGET_LITTLE_ENDIAN) fputs ("\t.little\n", asm_out_file); - - if (!TARGET_ELF) - { - if (TARGET_SHCOMPACT) - fputs ("\t.mode\tSHcompact\n", asm_out_file); - else if (TARGET_SHMEDIA) - fprintf (asm_out_file, "\t.mode\tSHmedia\n\t.abi\t%i\n", - TARGET_SHMEDIA64 ? 64 : 32); - } } /* Implementation of TARGET_ASM_INTEGER for SH. Pointers to functions @@ -3303,11 +3071,6 @@ sh_dynamicalize_shift_p (rtx count) static inline int shiftcosts (rtx x) { - int value; - - if (TARGET_SHMEDIA) - return 1; - if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) { if (GET_MODE (x) == DImode @@ -3324,7 +3087,7 @@ shiftcosts (rtx x) /* Otherwise, return the true cost in instructions. Cope with out of range shift counts more or less arbitrarily. */ - value = INTVAL (XEXP (x, 1)) & 31; + int value = INTVAL (XEXP (x, 1)) & 31; if (GET_CODE (x) == ASHIFTRT) { @@ -3345,9 +3108,7 @@ and_xor_ior_costs (rtx x, int code) { /* On SH1-4 we have only max. SImode operations. Double the cost for modes > SImode. */ - const int cost_scale = !TARGET_SHMEDIA - && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD - ? 2 : 1; + const int cost_scale = GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD ? 2 : 1; /* A logical operation with two registers is a single cycle instruction. */ @@ -3356,15 +3117,6 @@ and_xor_ior_costs (rtx x, int code) int i = INTVAL (XEXP (x, 1)); - if (TARGET_SHMEDIA) - { - if (satisfies_constraint_I10 (XEXP (x, 1)) - || satisfies_constraint_J16 (XEXP (x, 1))) - return 1; - else - return 1 + rtx_cost (XEXP (x, 1), GET_MODE (x), AND, 1, !optimize_size); - } - /* These constants are single cycle extu.[bw] instructions. */ if ((i == 0xff || i == 0xffff) && code == AND) return 1 * cost_scale; @@ -3423,9 +3175,7 @@ addsubcosts (rtx x) /* On SH1-4 we have only max. SImode operations. Double the cost for modes > SImode. */ - const int cost_scale = !TARGET_SHMEDIA - && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD - ? 2 : 1; + const int cost_scale = GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD ? 2 : 1; /* Adding a register is a single cycle insn. */ if (REG_P (XEXP (x, 1)) @@ -3437,27 +3187,6 @@ addsubcosts (rtx x) && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1)))) return 1 * cost_scale; - if (TARGET_SHMEDIA) - switch (GET_CODE (XEXP (x, 1))) - { - case CONST: - case LABEL_REF: - case SYMBOL_REF: - return TARGET_SHMEDIA64 ? 5 : 3; - - case CONST_INT: - if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)))) - return 2; - else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x, 1)) >> 16)) - return 3; - else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x, 1)) >> 16) >> 16)) - return 4; - - /* Fall through. */ - default: - return 5; - } - /* Any other constant requires a 2 cycle pc-relative load plus an addition. */ return 3 * cost_scale; @@ -3469,15 +3198,6 @@ multcosts (rtx x ATTRIBUTE_UNUSED) { if (sh_multcost >= 0) return sh_multcost; - if (TARGET_SHMEDIA) - /* ??? We have a mul insn, but it has a latency of three, and doesn't - accept constants. Ideally, we would use a cost of one or two and - add the cost of the operand, but disregard the latter when inside loops - and loop invariant code motion is still to follow. - Using a multiply first and splitting it later if it's a loss - doesn't work because of different sign / zero extension semantics - of multiplies vs. shifts. */ - return optimize_size ? 2 : 3; if (TARGET_SH2) { @@ -3630,26 +3350,6 @@ sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, return true; case CONST_INT: - if (TARGET_SHMEDIA) - { - if (INTVAL (x) == 0) - *total = 0; - else if (outer_code == AND && and_operand ((x), DImode)) - *total = 0; - else if ((outer_code == IOR || outer_code == XOR - || outer_code == PLUS) - && CONST_OK_FOR_I10 (INTVAL (x))) - *total = 0; - else if (CONST_OK_FOR_I16 (INTVAL (x))) - *total = COSTS_N_INSNS (outer_code != SET); - else if (CONST_OK_FOR_I16 (INTVAL (x) >> 16)) - *total = COSTS_N_INSNS ((outer_code != SET) + 1); - else if (CONST_OK_FOR_I16 ((INTVAL (x) >> 16) >> 16)) - *total = COSTS_N_INSNS ((outer_code != SET) + 2); - else - *total = COSTS_N_INSNS ((outer_code != SET) + 3); - return true; - } if (CONST_OK_FOR_I08 (INTVAL (x))) *total = 0; else if ((outer_code == AND || outer_code == IOR || outer_code == XOR) @@ -3713,21 +3413,14 @@ sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, case CONST: case LABEL_REF: case SYMBOL_REF: - if (TARGET_SHMEDIA64) - *total = COSTS_N_INSNS (4); - else if (TARGET_SHMEDIA32) - *total = COSTS_N_INSNS (2); - else - *total = 5; + *total = 5; return true; case CONST_DOUBLE: - if (TARGET_SHMEDIA) - *total = COSTS_N_INSNS (4); /* prepare_cmp_insn will force costly constants int registers before the cbranchdi4 pattern can see them, so preserve potentially interesting ones. */ - else if (outer_code == COMPARE && GET_MODE (x) == DImode) + if (outer_code == COMPARE && GET_MODE (x) == DImode) *total = 1; else *total = 10; @@ -3932,8 +3625,7 @@ sh_address_cost (rtx x, machine_mode mode, /* 'reg + reg' addressing. Account a slightly higher cost because of increased pressure on R0. */ - if (GET_CODE (x) == PLUS && ! CONSTANT_P (XEXP (x, 1)) - && ! TARGET_SHMEDIA) + if (GET_CODE (x) == PLUS && ! CONSTANT_P (XEXP (x, 1))) return 3; /* Not sure what it is - probably expensive. */ @@ -4704,30 +4396,6 @@ gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source) return false; } -/* Prefix a symbol_ref name with "datalabel". */ -rtx -gen_datalabel_ref (rtx sym) -{ - const char *str; - - if (GET_CODE (sym) == LABEL_REF) - return gen_rtx_CONST (GET_MODE (sym), - gen_rtx_UNSPEC (GET_MODE (sym), - gen_rtvec (1, sym), - UNSPEC_DATALABEL)); - - gcc_assert (GET_CODE (sym) == SYMBOL_REF); - - str = XSTR (sym, 0); - /* Share all SYMBOL_REF strings with the same value - that is important - for cse. */ - str = IDENTIFIER_POINTER (get_identifier (str)); - XSTR (sym, 0) = str; - - return sym; -} - - typedef struct label_ref_list_d { rtx_code_label *label; @@ -5252,7 +4920,6 @@ find_barrier (int num_mova, rtx_insn *mova, rtx_insn *from) int count_hi = 0; int found_hi = 0; int found_si = 0; - int found_di = 0; int hi_align = 2; int si_align = 2; int leading_mova = num_mova; @@ -5385,13 +5052,6 @@ find_barrier (int num_mova, rtx_insn *mova, rtx_insn *from) are higher. We may waste up to 4 additional bytes for alignment, and the DF/DI constant may have another SF/SI constant placed before it. */ - if (TARGET_SHCOMPACT - && ! found_di - && (mode == DFmode || mode == DImode)) - { - found_di = 1; - si_limit -= 8; - } while (si_align > 2 && found_si + si_align - 2 > count_si) si_align >>= 1; if (found_si > count_si) @@ -6078,7 +5738,7 @@ barrier_align (rtx_insn *barrier_or_label) return ((optimize_size || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat)) <= (unsigned) 1 << (CACHE_LOG - 2))) - ? 1 << TARGET_SHMEDIA : align_jumps_log); + ? 1 : align_jumps_log); } next = next_active_insn (barrier_or_label); @@ -6222,9 +5882,6 @@ sh_reorg (void) if (! optimize) split_all_insns_noflow (); - if (TARGET_SHMEDIA) - return; - /* If relaxing, generate pseudo-ops to associate function calls with the symbols they call. It does no harm to not generate these pseudo-ops. However, when we can generate them, it enables the @@ -6560,11 +6217,6 @@ sh_reorg (void) if (last_float && reg_set_between_p (r0_rtx, last_float_move, scan)) last_float = 0; - if (last_float - && TARGET_SHCOMPACT - && GET_MODE_SIZE (mode) != 4 - && GET_MODE_SIZE (GET_MODE (last_float)) == 4) - last_float = 0; lab = add_constant (src, mode, last_float); if (lab) emit_insn_before (gen_mova (lab), scan); @@ -7039,7 +6691,7 @@ output_stack_adjust (int size, rtx reg, int epilogue_p, { rtx const_reg; rtx insn; - int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1); + int temp = epilogue_p ? 7 : 1; int i; /* If TEMP is invalid, we could temporarily save a general @@ -7049,8 +6701,7 @@ output_stack_adjust (int size, rtx reg, int epilogue_p, || current_function_interrupt || ! call_really_used_regs[temp] || fixed_regs[temp]) temp = -1; - if (temp < 0 && ! current_function_interrupt - && (TARGET_SHMEDIA || epilogue_p >= 0)) + if (temp < 0 && ! current_function_interrupt && epilogue_p >= 0) { HARD_REG_SET temps; COPY_HARD_REG_SET (temps, call_used_reg_set); @@ -7074,9 +6725,6 @@ output_stack_adjust (int size, rtx reg, int epilogue_p, CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i)); } } - if (TARGET_SHMEDIA && epilogue_p < 0) - for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++) - CLEAR_HARD_REG_BIT (temps, i); if (epilogue_p <= 0) { for (i = FIRST_PARM_REG; @@ -7105,7 +6753,7 @@ output_stack_adjust (int size, rtx reg, int epilogue_p, would not be problem because it seems to be very rare. */ - gcc_assert (!TARGET_SHMEDIA && epilogue_p); + gcc_assert (epilogue_p); /* ??? There is still the slight possibility that r4 or @@ -7336,50 +6984,6 @@ push_regs (HARD_REG_SET *mask, int interrupt_handler) push (PR_REG); } -/* Calculate how much extra space is needed to save all callee-saved - target registers. - LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ -static int -shmedia_target_regs_stack_space (HARD_REG_SET *live_regs_mask) -{ - int reg; - int stack_space = 0; - int interrupt_handler = sh_cfun_interrupt_handler_p (); - - for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--) - if ((! call_really_used_regs[reg] || interrupt_handler) - && ! TEST_HARD_REG_BIT (*live_regs_mask, reg)) - /* Leave space to save this target register on the stack, - in case target register allocation wants to use it. */ - stack_space += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); - return stack_space; -} - -/* Decide whether we should reserve space for callee-save target registers, - in case target register allocation wants to use them. REGS_SAVED is - the space, in bytes, that is already required for register saves. - LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ -static int -shmedia_reserve_space_for_target_registers_p (int regs_saved, - HARD_REG_SET *live_regs_mask) -{ - if (optimize_size) - return 0; - return shmedia_target_regs_stack_space (live_regs_mask) <= regs_saved; -} - -/* Decide how much space to reserve for callee-save target registers - in case target register allocation wants to use them. - LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */ -static int -shmedia_target_regs_stack_adjust (HARD_REG_SET *live_regs_mask) -{ - if (shmedia_space_reserved_for_target_registers) - return shmedia_target_regs_stack_space (live_regs_mask); - else - return 0; -} - /* Work out the registers which need to be saved, both as a mask and a count of saved words. Return the count. @@ -7418,15 +7022,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) target_flags &= ~MASK_FPU_SINGLE; break; } - /* PR_MEDIA_REG is a general purpose register, thus global_alloc already - knows how to use it. That means the pseudo originally allocated for - the initial value can become the PR_MEDIA_REG hard register, as seen for - execute/20010122-1.c:test9. */ - if (TARGET_SHMEDIA) - /* ??? this function is called from initial_elimination_offset, hence we - can't use the result of sh_media_register_for_return here. */ - pr_live = sh_pr_n_sets (); - else + { rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG); pr_live = (pr_initial @@ -7440,15 +7036,10 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) } /* Force PR to be live if the prologue has to call the SHmedia argument decoder or register saver. */ - if (TARGET_SHCOMPACT - && ((crtl->args.info.call_cookie - & ~ CALL_COOKIE_RET_TRAMP (1)) - || crtl->saves_all_registers)) - pr_live = 1; - has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live; + has_call = pr_live; for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; ) { - if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) + if (reg == PR_REG ? pr_live : interrupt_handler ? (/* Need to save all the regs ever live. */ @@ -7456,10 +7047,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) || (call_really_used_regs[reg] && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG || reg == PIC_OFFSET_TABLE_REGNUM) - && has_call) - || (TARGET_SHMEDIA && has_call - && REGISTER_NATURAL_MODE (reg) == SImode - && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg)))) + && has_call)) && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM && reg != RETURN_ADDRESS_POINTER_REGNUM && reg != T_REG && reg != GBR_REG @@ -7467,10 +7055,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) /* Push fpscr only on targets which have FPU */ && (reg != FPSCR_REG || TARGET_FPU_ANY)) : (/* Only push those regs which are used and need to be saved. */ - (TARGET_SHCOMPACT - && flag_pic - && crtl->args.info.call_cookie - && reg == PIC_OFFSET_TABLE_REGNUM) + (false) || (df_regs_ever_live_p (reg) && ((!call_really_used_regs[reg] && !(reg != PIC_OFFSET_TABLE_REGNUM @@ -7489,7 +7074,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) SET_HARD_REG_BIT (*live_regs_mask, reg); count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg)); - if ((TARGET_SH4 || TARGET_SH2A_DOUBLE || TARGET_SH5) && TARGET_FMOVD + if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT) { if (FP_REGISTER_P (reg)) @@ -7513,9 +7098,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask) /* If we have a target register optimization pass after prologue / epilogue threading, we need to assume all target registers will be live even if they aren't now. */ - if (flag_branch_target_load_optimize2 - && TARGET_SAVE_ALL_TARGET_REGS - && shmedia_space_reserved_for_target_registers) + if (flag_branch_target_load_optimize2 && TARGET_SAVE_ALL_TARGET_REGS) for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--) if ((! call_really_used_regs[reg] || interrupt_handler) && ! TEST_HARD_REG_BIT (*live_regs_mask, reg)) @@ -7609,103 +7192,6 @@ typedef struct save_schedule_s int temps[MAX_TEMPS+1]; } save_schedule; -/* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero, - use reverse order. Returns the last entry written to (not counting - the delimiter). OFFSET_BASE is a number to be added to all offset - entries. */ -static save_entry * -sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule, - int offset_base) -{ - int align, i; - save_entry *entry = schedule->entries; - int tmpx = 0; - int offset; - - if (! current_function_interrupt) - for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++) - if (call_really_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG - && ! FUNCTION_ARG_REGNO_P (i) - && i != FIRST_RET_REG - && ! (cfun->static_chain_decl != NULL && i == STATIC_CHAIN_REGNUM) - && ! (crtl->calls_eh_return - && (i == EH_RETURN_STACKADJ_REGNO - || ((unsigned) i >= EH_RETURN_DATA_REGNO (0) - && (unsigned) i <= EH_RETURN_DATA_REGNO (3))))) - schedule->temps[tmpx++] = i; - entry->reg = -1; - entry->mode = VOIDmode; - entry->offset = offset_base; - entry++; - /* We loop twice: first, we save 8-byte aligned registers in the - higher addresses, that are known to be aligned. Then, we - proceed to saving 32-bit registers that don't need 8-byte - alignment. - If this is an interrupt function, all registers that need saving - need to be saved in full. moreover, we need to postpone saving - target registers till we have saved some general purpose registers - we can then use as scratch registers. */ - offset = offset_base; - for (align = 1; align >= 0; align--) - { - for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) - if (TEST_HARD_REG_BIT (*live_regs_mask, i)) - { - machine_mode mode = REGISTER_NATURAL_MODE (i); - int reg = i; - - if (current_function_interrupt) - { - if (TARGET_REGISTER_P (i)) - continue; - if (GENERAL_REGISTER_P (i)) - mode = DImode; - } - if (mode == SFmode && (i % 2) == 1 - && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i) - && (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1)))) - { - mode = DFmode; - i--; - reg--; - } - - /* If we're doing the aligned pass and this is not aligned, - or we're doing the unaligned pass and this is aligned, - skip it. */ - if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0) - != align) - continue; - - if (current_function_interrupt - && GENERAL_REGISTER_P (i) - && tmpx < MAX_TEMPS) - schedule->temps[tmpx++] = i; - - offset -= GET_MODE_SIZE (mode); - entry->reg = i; - entry->mode = mode; - entry->offset = offset; - entry++; - } - if (align && current_function_interrupt) - for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--) - if (TEST_HARD_REG_BIT (*live_regs_mask, i)) - { - offset -= GET_MODE_SIZE (DImode); - entry->reg = i; - entry->mode = DImode; - entry->offset = offset; - entry++; - } - } - entry->reg = -1; - entry->mode = VOIDmode; - entry->offset = offset; - schedule->temps[tmpx] = -1; - return entry - 1; -} - /* Expand code for the function prologue. */ void sh_expand_prologue (void) @@ -7734,48 +7220,6 @@ sh_expand_prologue (void) stack_pointer_rtx, 0, NULL, true); stack_usage = pretend_args + crtl->args.info.stack_regs * 8; - if (TARGET_SHCOMPACT && flag_pic && crtl->args.info.call_cookie) - /* We're going to use the PIC register to load the address of the - incoming-argument decoder and/or of the return trampoline from - the GOT, so make sure the PIC register is preserved and - initialized. */ - df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); - - if (TARGET_SHCOMPACT - && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1))) - { - int reg; - - /* First, make all registers with incoming arguments that will - be pushed onto the stack live, so that register renaming - doesn't overwrite them. */ - for (reg = 0; reg < NPARM_REGS (SImode); reg++) - if (CALL_COOKIE_STACKSEQ_GET (crtl->args.info.call_cookie) - >= NPARM_REGS (SImode) - reg) - for (; reg < NPARM_REGS (SImode); reg++) - emit_insn (gen_shcompact_preserve_incoming_args - (gen_rtx_REG (SImode, FIRST_PARM_REG + reg))); - else if (CALL_COOKIE_INT_REG_GET - (crtl->args.info.call_cookie, reg) == 1) - emit_insn (gen_shcompact_preserve_incoming_args - (gen_rtx_REG (SImode, FIRST_PARM_REG + reg))); - - emit_move_insn (gen_rtx_REG (Pmode, MACL_REG), - stack_pointer_rtx); - emit_move_insn (gen_rtx_REG (SImode, R0_REG), - GEN_INT (crtl->args.info.call_cookie)); - emit_move_insn (gen_rtx_REG (SImode, MACH_REG), - gen_rtx_REG (SImode, R0_REG)); - } - else if (TARGET_SHMEDIA) - { - int tr = sh_media_register_for_return (); - - if (tr >= 0) - emit_move_insn (gen_rtx_REG (DImode, tr), - gen_rtx_REG (DImode, PR_MEDIA_REG)); - } - /* Emit the code for SETUP_VARARGS. */ if (cfun->stdarg) { @@ -7819,222 +7263,13 @@ sh_expand_prologue (void) if (target_flags != save_flags && ! current_function_interrupt) emit_insn (gen_toggle_sz ()); - if (TARGET_SH5) - { - int offset_base, offset; - rtx r0 = NULL_RTX; - int offset_in_r0 = -1; - int sp_in_r0 = 0; - int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask); - int total_size, save_size; - save_schedule schedule; - save_entry *entry; - int *tmp_pnt; - - if (call_really_used_regs[R0_REG] && ! fixed_regs[R0_REG] - && ! current_function_interrupt) - r0 = gen_rtx_REG (Pmode, R0_REG); - - /* D is the actual number of bytes that we need for saving registers, - however, in initial_elimination_offset we have committed to using - an additional TREGS_SPACE amount of bytes - in order to keep both - addresses to arguments supplied by the caller and local variables - valid, we must keep this gap. Place it between the incoming - arguments and the actually saved registers in a bid to optimize - locality of reference. */ - total_size = d + tregs_space; - total_size += rounded_frame_size (total_size); - save_size = total_size - rounded_frame_size (d); - if (save_size % (STACK_BOUNDARY / BITS_PER_UNIT)) - d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) - - save_size % (STACK_BOUNDARY / BITS_PER_UNIT)); - - /* If adjusting the stack in a single step costs nothing extra, do so. - I.e. either if a single addi is enough, or we need a movi anyway, - and we don't exceed the maximum offset range (the test for the - latter is conservative for simplicity). */ - if (TARGET_SHMEDIA - && (CONST_OK_FOR_I10 (-total_size) - || (! CONST_OK_FOR_I10 (-(save_size + d_rounding)) - && total_size <= 2044))) - d_rounding = total_size - save_size; - - offset_base = d + d_rounding; - - output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx, - 0, NULL, true); - stack_usage += save_size + d_rounding; - - sh5_schedule_saves (&live_regs_mask, &schedule, offset_base); - tmp_pnt = schedule.temps; - for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++) - { - machine_mode mode = (machine_mode) entry->mode; - unsigned int reg = entry->reg; - rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX; - rtx orig_reg_rtx; - - offset = entry->offset; - - reg_rtx = gen_rtx_REG (mode, reg); - - mem_rtx = gen_frame_mem (mode, - gen_rtx_PLUS (Pmode, - stack_pointer_rtx, - GEN_INT (offset))); - - if (!memory_address_p (mode, XEXP (mem_rtx, 0))) - { - gcc_assert (r0); - mem_rtx = NULL_RTX; - } - - if (HAVE_PRE_DECREMENT - && (offset_in_r0 - offset == GET_MODE_SIZE (mode) - || mem_rtx == NULL_RTX - || reg == PR_REG || SPECIAL_REGISTER_P (reg))) - { - pre_dec = gen_frame_mem (mode, gen_rtx_PRE_DEC (Pmode, r0)); - - if (!memory_address_p (mode, XEXP (pre_dec, 0))) - pre_dec = NULL_RTX; - else - { - mem_rtx = NULL_RTX; - offset += GET_MODE_SIZE (mode); - } - } - - if (mem_rtx != NULL_RTX) - goto addr_ok; - - if (offset_in_r0 == -1) - { - emit_move_insn (r0, GEN_INT (offset)); - offset_in_r0 = offset; - } - else if (offset != offset_in_r0) - { - emit_move_insn (r0, - gen_rtx_PLUS - (Pmode, r0, - GEN_INT (offset - offset_in_r0))); - offset_in_r0 += offset - offset_in_r0; - } - - if (pre_dec != NULL_RTX) - { - if (! sp_in_r0) - { - emit_move_insn (r0, - gen_rtx_PLUS - (Pmode, r0, stack_pointer_rtx)); - sp_in_r0 = 1; - } - - offset -= GET_MODE_SIZE (mode); - offset_in_r0 -= GET_MODE_SIZE (mode); - - mem_rtx = pre_dec; - } - else if (sp_in_r0) - mem_rtx = gen_frame_mem (mode, r0); - else - mem_rtx = gen_frame_mem (mode, - gen_rtx_PLUS (Pmode, - stack_pointer_rtx, - r0)); - - /* We must not use an r0-based address for target-branch - registers or for special registers without pre-dec - memory addresses, since we store their values in r0 - first. */ - gcc_assert (!TARGET_REGISTER_P (reg) - && ((reg != PR_REG && !SPECIAL_REGISTER_P (reg)) - || mem_rtx == pre_dec)); - - addr_ok: - orig_reg_rtx = reg_rtx; - if (TARGET_REGISTER_P (reg) - || ((reg == PR_REG || SPECIAL_REGISTER_P (reg)) - && mem_rtx != pre_dec)) - { - rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt); - - emit_move_insn (tmp_reg, reg_rtx); - - if (REGNO (tmp_reg) == R0_REG) - { - offset_in_r0 = -1; - sp_in_r0 = 0; - gcc_assert (!refers_to_regno_p (R0_REG, mem_rtx)); - } - - if (*++tmp_pnt <= 0) - tmp_pnt = schedule.temps; - - reg_rtx = tmp_reg; - } - { - rtx insn; - - /* Mark as interesting for dwarf cfi generator */ - insn = emit_move_insn (mem_rtx, reg_rtx); - RTX_FRAME_RELATED_P (insn) = 1; - /* If we use an intermediate register for the save, we can't - describe this exactly in cfi as a copy of the to-be-saved - register into the temporary register and then the temporary - register on the stack, because the temporary register can - have a different natural size than the to-be-saved register. - Thus, we gloss over the intermediate copy and pretend we do - a direct save from the to-be-saved register. */ - if (REGNO (reg_rtx) != reg) - { - rtx set; - - set = gen_rtx_SET (mem_rtx, orig_reg_rtx); - add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); - } - - if (TARGET_SHCOMPACT && (offset_in_r0 != -1)) - { - rtx reg_rtx = gen_rtx_REG (mode, reg); - rtx set; - rtx mem_rtx = gen_frame_mem (mode, - gen_rtx_PLUS (Pmode, - stack_pointer_rtx, - GEN_INT (offset))); - - set = gen_rtx_SET (mem_rtx, reg_rtx); - add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); - } - } - } - - gcc_assert (entry->offset == d_rounding); - } - else - { - push_regs (&live_regs_mask, current_function_interrupt); - stack_usage += d; - } + push_regs (&live_regs_mask, current_function_interrupt); + stack_usage += d; if (flag_pic && !TARGET_FDPIC && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) emit_insn (gen_GOTaddr2picreg (const0_rtx)); - if (SHMEDIA_REGS_STACK_ADJUST ()) - { - /* This must NOT go through the PLT, otherwise mach and macl - may be clobbered. */ - function_symbol (gen_rtx_REG (Pmode, R0_REG), - (TARGET_FPU_ANY - ? "__GCC_push_shmedia_regs" - : "__GCC_push_shmedia_regs_nofpu"), SFUNC_GOT); - emit_insn (gen_shmedia_save_restore_regs_compact - (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ()))); - } - if (target_flags != save_flags && ! current_function_interrupt) emit_insn (gen_toggle_sz ()); @@ -8047,16 +7282,6 @@ sh_expand_prologue (void) if (frame_pointer_needed) frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx)); - if (TARGET_SHCOMPACT - && (crtl->args.info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1))) - { - /* This must NOT go through the PLT, otherwise mach and macl - may be clobbered. */ - function_symbol (gen_rtx_REG (Pmode, R0_REG), - "__GCC_shcompact_incoming_args", SFUNC_GOT); - emit_insn (gen_shcompact_incoming_args ()); - } - /* If we are profiling, make sure no instructions are scheduled before the call to mcount. Similarly if some call instructions are swapped before frame related insns, it'll confuse the unwinder because @@ -8086,32 +7311,6 @@ sh_expand_epilogue (bool sibcall_p) save_size = d; frame_size = rounded_frame_size (d); - if (TARGET_SH5) - { - int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask); - int total_size; - if (d % (STACK_BOUNDARY / BITS_PER_UNIT)) - d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) - - d % (STACK_BOUNDARY / BITS_PER_UNIT)); - - total_size = d + tregs_space; - total_size += rounded_frame_size (total_size); - save_size = total_size - frame_size; - - /* If adjusting the stack in a single step costs nothing extra, do so. - I.e. either if a single addi is enough, or we need a movi anyway, - and we don't exceed the maximum offset range (the test for the - latter is conservative for simplicity). */ - if (TARGET_SHMEDIA - && ! frame_pointer_needed - && (CONST_OK_FOR_I10 (total_size) - || (! CONST_OK_FOR_I10 (save_size + d_rounding) - && total_size <= 2044))) - d_rounding = frame_size; - - frame_size -= d_rounding; - } - if (frame_pointer_needed) { /* We must avoid scheduling the epilogue with previous basic blocks. @@ -8138,133 +7337,11 @@ sh_expand_epilogue (bool sibcall_p) &live_regs_mask, true); } - if (SHMEDIA_REGS_STACK_ADJUST ()) - { - function_symbol (gen_rtx_REG (Pmode, R0_REG), - (TARGET_FPU_ANY - ? "__GCC_pop_shmedia_regs" - : "__GCC_pop_shmedia_regs_nofpu"), SFUNC_GOT); - /* This must NOT go through the PLT, otherwise mach and macl - may be clobbered. */ - emit_insn (gen_shmedia_save_restore_regs_compact - (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ()))); - } - /* Pop all the registers. */ if (target_flags != save_flags && ! current_function_interrupt) emit_insn (gen_toggle_sz ()); - if (TARGET_SH5) - { - int offset_base, offset; - int offset_in_r0 = -1; - int sp_in_r0 = 0; - rtx r0 = gen_rtx_REG (Pmode, R0_REG); - save_schedule schedule; - save_entry *entry; - int *tmp_pnt; - - entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding); - offset_base = -entry[1].offset + d_rounding; - tmp_pnt = schedule.temps; - for (; entry->mode != VOIDmode; entry--) - { - machine_mode mode = (machine_mode) entry->mode; - int reg = entry->reg; - rtx reg_rtx, mem_rtx, post_inc = NULL_RTX; - - offset = offset_base + entry->offset; - reg_rtx = gen_rtx_REG (mode, reg); - - mem_rtx = gen_frame_mem (mode, - gen_rtx_PLUS (Pmode, - stack_pointer_rtx, - GEN_INT (offset))); - - if (!memory_address_p (mode, XEXP (mem_rtx, 0))) - mem_rtx = NULL_RTX; - - if (HAVE_POST_INCREMENT - && (offset == offset_in_r0 - || (offset + GET_MODE_SIZE (mode) != d + d_rounding - && mem_rtx == NULL_RTX) - || reg == PR_REG || SPECIAL_REGISTER_P (reg))) - { - post_inc = gen_frame_mem (mode, gen_rtx_POST_INC (Pmode, r0)); - - if (!memory_address_p (mode, XEXP (post_inc, 0))) - post_inc = NULL_RTX; - else - mem_rtx = NULL_RTX; - } - - if (mem_rtx != NULL_RTX) - goto addr_ok; - - if (offset_in_r0 == -1) - { - emit_move_insn (r0, GEN_INT (offset)); - offset_in_r0 = offset; - } - else if (offset != offset_in_r0) - { - emit_move_insn (r0, - gen_rtx_PLUS - (Pmode, r0, - GEN_INT (offset - offset_in_r0))); - offset_in_r0 += offset - offset_in_r0; - } - - if (post_inc != NULL_RTX) - { - if (! sp_in_r0) - { - emit_move_insn (r0, - gen_rtx_PLUS - (Pmode, r0, stack_pointer_rtx)); - sp_in_r0 = 1; - } - - mem_rtx = post_inc; - offset_in_r0 += GET_MODE_SIZE (mode); - } - else if (sp_in_r0) - mem_rtx = gen_frame_mem (mode, r0); - else - mem_rtx = gen_frame_mem (mode, - gen_rtx_PLUS (Pmode, - stack_pointer_rtx, - r0)); - - gcc_assert ((reg != PR_REG && !SPECIAL_REGISTER_P (reg)) - || mem_rtx == post_inc); - - addr_ok: - if ((reg == PR_REG || SPECIAL_REGISTER_P (reg)) - && mem_rtx != post_inc) - { - emit_move_insn (r0, mem_rtx); - mem_rtx = r0; - } - else if (TARGET_REGISTER_P (reg)) - { - rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt); - - /* Give the scheduler a bit of freedom by using up to - MAX_TEMPS registers in a round-robin fashion. */ - emit_move_insn (tmp_reg, mem_rtx); - mem_rtx = tmp_reg; - if (*++tmp_pnt < 0) - tmp_pnt = schedule.temps; - } - - emit_move_insn (reg_rtx, mem_rtx); - } - - gcc_assert (entry->offset + offset_base == d + d_rounding); - } - else /* ! TARGET_SH5 */ { int last_reg; @@ -8376,58 +7453,20 @@ void sh_set_return_address (rtx ra, rtx tmp) { HARD_REG_SET live_regs_mask; - int d; - int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG; - int pr_offset; - - d = calc_live_regs (&live_regs_mask); + int d = calc_live_regs (&live_regs_mask); /* If pr_reg isn't life, we can set it (or the register given in sh_media_register_for_return) directly. */ - if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg)) + if (! TEST_HARD_REG_BIT (live_regs_mask, PR_REG)) { - rtx rr; - - if (TARGET_SHMEDIA) - { - int rr_regno = sh_media_register_for_return (); - - if (rr_regno < 0) - rr_regno = pr_reg; - - rr = gen_rtx_REG (DImode, rr_regno); - } - else - rr = gen_rtx_REG (SImode, pr_reg); - + rtx rr = gen_rtx_REG (SImode, PR_REG); emit_insn (GEN_MOV (rr, ra)); /* Tell flow the register for return isn't dead. */ emit_use (rr); return; } - if (TARGET_SH5) - { - int offset; - save_schedule schedule; - save_entry *entry; - - entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0); - offset = entry[1].offset; - for (; entry->mode != VOIDmode; entry--) - if (entry->reg == pr_reg) - goto found; - - /* We can't find pr register. */ - gcc_unreachable (); - - found: - offset = entry->offset - offset; - pr_offset = (rounded_frame_size (d) + offset - + SHMEDIA_REGS_STACK_ADJUST ()); - } - else - pr_offset = rounded_frame_size (d); + int pr_offset = rounded_frame_size (d); emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset))); @@ -8464,55 +7503,18 @@ sh_builtin_saveregs (void) int bufsize, regno; alias_set_type alias_set; - if (TARGET_SH5) - { - if (n_intregs) - { - int pushregs = n_intregs; - - while (pushregs < NPARM_REGS (SImode) - 1 - && (CALL_COOKIE_INT_REG_GET - (crtl->args.info.call_cookie, - NPARM_REGS (SImode) - pushregs) - == 1)) - { - crtl->args.info.call_cookie - &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) - - pushregs, 1); - pushregs++; - } - - if (pushregs == NPARM_REGS (SImode)) - crtl->args.info.call_cookie - |= (CALL_COOKIE_INT_REG (0, 1) - | CALL_COOKIE_STACKSEQ (pushregs - 1)); - else - crtl->args.info.call_cookie - |= CALL_COOKIE_STACKSEQ (pushregs); - - crtl->args.pretend_args_size += 8 * n_intregs; - } - if (TARGET_SHCOMPACT) - return const0_rtx; - } - - if (! TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH5) + if (! TARGET_SH2E && ! TARGET_SH4) { error ("__builtin_saveregs not supported by this subtarget"); return const0_rtx; } - if (TARGET_SHMEDIA) - n_floatregs = 0; - /* Allocate block of memory for the regs. */ /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte? Or can assign_stack_local accept a 0 SIZE argument? */ bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD); - if (TARGET_SHMEDIA) - regbuf = gen_frame_mem (BLKmode, gen_rtx_REG (Pmode, ARG_POINTER_REGNUM)); - else if (n_floatregs & 1) + if (n_floatregs & 1) { rtx addr; @@ -8546,10 +7548,6 @@ sh_builtin_saveregs (void) n_floatregs * UNITS_PER_WORD), n_intregs); - if (TARGET_SHMEDIA) - /* Return the address of the regbuf. */ - return XEXP (regbuf, 0); - /* Save float args. This is optimized to only save the regs that are necessary. Explicitly named args need not be saved. @@ -8604,7 +7602,7 @@ sh_build_builtin_va_list (void) tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; tree record, type_decl; - if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4) + if ((! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI || sh_cfun_attr_renesas_p ()) return ptr_type_node; @@ -8658,13 +7656,6 @@ sh_va_start (tree valist, rtx nextarg) tree t, u; int nfp, nint; - if (TARGET_SH5) - { - expand_builtin_saveregs (); - std_expand_builtin_va_start (valist, nextarg); - return; - } - if ((! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI || sh_cfun_attr_renesas_p ()) { @@ -8771,7 +7762,7 @@ sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; pptr_type_node = build_pointer_type (ptr_type_node); - if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4) + if ((TARGET_SH2E || TARGET_SH4) && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ())) { tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack; @@ -9004,37 +7995,9 @@ sh_promote_prototypes (const_tree type) return ! sh_attr_renesas_p (type); } -/* Whether an argument must be passed by reference. On SHcompact, we - pretend arguments wider than 32-bits that would have been passed in - registers are passed by reference, so that an SHmedia trampoline - loads them into the full 64-bits registers. */ -static int -shcompact_byref (const CUMULATIVE_ARGS *cum, machine_mode mode, - const_tree type, bool named) -{ - unsigned HOST_WIDE_INT size; - - if (type) - size = int_size_in_bytes (type); - else - size = GET_MODE_SIZE (mode); - - if (cum->arg_count[SH_ARG_INT] < NPARM_REGS (SImode) - && (!named - || GET_SH_ARG_CLASS (mode) == SH_ARG_INT - || (GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT - && cum->arg_count[SH_ARG_FLOAT] >= NPARM_REGS (SFmode))) - && size > 4 - && !SHCOMPACT_FORCE_ON_STACK (mode, type) - && !SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named)) - return size; - else - return 0; -} - static bool sh_pass_by_reference (cumulative_args_t cum_v, machine_mode mode, - const_tree type, bool named) + const_tree type, bool named ATTRIBUTE_UNUSED) { CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); @@ -9047,12 +8010,6 @@ sh_pass_by_reference (cumulative_args_t cum_v, machine_mode mode, if (! cum) return false; - if (TARGET_SHCOMPACT) - { - cum->byref = shcompact_byref (cum, mode, type, named); - return cum->byref != 0; - } - return false; } @@ -9123,8 +8080,7 @@ sh_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); int words = 0; - if (!TARGET_SH5 - && sh_pass_in_reg_p (*cum, mode, type) + if (sh_pass_in_reg_p (*cum, mode, type) && !(TARGET_SH4 || TARGET_SH2A_DOUBLE) && (sh_round_reg (*cum, mode) + (mode != BLKmode @@ -9133,10 +8089,6 @@ sh_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, > NPARM_REGS (mode))) words = NPARM_REGS (mode) - sh_round_reg (*cum, mode); - else if (!TARGET_SHCOMPACT - && SH5_WOULD_BE_PARTIAL_NREGS (*cum, mode, type, named)) - words = NPARM_REGS (SImode) - cum->arg_count[SH_ARG_INT]; - return words * UNITS_PER_WORD; } @@ -9164,11 +8116,10 @@ sh_function_arg (cumulative_args_t ca_v, machine_mode mode, { CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); - if (! TARGET_SH5 && mode == VOIDmode) - return GEN_INT (ca->renesas_abi ? 1 : 0); + if (mode == VOIDmode) + return ca->renesas_abi ? const1_rtx : const0_rtx; - if (! TARGET_SH5 - && sh_pass_in_reg_p (*ca, mode, type) + if (sh_pass_in_reg_p (*ca, mode, type) && (named || ! (TARGET_HITACHI || ca->renesas_abi))) { int regno; @@ -9205,41 +8156,6 @@ sh_function_arg (cumulative_args_t ca_v, machine_mode mode, } - if (TARGET_SH5) - { - if (mode == VOIDmode && TARGET_SHCOMPACT) - return GEN_INT (ca->call_cookie); - - /* The following test assumes unnamed arguments are promoted to - DFmode. */ - if (mode == SFmode && ca->free_single_fp_reg) - return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg); - - if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT) - && (named || ! ca->prototype_p) - && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) - { - if (! ca->prototype_p && TARGET_SHMEDIA) - return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode); - - return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, - FIRST_FP_PARM_REG - + ca->arg_count[(int) SH_ARG_FLOAT]); - } - - if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) - && (! TARGET_SHCOMPACT - || (! SHCOMPACT_FORCE_ON_STACK (mode, type) - && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode, - type, named)))) - { - return gen_rtx_REG (mode, (FIRST_PARM_REG - + ca->arg_count[(int) SH_ARG_INT])); - } - - return NULL_RTX; - } - return NULL_RTX; } @@ -9249,120 +8165,12 @@ sh_function_arg (cumulative_args_t ca_v, machine_mode mode, available.) */ static void sh_function_arg_advance (cumulative_args_t ca_v, machine_mode mode, - const_tree type, bool named) + const_tree type, bool named ATTRIBUTE_UNUSED) { CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); if (ca->force_mem) ca->force_mem = 0; - else if (TARGET_SH5) - { - const_tree type2 = (ca->byref && type - ? TREE_TYPE (type) - : type); - machine_mode mode2 = (ca->byref && type - ? TYPE_MODE (type2) - : mode); - int dwords = ((ca->byref - ? ca->byref - : mode2 == BLKmode - ? int_size_in_bytes (type2) - : GET_MODE_SIZE (mode2)) + 7) / 8; - int numregs = MIN (dwords, NPARM_REGS (SImode) - - ca->arg_count[(int) SH_ARG_INT]); - - if (numregs) - { - ca->arg_count[(int) SH_ARG_INT] += numregs; - if (TARGET_SHCOMPACT - && SHCOMPACT_FORCE_ON_STACK (mode2, type2)) - { - ca->call_cookie - |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT] - - numregs, 1); - /* N.B. We want this also for outgoing. */ - ca->stack_regs += numregs; - } - else if (ca->byref) - { - if (! ca->outgoing) - ca->stack_regs += numregs; - ca->byref_regs += numregs; - ca->byref = 0; - do - ca->call_cookie - |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT] - - numregs, 2); - while (--numregs); - ca->call_cookie - |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT] - - 1, 1); - } - else if (dwords > numregs) - { - int pushregs = numregs; - - if (TARGET_SHCOMPACT) - ca->stack_regs += numregs; - while (pushregs < NPARM_REGS (SImode) - 1 - && (CALL_COOKIE_INT_REG_GET - (ca->call_cookie, - NPARM_REGS (SImode) - pushregs) - == 1)) - { - ca->call_cookie - &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) - - pushregs, 1); - pushregs++; - } - if (numregs == NPARM_REGS (SImode)) - ca->call_cookie - |= CALL_COOKIE_INT_REG (0, 1) - | CALL_COOKIE_STACKSEQ (numregs - 1); - else - ca->call_cookie - |= CALL_COOKIE_STACKSEQ (numregs); - } - } - if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT - && (named || ! ca->prototype_p)) - { - if (mode2 == SFmode && ca->free_single_fp_reg) - ca->free_single_fp_reg = 0; - else if (ca->arg_count[(int) SH_ARG_FLOAT] - < NPARM_REGS (SFmode)) - { - int numfpregs - = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2, - NPARM_REGS (SFmode) - - ca->arg_count[(int) SH_ARG_FLOAT]); - - ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs; - - if (TARGET_SHCOMPACT && ! ca->prototype_p) - { - if (ca->outgoing && numregs > 0) - do - { - ca->call_cookie - |= (CALL_COOKIE_INT_REG - (ca->arg_count[(int) SH_ARG_INT] - - numregs + ((numfpregs - 2) / 2), - 4 + (ca->arg_count[(int) SH_ARG_FLOAT] - - numfpregs) / 2)); - } - while (numfpregs -= 2); - } - else if (mode2 == SFmode && (named) - && (ca->arg_count[(int) SH_ARG_FLOAT] - < NPARM_REGS (SFmode))) - ca->free_single_fp_reg - = FIRST_FP_PARM_REG - numfpregs - + ca->arg_count[(int) SH_ARG_FLOAT] + 1; - } - } - return; - } if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE) { @@ -9429,7 +8237,7 @@ sh_function_value (const_tree valtype, || TREE_CODE (valtype) == REAL_TYPE || TREE_CODE (valtype) == OFFSET_TYPE)) && sh_promote_prototypes (fn_decl_or_type) - ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (valtype)), + ? SImode : TYPE_MODE (valtype)), BASE_RETURN_VALUE_REG (TYPE_MODE (valtype))); } @@ -9444,28 +8252,16 @@ sh_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) static bool sh_function_value_regno_p (const unsigned int regno) { - return ((regno) == FIRST_RET_REG - || (TARGET_SH2E && (regno) == FIRST_FP_RET_REG) - || (TARGET_SHMEDIA_FPU && (regno) == FIRST_FP_RET_REG)); + return regno == FIRST_RET_REG || (TARGET_SH2E && regno == FIRST_FP_RET_REG); } /* Worker function for TARGET_RETURN_IN_MEMORY. */ static bool sh_return_in_memory (const_tree type, const_tree fndecl) { - if (TARGET_SH5) - { - if (TYPE_MODE (type) == BLKmode) - return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8; - else - return GET_MODE_SIZE (TYPE_MODE (type)) > 8; - } - else - { - return (TYPE_MODE (type) == BLKmode - || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl)) - && TREE_CODE (type) == RECORD_TYPE)); - } + return TYPE_MODE (type) == BLKmode + || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl)) + && TREE_CODE (type) == RECORD_TYPE); } /* We actually emit the code in sh_expand_prologue. We used to use @@ -9498,7 +8294,7 @@ sh_setup_incoming_varargs (cumulative_args_t ca, static bool sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) { - return TARGET_SH5; + return false; } static bool @@ -9506,7 +8302,7 @@ sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v) { CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); - return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5; + return ! (TARGET_HITACHI || ca->renesas_abi); } @@ -9520,25 +8316,11 @@ initial_elimination_offset (int from, int to) int total_saved_regs_space; int total_auto_space; int save_flags = target_flags; - int copy_flags; HARD_REG_SET live_regs_mask; - shmedia_space_reserved_for_target_registers = false; regs_saved = calc_live_regs (&live_regs_mask); - regs_saved += SHMEDIA_REGS_STACK_ADJUST (); - - if (shmedia_reserve_space_for_target_registers_p (regs_saved, &live_regs_mask)) - { - shmedia_space_reserved_for_target_registers = true; - regs_saved += shmedia_target_regs_stack_adjust (&live_regs_mask); - } - - if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT)) - regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT) - - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT)); total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding; - copy_flags = target_flags; target_flags = save_flags; total_saved_regs_space = regs_saved + regs_saved_rounding; @@ -9564,32 +8346,7 @@ initial_elimination_offset (int from, int to) gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM && (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM)); - if (TARGET_SH5) - { - int n = total_saved_regs_space; - int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG; - save_schedule schedule; - save_entry *entry; - - n += total_auto_space; - - /* If it wasn't saved, there's not much we can do. */ - if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg)) - return n; - - target_flags = copy_flags; - - sh5_schedule_saves (&live_regs_mask, &schedule, n); - for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++) - if (entry->reg == pr_reg) - { - target_flags = save_flags; - return entry->offset; - } - gcc_unreachable (); - } - else - return total_auto_space; + return total_auto_space; } /* Parse the -mfixed-range= option string. */ @@ -9799,11 +8556,6 @@ sh_handle_interrupt_handler_attribute (tree *node, tree name, name); *no_add_attrs = true; } - else if (TARGET_SHCOMPACT) - { - error ("attribute interrupt_handler is not compatible with -m5-compact"); - *no_add_attrs = true; - } return NULL_TREE; } @@ -10398,20 +9150,6 @@ sh_legitimate_index_p (machine_mode mode, rtx op, bool consider_sh2a, if (! CONST_INT_P (op)) return false; - if (TARGET_SHMEDIA) - { - int size; - - /* Check if this is the address of an unaligned load / store. */ - if (mode == VOIDmode) - return satisfies_constraint_I06 (op); - - size = GET_MODE_SIZE (mode); - return (!(INTVAL (op) & (size - 1)) - && INTVAL (op) >= -512 * size - && INTVAL (op) < 512 * size); - } - else { const HOST_WIDE_INT offset = INTVAL (op); const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a); @@ -10443,17 +9181,12 @@ sh_legitimate_index_p (machine_mode mode, rtx op, bool consider_sh2a, static bool sh_legitimate_address_p (machine_mode mode, rtx x, bool strict) { - if (! ALLOW_INDEXED_ADDRESS - && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))) - return false; - if (REG_P (x) && REGNO (x) == GBR_REG) return true; if (MAYBE_BASE_REGISTER_RTX_P (x, strict)) return true; else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) - && ! TARGET_SHMEDIA && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict)) return true; else if (GET_CODE (x) == PLUS) @@ -10469,17 +9202,9 @@ sh_legitimate_address_p (machine_mode mode, rtx x, bool strict) && sh_legitimate_index_p (mode, xop1, TARGET_SH2A, false)) return true; - if ((ALLOW_INDEXED_ADDRESS || GET_MODE (x) == DImode - || ((xop0 == stack_pointer_rtx - || xop0 == hard_frame_pointer_rtx) - && REG_P (xop1) && REGNO (xop1) == R0_REG) - || ((xop1 == stack_pointer_rtx - || xop1 == hard_frame_pointer_rtx) - && REG_P (xop0) && REGNO (xop0) == R0_REG)) - && ((!TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 4) - || (TARGET_SHMEDIA && GET_MODE_SIZE (mode) <= 8) - || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) - && TARGET_FMOVD && mode == DFmode))) + if (GET_MODE_SIZE (mode) <= 4 + || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) + && TARGET_FMOVD && mode == DFmode)) { if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict) && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict)) @@ -10664,9 +9389,6 @@ sh_legitimize_address (rtx x, rtx oldx, machine_mode mode) if (flag_pic) x = legitimize_pic_address (oldx, mode, NULL_RTX); - if (TARGET_SHMEDIA) - return x; - if (((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) || (TARGET_SH2E && mode == SFmode)) return x; @@ -10702,36 +9424,8 @@ sh_legitimize_reload_address (rtx *p, machine_mode mode, int opnum, if (sh_lra_p ()) return false; - if (! ALLOW_INDEXED_ADDRESS - && GET_CODE (*p) == PLUS - && REG_P (XEXP (*p, 0)) && REG_P (XEXP (*p, 1))) - { - *p = copy_rtx (*p); - push_reload (*p, NULL_RTX, p, NULL, - BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - return true; - } - - if (! ALLOW_INDEXED_ADDRESS - && GET_CODE (*p) == PLUS - && GET_CODE (XEXP (*p, 0)) == PLUS) - { - rtx sum = gen_rtx_PLUS (Pmode, XEXP (XEXP (*p, 0), 0), - XEXP (XEXP (*p, 0), 1)); - *p = gen_rtx_PLUS (Pmode, sum, XEXP (*p, 1)); - push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL, - BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type); - return true; - } - - if (TARGET_SHMEDIA) - return false; - if (GET_CODE (*p) == PLUS && CONST_INT_P (XEXP (*p, 1)) - && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true) - && (ALLOW_INDEXED_ADDRESS - || XEXP (*p, 0) == stack_pointer_rtx - || XEXP (*p, 0) == hard_frame_pointer_rtx)) + && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true)) { const HOST_WIDE_INT offset = INTVAL (XEXP (*p, 1)); struct disp_adjust adj = sh_find_mov_disp_adjust (mode, offset); @@ -10822,17 +9516,6 @@ sh_delegitimize_address (rtx orig_x) return XVECEXP (symplt, 0, 0); } } - else if (TARGET_SHMEDIA - && (XINT (y, 1) == UNSPEC_EXTRACT_S16 - || XINT (y, 1) == UNSPEC_EXTRACT_U16)) - { - rtx offset = XVECEXP (y, 0, 1); - - x = gen_rtx_PLUS (Pmode, XVECEXP (y, 0, 0), offset); - if (MEM_P (orig_x)) - x = replace_equiv_address_nv (orig_x, x); - return x; - } } } @@ -10974,64 +9657,7 @@ sh_adjust_cost (rtx_insn *insn, rtx link ATTRIBUTE_UNUSED, { rtx reg, use_pat; - if (TARGET_SHMEDIA) - { - /* On SHmedia, if the dependence is an anti-dependence or - output-dependence, there is no cost. */ - if (REG_NOTE_KIND (link) != 0) - { - /* However, dependencies between target register loads and - uses of the register in a subsequent block that are separated - by a conditional branch are not modelled - we have to do with - the anti-dependency between the target register load and the - conditional branch that ends the current block. */ - if (REG_NOTE_KIND (link) == REG_DEP_ANTI - && GET_CODE (PATTERN (dep_insn)) == SET - && (get_attr_type (dep_insn) == TYPE_PT_MEDIA - || get_attr_type (dep_insn) == TYPE_PTABS_MEDIA) - && get_attr_type (insn) == TYPE_CBRANCH_MEDIA) - { - int orig_cost = cost; - rtx note = find_reg_note (insn, REG_BR_PROB, 0); - rtx target = ((!note || XINT (note, 0) * 2 < REG_BR_PROB_BASE) - ? insn : JUMP_LABEL (insn)); - /* On the likely path, the branch costs 1, on the unlikely path, - it costs 3. */ - cost--; - do - target = next_active_insn (target); - while (target && ! flow_dependent_p (target, dep_insn) - && --cost > 0); - /* If two branches are executed in immediate succession, with the - first branch properly predicted, this causes a stall at the - second branch, hence we won't need the target for the - second branch for two cycles after the launch of the first - branch. */ - if (cost > orig_cost - 2) - cost = orig_cost - 2; - } - else - cost = 0; - } - - else if (get_attr_is_mac_media (insn) - && get_attr_is_mac_media (dep_insn)) - cost = 1; - - else if (! reload_completed - && GET_CODE (PATTERN (insn)) == SET - && GET_CODE (SET_SRC (PATTERN (insn))) == FLOAT - && GET_CODE (PATTERN (dep_insn)) == SET - && fp_arith_reg_operand (SET_SRC (PATTERN (dep_insn)), VOIDmode) - && cost < 4) - cost = 4; - /* Schedule the ptabs for a casesi_jump_media in preference to stuff - that is needed at the target. */ - else if (get_attr_type (insn) == TYPE_JUMP_MEDIA - && ! flow_dependent_p (insn, dep_insn)) - cost--; - } - else if (REG_NOTE_KIND (link) == 0) + if (REG_NOTE_KIND (link) == 0) { enum attr_type type; rtx dep_set; @@ -11190,7 +9816,7 @@ flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) static int sh_pr_n_sets (void) { - return DF_REG_DEF_COUNT (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG); + return DF_REG_DEF_COUNT (PR_REG); } /* Return where to allocate pseudo for a given hard register initial @@ -11198,24 +9824,15 @@ sh_pr_n_sets (void) static rtx sh_allocate_initial_value (rtx hard_reg) { - rtx x; - - if (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)) + if (REGNO (hard_reg) == PR_REG) { - if (crtl->is_leaf - && ! sh_pr_n_sets () - && ! (TARGET_SHCOMPACT - && ((crtl->args.info.call_cookie - & ~ CALL_COOKIE_RET_TRAMP (1)) - || crtl->saves_all_registers))) - x = hard_reg; + if (crtl->is_leaf && ! sh_pr_n_sets ()) + return hard_reg; else - x = gen_frame_mem (Pmode, return_address_pointer_rtx); + return gen_frame_mem (Pmode, return_address_pointer_rtx); } - else - x = NULL_RTX; - return x; + return NULL_RTX; } /* This function returns "2" to indicate dual issue for the SH4 @@ -11442,17 +10059,6 @@ sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED, } } -/* The scalar modes supported differs from the default version in TImode - for 32-bit SHMEDIA. */ -static bool -sh_scalar_mode_supported_p (machine_mode mode) -{ - if (TARGET_SHMEDIA32 && mode == TImode) - return false; - - return default_scalar_mode_supported_p (mode); -} - /* Cache the can_issue_more so that we can return it from reorder2. Also, keep count of register pressures on SImode and SFmode. */ static int @@ -11583,38 +10189,23 @@ sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED, return 0; } -/* SHmedia requires registers for branches, so we can't generate new - branches past reload. */ -static bool -sh_cannot_modify_jumps_p (void) -{ - return (TARGET_SHMEDIA && (reload_in_progress || reload_completed)); -} - static reg_class_t sh_target_reg_class (void) { - return TARGET_SHMEDIA ? TARGET_REGS : NO_REGS; + return NO_REGS; } static bool -sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen) +sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen + ATTRIBUTE_UNUSED) { - if (! shmedia_space_reserved_for_target_registers) - return 0; - if (after_prologue_epilogue_gen && ! TARGET_SAVE_ALL_TARGET_REGS) - return 0; - - HARD_REG_SET dummy; - if (calc_live_regs (&dummy) >= 6 * 8) - return 1; - return 0; + return false; } static bool sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED) { - return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type)); + return TARGET_HITACHI || sh_attr_renesas_p (record_type); } /* @@ -11669,130 +10260,6 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0)); - if (TARGET_SHMEDIA64) - { - rtx tramp_templ; - int fixed_len; - - rtx movi1 = GEN_INT (0xcc000010); - rtx shori1 = GEN_INT (0xc8000010); - rtx src, dst; - - /* The following trampoline works within a +- 128 KB range for cxt: - ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0; - shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0 - gettr tr1,r1; blink tr0,r63 */ - /* Address rounding makes it hard to compute the exact bounds of the - offset for this trampoline, but we have a rather generous offset - range, so frame_offset should do fine as an upper bound. */ - if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000) - { - /* ??? could optimize this trampoline initialization - by writing DImode words with two insns each. */ - rtx mask = force_reg (DImode, GEN_INT (0x3fffc00)); - rtx insn = gen_rtx_MINUS (DImode, cxt, tramp); - insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2)); - insn = gen_rtx_AND (DImode, insn, mask); - /* Or in ptb/u .,tr1 pattern */ - insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode)); - insn = force_operand (insn, NULL_RTX); - insn = gen_lowpart (SImode, insn); - emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), insn); - insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38)); - insn = gen_rtx_AND (DImode, insn, mask); - insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX); - insn = gen_lowpart (SImode, insn); - emit_move_insn (adjust_address (tramp_mem, SImode, 4), insn); - insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22)); - insn = gen_rtx_AND (DImode, insn, mask); - insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX); - insn = gen_lowpart (SImode, insn); - emit_move_insn (adjust_address (tramp_mem, SImode, 8), insn); - insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6)); - insn = gen_rtx_AND (DImode, insn, mask); - insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX); - insn = gen_lowpart (SImode, insn); - emit_move_insn (adjust_address (tramp_mem, SImode, 12), insn); - insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10)); - insn = gen_rtx_AND (DImode, insn, mask); - insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX); - insn = gen_lowpart (SImode, insn); - emit_move_insn (adjust_address (tramp_mem, SImode, 16), insn); - emit_move_insn (adjust_address (tramp_mem, SImode, 20), - GEN_INT (0x6bf10600)); - emit_move_insn (adjust_address (tramp_mem, SImode, 24), - GEN_INT (0x4415fc10)); - emit_move_insn (adjust_address (tramp_mem, SImode, 28), - GEN_INT (0x4401fff0)); - emit_insn (gen_ic_invalidate_line (tramp)); - return; - } - tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline"); - fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode); - - tramp_templ = gen_datalabel_ref (tramp_templ); - dst = tramp_mem; - src = gen_const_mem (BLKmode, tramp_templ); - set_mem_align (dst, 256); - set_mem_align (src, 64); - emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL); - - emit_move_insn (adjust_address (tramp_mem, Pmode, fixed_len), fnaddr); - emit_move_insn (adjust_address (tramp_mem, Pmode, - fixed_len + GET_MODE_SIZE (Pmode)), - cxt); - emit_insn (gen_ic_invalidate_line (tramp)); - return; - } - else if (TARGET_SHMEDIA) - { - /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0 - movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */ - rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode); - rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode); - /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated, - rotated 10 right, and higher 16 bit of every 32 selected. */ - rtx movishori - = force_reg (V2HImode, (simplify_gen_subreg - (V2HImode, GEN_INT (0x4330432), SImode, 0))); - rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600)); - rtx blink = force_reg (DImode, GEN_INT (0x4401fff0)); - - fnaddr = force_reg (SImode, fnaddr); - cxt = force_reg (SImode, cxt); - emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0), - gen_rtx_SUBREG (V2HImode, fnaddr, 0), - movishori)); - emit_insn (gen_rotrdi3_mextr (quad0, quad0, - GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56))); - emit_insn (gen_ashldi3_media (quad0, quad0, const2_rtx)); - emit_move_insn (change_address (tramp_mem, DImode, NULL_RTX), quad0); - emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0), - gen_rtx_SUBREG (V2HImode, cxt, 0), - movishori)); - emit_insn (gen_rotrdi3_mextr (cxtload, cxtload, - GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56))); - emit_insn (gen_ashldi3_media (cxtload, cxtload, const2_rtx)); - if (TARGET_LITTLE_ENDIAN) - { - emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload)); - emit_insn (gen_mextr4 (quad2, cxtload, blink)); - } - else - { - emit_insn (gen_mextr4 (quad1, cxtload, ptabs)); - emit_insn (gen_mshflo_l_di (quad2, blink, cxtload)); - } - emit_move_insn (adjust_address (tramp_mem, DImode, 8), quad1); - emit_move_insn (adjust_address (tramp_mem, DImode, 16), quad2); - emit_insn (gen_ic_invalidate_line (tramp)); - return; - } - else if (TARGET_SHCOMPACT) - { - emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr)); - return; - } if (TARGET_FDPIC) { rtx a = force_reg (Pmode, plus_constant (Pmode, XEXP (tramp_mem, 0), 8)); @@ -11815,7 +10282,7 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) sh_emit_storesi (tramp_mem, 8, cxt); sh_emit_storesi (tramp_mem, 12, fnaddr); } - if (TARGET_HARD_SH4 || TARGET_SH5) + if (TARGET_HARD_SH4) { if (!TARGET_INLINE_IC_INVALIDATE || (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE)) @@ -11831,9 +10298,6 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) static rtx sh_trampoline_adjust_address (rtx tramp) { - if (TARGET_SHMEDIA) - tramp = expand_simple_binop (Pmode, PLUS, tramp, const1_rtx, - gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); return tramp; } @@ -11847,8 +10311,6 @@ static bool sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) { return (1 - && (! TARGET_SHCOMPACT - || crtl->args.info.stack_regs == 0) && ! sh_cfun_interrupt_handler_p () && (! flag_pic || TARGET_FDPIC || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl))) @@ -11881,12 +10343,6 @@ struct builtin_description tree fndecl; }; -static bool -shmedia_builtin_p (void) -{ - return TARGET_SHMEDIA; -} - /* This function can be used if there are any built-ins that are not for SHmedia. It's commented out to avoid the defined-but-unused warning. */ static bool @@ -11967,173 +10423,6 @@ static const char signature_args[][4] = /* nsb: takes long long arg, returns unsigned char. */ static struct builtin_description bdesc[] = { - { shmedia_builtin_p, - CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2, 0 }, - { shmedia_builtin_p, - CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2, 0 }, - { shmedia_builtin_p, - CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_alloco_i, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV, 0 }, - { shmedia_builtin_p, - CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU, 0 }, - { shmedia_builtin_p, - CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI, 0 }, - { shmedia_builtin_p, - CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI, 0 }, - { shmedia_builtin_p, - CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI, 0 }, - { shmedia_builtin_p, - CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI, 0 }, - { shmedia_builtin_p, - CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI, 0 }, - { shmedia_builtin_p, - CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI, 0 }, - { shmedia_builtin_p, - CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU, 0 }, - { shmedia_builtin_p, - CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI, 0 }, - { shmedia_builtin_p, - CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI, 0 }, - { shmedia_builtin_p, - CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI, 0 }, - { shmedia_builtin_p, - CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI, 0 }, - { shmedia_builtin_p, - CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI, 0 }, - { shmedia_builtin_p, - CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI, 0 }, - { shmedia_builtin_p, - CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI, 0 }, - { shmedia_builtin_p, - CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3, 0 }, - { shmedia_builtin_p, - CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF, 0 }, - { shmedia_builtin_p, - CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF, 0 }, - { shmedia_builtin_p, - CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3, 0 }, - { shmedia_builtin_p, - CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3, 0 }, - { shmedia_builtin_p, - CODE_FOR_sqrtdf2, "__builtin_sh_media_FSQRT_D", SH_BLTIN_2, 0 }, - { shmedia_builtin_p, - CODE_FOR_sqrtsf2, "__builtin_sh_media_FSQRT_S", SH_BLTIN_2, 0 }, - { shmedia_builtin_p, - CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2, 0 }, - { shmedia_builtin_p, - CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L, 0 }, - { shmedia_builtin_p, - CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q, 0 }, - { shmedia_builtin_p, - CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L, 0 }, - { shmedia_builtin_p, - CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q, 0 }, - { shmedia_builtin_p, - CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L, 0 }, - { shmedia_builtin_p, - CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q, 0 }, - { shmedia_builtin_p, - CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L, 0 }, - { shmedia_builtin_p, - CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q, 0 }, - { shmedia_builtin_p, - CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L64, 0 }, - { shmedia_builtin_p, - CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q64, 0 }, - { shmedia_builtin_p, - CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L64, 0 }, - { shmedia_builtin_p, - CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q64, 0 }, - { shmedia_builtin_p, - CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L64, 0 }, - { shmedia_builtin_p, - CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q64, 0 }, - { shmedia_builtin_p, - CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L64, 0 }, - { shmedia_builtin_p, - CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q64, 0 }, - { shmedia_builtin_p, - CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU, 0 }, - { shmedia_builtin_p, - CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2, 0 }, - { shmedia_builtin_p, - CODE_FOR_prefetch, "__builtin_sh_media_PREFO", SH_BLTIN_PSSV, 0 }, - { sh1_builtin_p, CODE_FOR_sts_fpscr, "__builtin_sh_get_fpscr", SH_BLTIN_UV, 0 }, { sh1_builtin_p, @@ -12166,10 +10455,6 @@ sh_init_builtins (void) int has_result = signature_args[signature][0] != 0; tree args[3]; - if ((signature_args[signature][1] & 8) - && (((signature_args[signature][1] & 1) && TARGET_SHMEDIA32) - || ((signature_args[signature][1] & 2) && TARGET_SHMEDIA64))) - continue; if (! TARGET_FPU_ANY && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode)) continue; @@ -12283,21 +10568,8 @@ sh_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) /* Implements target hook vector_mode_supported_p. */ bool -sh_vector_mode_supported_p (machine_mode mode) +sh_vector_mode_supported_p (machine_mode mode ATTRIBUTE_UNUSED) { - if (TARGET_SHMEDIA_FPU - && ((mode == V2SFmode) - || (mode == V4SFmode) - || (mode == V16SFmode))) - return true; - - else if (TARGET_SHMEDIA - && ((mode == V8QImode) - || (mode == V2HImode) - || (mode == V4HImode) - || (mode == V2SImode))) - return true; - return false; } @@ -12424,27 +10696,6 @@ sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return target; } -void -sh_expand_unop_v2sf (enum rtx_code code, rtx op0, rtx op1) -{ - rtx sel0 = const0_rtx; - rtx sel1 = const1_rtx; - rtx (*fn) (rtx, rtx, rtx, rtx, rtx) = gen_unary_sf_op; - rtx op = gen_rtx_fmt_e (code, SFmode, op1); - - emit_insn ((*fn) (op0, op1, op, sel0, sel0)); - emit_insn ((*fn) (op0, op1, op, sel1, sel1)); -} - -void -sh_expand_binop_v2sf (enum rtx_code code, rtx op0, rtx op1, rtx op2) -{ - rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2); - - emit_insn (gen_binary_sf_op0 (op0, op1, op2, op)); - emit_insn (gen_binary_sf_op1 (op0, op1, op2, op)); -} - /* Return true if hard register REGNO can hold a value of machine-mode MODE. We can allow any mode in any general register. The special registers only allow SImode. Don't allow any mode in the PR. @@ -12491,30 +10742,17 @@ sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode) } if (mode == V16SFmode) - { - if (TARGET_SHMEDIA) - { - if (FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 16 == 0) - return true; - else - return false; - } - else - return regno == FIRST_XD_REG; - } + return regno == FIRST_XD_REG; if (FP_REGISTER_P (regno)) { if (mode == SFmode || mode == SImode - || ((TARGET_SH2E || TARGET_SHMEDIA) && mode == SCmode) + || ((TARGET_SH2E) && mode == SCmode) || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) - || mode == DCmode - || (TARGET_SHMEDIA - && (mode == DFmode || mode == DImode - || mode == V2SFmode || mode == TImode))) + || mode == DCmode) && ((regno - FIRST_FP_REG) & 1) == 0) - || ((TARGET_SH4 || TARGET_SHMEDIA) && mode == TImode + || (TARGET_SH4 && mode == TImode && ((regno - FIRST_FP_REG) & 3) == 0)) return true; else @@ -12533,16 +10771,6 @@ sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode) if (regno == FPSCR_REG) return mode == SImode; - /* FIXME. This works around PR target/37633 for -O0. */ - if (!optimize && TARGET_SHMEDIA32 && GET_MODE_SIZE (mode) > 4) - { - unsigned int n = GET_MODE_SIZE (mode) / 8; - - if (regno >= FIRST_GENERAL_REG + 10 - n + 1 - && regno <= FIRST_GENERAL_REG + 14) - return false; - } - return true; } @@ -12603,7 +10831,7 @@ sh_cannot_change_mode_class (machine_mode from, machine_mode to, bool sh_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED) { - return (! TARGET_SHMEDIA); + return true; } /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times @@ -12640,7 +10868,7 @@ sh_register_move_cost (machine_mode mode, if (dstclass == MAC_REGS && srcclass == MAC_REGS) return 4; - if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD + if (mode == SImode && TARGET_FMOVD && REGCLASS_HAS_FP_REG (srcclass) && REGCLASS_HAS_FP_REG (dstclass)) return 4; @@ -12662,8 +10890,8 @@ sh_register_move_cost (machine_mode mode, of SImode on this target. See PR target/48596. */ int addend = (mode == Pmode) ? 40 : 0; - return (((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12) + addend) - * ((GET_MODE_SIZE (mode) + 7) / 8U)); + return ((TARGET_FMOVD ? 8 : 12) + addend) + * ((GET_MODE_SIZE (mode) + 7) / 8U); } if ((dstclass == FPUL_REGS @@ -12682,24 +10910,13 @@ sh_register_move_cost (machine_mode mode, || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass))) return 20; - /* ??? ptabs faults on (value & 0x3) == 0x3 */ - if (TARGET_SHMEDIA - && ((srcclass) == TARGET_REGS || (srcclass) == SIBCALL_REGS)) - { - if (sh_gettrcost >= 0) - return sh_gettrcost; - else if (!TARGET_PT_FIXED) - return 100; - } - if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass)) || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass))) return 4; - if (TARGET_SHMEDIA - || (TARGET_FMOVD - && ! REGCLASS_HAS_GENERAL_REG (srcclass) - && ! REGCLASS_HAS_GENERAL_REG (dstclass))) + if (TARGET_FMOVD + && ! REGCLASS_HAS_GENERAL_REG (srcclass) + && ! REGCLASS_HAS_GENERAL_REG (dstclass)) return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U); return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U); @@ -12728,7 +10945,6 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, int simple_add = CONST_OK_FOR_ADD (delta); int did_load = 0; rtx scratch0, scratch1, scratch2; - unsigned i; reload_completed = 1; epilogue_completed = 1; @@ -12763,7 +10979,7 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, if (! call_used_regs[0] || fixed_regs[0]) error ("r0 needs to be available as a call-clobbered register"); scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0); - if (! TARGET_SH5) + { if (call_used_regs[1] && ! fixed_regs[1]) scratch1 = gen_rtx_REG (ptr_mode, 1); @@ -12772,26 +10988,6 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, if (call_used_regs[3] && ! fixed_regs[3]) scratch2 = gen_rtx_REG (Pmode, 3); } - else if (TARGET_SHMEDIA) - { - for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++) - if (i != REGNO (scratch0) && - call_used_regs[i] && ! fixed_regs[i] && ! FUNCTION_ARG_REGNO_P (i)) - { - scratch1 = gen_rtx_REG (ptr_mode, i); - break; - } - if (scratch1 == scratch0) - error ("need a second call-clobbered general purpose register"); - for (i = FIRST_TARGET_REG; i <= LAST_TARGET_REG; i++) - if (call_used_regs[i] && ! fixed_regs[i]) - { - scratch2 = gen_rtx_REG (Pmode, i); - break; - } - if (scratch2 == scratch0) - error ("need a call-clobbered target register"); - } this_value = plus_constant (Pmode, this_rtx, delta); if (vcall_offset @@ -12822,7 +11018,7 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, offset_addr = plus_constant (Pmode, scratch0, vcall_offset); if (strict_memory_address_p (ptr_mode, offset_addr)) ; /* Do nothing. */ - else if (! TARGET_SH5 && scratch0 != scratch1) + else if (scratch0 != scratch1) { /* scratch0 != scratch1, and we have indexed loads. Get better schedule by loading the offset into r1 and using an indexed @@ -12880,11 +11076,6 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, } else { - if (TARGET_SHMEDIA && flag_pic) - { - funexp = gen_sym2PIC (funexp); - PUT_MODE (funexp, Pmode); - } emit_move_insn (scratch2, funexp); funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2); sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX); @@ -12997,17 +11188,6 @@ scavenge_reg (HARD_REG_SET *s) rtx sh_get_pr_initial_val (void) { - rtx val; - - /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the - PR register on SHcompact, because it might be clobbered by the prologue. - We check first if that is known to be the case. */ - if (TARGET_SHCOMPACT - && ((crtl->args.info.call_cookie - & ~ CALL_COOKIE_RET_TRAMP (1)) - || crtl->saves_all_registers)) - return gen_frame_mem (SImode, return_address_pointer_rtx); - /* If we haven't finished rtl generation, there might be a nonlocal label that we haven't seen yet. ??? get_hard_reg_initial_val fails if it is called after register @@ -13020,11 +11200,8 @@ sh_get_pr_initial_val (void) combine can put the pseudo returned by get_hard_reg_initial_val into instructions that need a general purpose registers, which will fail to be recognized when the pseudo becomes allocated to PR. */ - val - = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG); - if (TARGET_SH1) - return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA); - return val; + rtx val = get_hard_reg_initial_val (Pmode, PR_REG); + return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA); } bool @@ -13165,17 +11342,7 @@ sh_init_cumulative_args (CUMULATIVE_ARGS * pcum, pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi) && aggregate_value_p (TREE_TYPE (fntype), fndecl)); pcum->prototype_p = prototype_p (fntype); - pcum->arg_count [(int) SH_ARG_INT] - = TARGET_SH5 && aggregate_value_p (TREE_TYPE (fntype), fndecl); - - pcum->call_cookie - = CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT - && pcum->arg_count [(int) SH_ARG_INT] == 0 - && (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode - ? int_size_in_bytes (TREE_TYPE (fntype)) - : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (fntype)))) > 4 - && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE (fntype))) - == FIRST_RET_REG)); + pcum->arg_count [(int) SH_ARG_INT] = false; } else { @@ -13183,11 +11350,6 @@ sh_init_cumulative_args (CUMULATIVE_ARGS * pcum, pcum->prototype_p = FALSE; if (mode != VOIDmode) { - pcum->call_cookie = - CALL_COOKIE_RET_TRAMP (TARGET_SHCOMPACT - && GET_MODE_SIZE (mode) > 4 - && BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG); - /* If the default ABI is the Renesas ABI then all library calls must assume that the library will be using the Renesas ABI. So if the function would return its result @@ -13204,10 +11366,7 @@ sh_init_cumulative_args (CUMULATIVE_ARGS * pcum, && TARGET_FPU_DOUBLE))); } else - { - pcum->call_cookie = 0; - pcum->force_mem = FALSE; - } + pcum->force_mem = FALSE; } } @@ -13235,32 +11394,6 @@ sh_gen_truncate (machine_mode mode, rtx x, int need_sign_ext) return gen_rtx_fmt_e (code, mode, x); } -/* Look through X cleaning up truncates of registers that span multiple - actual hard registers. Return the number of changes made. */ -int -shmedia_cleanup_truncate (rtx x) -{ - int n_changes = 0; - subrtx_var_iterator::array_type array; - FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST) - { - rtx x = *iter; - if (GET_CODE (x) == TRUNCATE) - { - rtx reg = XEXP (x, 0); - machine_mode reg_mode = GET_MODE (reg); - if (REG_P (reg) && GET_MODE_SIZE (reg_mode) > 8) - { - int offset = subreg_lowpart_offset (DImode, reg_mode); - XEXP (x, 0) = simplify_subreg (DImode, reg, reg_mode, offset); - n_changes += 1; - iter.skip_subrtxes (); - } - } - } - return n_changes; -} - /* Load and store depend on the highpart of the address. However, set_attr_alternative does not give well-defined results before reload, so we must look at the rtl ourselves to see if any of the feeding @@ -13291,65 +11424,10 @@ sh_loads_bankedreg_p (rtx insn) return false; } -/* FNADDR is the MEM expression from a call expander. Return an address - to use in an SHmedia insn pattern. */ -rtx -shmedia_prepare_call_address (rtx fnaddr, int is_sibcall) -{ - int is_sym; - - fnaddr = XEXP (fnaddr, 0); - is_sym = GET_CODE (fnaddr) == SYMBOL_REF; - if (flag_pic && is_sym) - { - if (! SYMBOL_REF_LOCAL_P (fnaddr)) - { - rtx reg = gen_reg_rtx (Pmode); - - /* We must not use GOTPLT for sibcalls, because PIC_REG - must be restored before the PLT code gets to run. */ - if (is_sibcall) - emit_insn (gen_symGOT2reg (reg, fnaddr)); - else - emit_insn (gen_symGOTPLT2reg (reg, fnaddr)); - fnaddr = reg; - } - else - { - fnaddr = gen_sym2PIC (fnaddr); - PUT_MODE (fnaddr, Pmode); - } - } - /* If ptabs might trap, make this visible to the rest of the compiler. - We generally assume that symbols pertain to valid locations, but - it is possible to generate invalid symbols with asm or linker tricks. - In a list of functions where each returns its successor, an invalid - symbol might denote an empty list. */ - if (!TARGET_PT_FIXED - && (!is_sym || TARGET_INVALID_SYMBOLS) - && (!REG_P (fnaddr) || ! TARGET_REGISTER_P (REGNO (fnaddr)))) - { - rtx tr = gen_reg_rtx (PDImode); - - emit_insn (gen_ptabs (tr, fnaddr)); - fnaddr = tr; - } - else if (! target_reg_operand (fnaddr, Pmode)) - fnaddr = copy_to_mode_reg (Pmode, fnaddr); - return fnaddr; -} - /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ static reg_class_t -sh_preferred_reload_class (rtx x, reg_class_t rclass) +sh_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass) { - if (rclass == NO_REGS - && TARGET_SHMEDIA - && (CONST_DOUBLE_P (x) - || GET_CODE (x) == SYMBOL_REF - || PIC_ADDR_P (x))) - return GENERAL_REGS; - return rclass; } @@ -13374,7 +11452,6 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, if (in_p) { if (REGCLASS_HAS_FP_REG (rclass) - && ! TARGET_SHMEDIA && immediate_operand ((x), mode) && ! ((fp_zero_operand (x) || fp_one_operand (x)) && mode == SFmode)) switch (mode) @@ -13410,22 +11487,6 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER) || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS))) return GENERAL_REGS; - if (REGCLASS_HAS_FP_REG (rclass) - && TARGET_SHMEDIA - && immediate_operand (x, mode) - && x != CONST0_RTX (GET_MODE (x)) - && GET_MODE (x) != V4SFmode) - return GENERAL_REGS; - if ((mode == QImode || mode == HImode) - && TARGET_SHMEDIA && inqhi_operand (x, mode)) - { - sri->icode = ((mode == QImode) - ? CODE_FOR_reload_inqi : CODE_FOR_reload_inhi); - return NO_REGS; - } - if (TARGET_SHMEDIA && rclass == GENERAL_REGS - && (GET_CODE (x) == LABEL_REF || PIC_ADDR_P (x))) - return TARGET_REGS; } /* end of input-only processing. */ if (((REGCLASS_HAS_FP_REG (rclass) @@ -13436,12 +11497,10 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, || (REGCLASS_HAS_GENERAL_REG (rclass) && REG_P (x) && FP_REGISTER_P (REGNO (x)))) - && ! TARGET_SHMEDIA && (mode == SFmode || mode == SImode)) return FPUL_REGS; if ((rclass == FPUL_REGS - || (REGCLASS_HAS_FP_REG (rclass) - && ! TARGET_SHMEDIA && mode == SImode)) + || (REGCLASS_HAS_FP_REG (rclass) && mode == SImode)) && (MEM_P (x) || (REG_P (x) && (REGNO (x) >= FIRST_PSEUDO_REGISTER @@ -13452,8 +11511,7 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, return GENERAL_REGS; return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS; } - if ((rclass == TARGET_REGS - || (TARGET_SHMEDIA && rclass == SIBCALL_REGS)) + if (rclass == TARGET_REGS && !satisfies_constraint_Csy (x) && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x)))) return GENERAL_REGS; @@ -13501,9 +11559,6 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, static bool sh_cannot_substitute_mem_equiv_p (rtx) { - if (TARGET_SHMEDIA) - return false; - /* If SUBST is mem[base+index] or QI/HImode mem[base+disp], the insn uses R0 and may cause spill failure when R0 is already used. We have to return true for that case at least. @@ -13520,9 +11575,6 @@ static bool sh_legitimize_address_displacement (rtx *disp, rtx *offs, machine_mode mode) { - if (TARGET_SHMEDIA) - return false; - if (((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode) || (TARGET_SH2E && mode == SFmode)) return false; @@ -13575,19 +11627,6 @@ sh_conditional_register_usage (void) if (! VALID_REGISTER_P (regno)) fixed_regs[regno] = call_used_regs[regno] = 1; /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ - if (TARGET_SH5) - { - call_used_regs[FIRST_GENERAL_REG + 8] - = call_used_regs[FIRST_GENERAL_REG + 9] = 1; - call_really_used_regs[FIRST_GENERAL_REG + 8] - = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; - } - if (TARGET_SHMEDIA) - { - regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; - CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); - regno_reg_class[FIRST_FP_REG] = FP_REGS; - } if (flag_pic) { fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; @@ -13606,16 +11645,9 @@ sh_conditional_register_usage (void) call_really_used_regs[MACL_REG] = 0; } - if (TARGET_SHMEDIA) - { - for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++) - if (! fixed_regs[regno] && call_really_used_regs[regno]) - SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); - } - else - for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) - if (! fixed_regs[regno] && call_really_used_regs[regno]) - SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); + for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) + if (! fixed_regs[regno] && call_really_used_regs[regno]) + SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); call_really_used_regs[FPSCR_MODES_REG] = 0; call_really_used_regs[FPSCR_STAT_REG] = 0; @@ -13643,13 +11675,6 @@ sh_legitimate_constant_p (machine_mode mode, rtx x) && SYMBOLIC_CONST_P (XEXP (XEXP (x, 0), 0))))) return false; - if (TARGET_SHMEDIA - && ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT) - || x == CONST0_RTX (mode) - || !TARGET_SHMEDIA_FPU - || TARGET_SHMEDIA64)) - return false; - return GET_CODE (x) != CONST_DOUBLE || mode == DFmode || mode == SFmode || mode == DImode || GET_MODE (x) == VOIDmode; @@ -13671,12 +11696,6 @@ sh_can_use_simple_return_p (void) HARD_REG_SET live_regs_mask; int d; - /* Some targets require special return insns. */ - if (TARGET_SHMEDIA - || (TARGET_SHCOMPACT - && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))) - return false; - if (! reload_completed || frame_pointer_needed) return false; diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 7187c23dd0f..03035274f44 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -74,28 +74,10 @@ extern int code_for_indirect_jump_scratch; FPU is disabled (which makes it compatible with SH4al-dsp). */ #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY) -/* Nonzero if we should generate code using the SHcompact instruction - set and 32-bit ABI. */ -#define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1) - -/* Nonzero if we should generate code using the SHmedia instruction - set and ABI. */ -#define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1) - -/* Nonzero if we should generate code using the SHmedia ISA and 32-bit - ABI. */ -#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E) - -/* Nonzero if we should generate code using the SHmedia ISA and 64-bit - ABI. */ -#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E) - -/* Nonzero if we should generate code using SHmedia FPU instructions. */ -#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE) /* This is not used by the SH2E calling convention */ #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ - (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \ + (TARGET_SH1 && ! TARGET_SH2E \ && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) #ifndef TARGET_CPU_DEFAULT @@ -108,19 +90,6 @@ extern int code_for_indirect_jump_scratch; #define SUPPORT_SH2A_SINGLE 1 #endif -#define TARGET_DIVIDE_INV \ - (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \ - || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \ - || sh_div_strategy == SH_DIV_INV_CALL \ - || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP) -#define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP) -#define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP) -#define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2) -#define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT) -#define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U) -#define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L) -#define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL) -#define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2) #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP) #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE) @@ -151,12 +120,6 @@ extern int code_for_indirect_jump_scratch; #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) -#define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4) -#define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5) -#define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E) -#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E) -#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E) -#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3) #if SUPPORT_SH1 #define SUPPORT_SH2 1 @@ -192,25 +155,10 @@ extern int code_for_indirect_jump_scratch; #define SUPPORT_SH4A_SINGLE 1 #endif -#if SUPPORT_SH5_COMPAT -#define SUPPORT_SH5_32MEDIA 1 -#endif - -#if SUPPORT_SH5_COMPACT_NOFPU -#define SUPPORT_SH5_32MEDIA_NOFPU 1 -#endif - -#define SUPPORT_ANY_SH5_32MEDIA \ - (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU) -#define SUPPORT_ANY_SH5_64MEDIA \ - (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU) -#define SUPPORT_ANY_SH5 \ - (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA) - /* Reset all target-selection flags. */ #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ - | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ | MASK_FPU_SINGLE_ONLY) /* This defaults us to big-endian. */ @@ -286,10 +234,7 @@ extern int code_for_indirect_jump_scratch; %{m2a-single:--isa=sh2a} \ %{m2a-single-only:--isa=sh2a} \ %{m2a-nofpu:--isa=sh2a-nofpu} \ -%{m5-compact*:--isa=SHcompact} \ -%{m5-32media*:--isa=SHmedia --abi=32} \ -%{m5-64media*:--isa=SHmedia --abi=64} \ -%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}" +%{m4al:-dsp}" #define ASM_SPEC SH_ASM_SPEC @@ -307,7 +252,7 @@ extern int code_for_indirect_jump_scratch; #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E) #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}" #else -/* If there were an -isa option for sh5-nofpu then it would also go here. */ + #define SUBTARGET_ASM_ISA_SPEC \ "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC #endif @@ -325,24 +270,8 @@ extern int code_for_indirect_jump_scratch; #define LINK_EMUL_PREFIX "sh%{ml:l}" #endif -#if TARGET_CPU_DEFAULT & MASK_SH5 -#if TARGET_CPU_DEFAULT & MASK_SH_E -#define LINK_DEFAULT_CPU_EMUL "32" -#if TARGET_CPU_DEFAULT & MASK_SH1 -#define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact" -#else -#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32" -#endif /* MASK_SH1 */ -#else /* !MASK_SH_E */ -#define LINK_DEFAULT_CPU_EMUL "64" -#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64" -#endif /* MASK_SH_E */ -#define ASM_ISA_DEFAULT_SPEC \ -" %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}" -#else /* !MASK_SH5 */ #define LINK_DEFAULT_CPU_EMUL "" #define ASM_ISA_DEFAULT_SPEC "" -#endif /* MASK_SH5 */ #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}" #define SUBTARGET_LINK_SPEC "" @@ -352,9 +281,7 @@ extern int code_for_indirect_jump_scratch; #define SH_LINK_SPEC "\ -m %(link_emul_prefix)\ -%{m5-compact*|m5-32media*:32}\ -%{m5-64media*:64}\ -%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\ +%{!m1:%{!m2:%{!m3*:%{!m4*:%(link_default_cpu_emul)}}}}\ %(subtarget_link_emul_suffix) \ %{mrelax:-relax} %(subtarget_link_spec)" @@ -419,7 +346,7 @@ enum sh_divide_strategy_e { extern enum sh_divide_strategy_e sh_div_strategy; #ifndef SH_DIV_STRATEGY_DEFAULT -#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL +#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1 #endif #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 @@ -450,7 +377,7 @@ extern enum sh_divide_strategy_e sh_div_strategy; #define INT_TYPE_SIZE 32 /* Width in bits of a `long'. */ -#define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32) +#define LONG_TYPE_SIZE (32) /* Width in bits of a `long long'. */ #define LONG_LONG_TYPE_SIZE 64 @@ -459,7 +386,7 @@ extern enum sh_divide_strategy_e sh_div_strategy; #define LONG_DOUBLE_TYPE_SIZE 64 /* Width of a word, in units (bytes). */ -#define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4) +#define UNITS_PER_WORD (4) #define MIN_UNITS_PER_WORD 4 /* Scaling factor for Dwarf data offsets for CFI information. @@ -471,10 +398,10 @@ extern enum sh_divide_strategy_e sh_div_strategy; /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ -#define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32) +#define POINTER_SIZE (32) /* Allocation boundary (in *bits*) for storing arguments in argument list. */ -#define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32) +#define PARM_BOUNDARY (32) /* Boundary (in *bits*) on which stack pointer should be aligned. */ #define STACK_BOUNDARY BIGGEST_ALIGNMENT @@ -482,17 +409,16 @@ extern enum sh_divide_strategy_e sh_div_strategy; /* The log (base 2) of the cache line size, in bytes. Processors prior to SH2 have no actual cache, but they fetch code in chunks of 4 bytes. The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ -#define CACHE_LOG ((TARGET_HARD_SH4 || TARGET_SH5) ? 5 : TARGET_SH2 ? 4 : 2) +#define CACHE_LOG (TARGET_HARD_SH4 ? 5 : TARGET_SH2 ? 4 : 2) /* ABI given & required minimum allocation boundary (in *bits*) for the code of a function. */ -#define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA) +#define FUNCTION_BOUNDARY (16) /* On SH5, the lowest bit is used to indicate SHmedia functions, so the vbit must go into the delta field of pointers-to-member-functions. */ -#define TARGET_PTRMEMFUNC_VBIT_LOCATION \ - (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn) +#define TARGET_PTRMEMFUNC_VBIT_LOCATION (ptrmemfunc_vbit_in_pfn) /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 @@ -501,7 +427,7 @@ extern enum sh_divide_strategy_e sh_div_strategy; #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) /* The best alignment to use in cases where we have a choice. */ -#define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32) +#define FASTEST_ALIGNMENT (32) /* Make strings word-aligned so strcpy from constants will be faster. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ @@ -555,11 +481,11 @@ extern enum sh_divide_strategy_e sh_div_strategy; #define ADDR_VEC_ALIGN(ADDR_VEC) 2 /* The base two logarithm of the known minimum alignment of an insn length. */ -#define INSN_LENGTH_ALIGNMENT(A_INSN) \ - (NONJUMP_INSN_P (A_INSN) \ - ? 1 << TARGET_SHMEDIA \ - : JUMP_P (A_INSN) || CALL_P (A_INSN) \ - ? 1 << TARGET_SHMEDIA \ +#define INSN_LENGTH_ALIGNMENT(A_INSN) \ + (NONJUMP_INSN_P (A_INSN) \ + ? 1 \ + : JUMP_P (A_INSN) || CALL_P (A_INSN) \ + ? 1 \ : CACHE_LOG) /* Standard register usage. */ @@ -680,14 +606,13 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ /* There are many other relevant definitions in sh.md's md_constants. */ #define FIRST_GENERAL_REG R0_REG -#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15)) +#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (15)) #define FIRST_FP_REG DR0_REG -#define LAST_FP_REG (FIRST_FP_REG + \ - (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1)) +#define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)) #define FIRST_XD_REG XD0_REG #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) #define FIRST_TARGET_REG TR0_REG -#define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1)) +#define LAST_TARGET_REG (FIRST_TARGET_REG + (-1)) /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ #define FIRST_BANKED_REG R0_REG @@ -727,14 +652,9 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ #define TARGET_REGISTER_P(REGNO) \ ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG) -#define SHMEDIA_REGISTER_P(REGNO) \ - (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ - || TARGET_REGISTER_P (REGNO)) - -/* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark - registers that should be fixed. */ #define VALID_REGISTER_P(REGNO) \ - (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \ + (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ + || XD_REGISTER_P (REGNO) \ || (REGNO) == AP_REG || (REGNO) == RAP_REG \ || (REGNO) == FRAME_POINTER_REGNUM \ || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ @@ -743,11 +663,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ /* The mode that should be generally used to store a register by itself in the stack, or to load it back. */ #define REGISTER_NATURAL_MODE(REGNO) \ - (FP_REGISTER_P (REGNO) ? SFmode \ - : XD_REGISTER_P (REGNO) ? DFmode \ - : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \ - ? DImode \ - : SImode) + (FP_REGISTER_P (REGNO) ? SFmode : XD_REGISTER_P (REGNO) ? DFmode : SImode) + #define FIRST_PSEUDO_REGISTER 156 @@ -868,18 +785,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ 1, 1, 0, 0, \ } -/* Only the lower 32-bits of R10-R14 are guaranteed to be preserved - across SHcompact function calls. We can't tell whether a called - function is SHmedia or SHcompact, so we assume it may be when - compiling SHmedia code with the 32-bit ABI, since that's the only - ABI that can be linked with SHcompact code. */ -#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \ - (TARGET_SHMEDIA32 \ - && GET_MODE_SIZE (MODE) > 4 \ - && (((REGNO) >= FIRST_GENERAL_REG + 10 \ - && (REGNO) <= FIRST_GENERAL_REG + 15) \ - || TARGET_REGISTER_P (REGNO) \ - || (REGNO) == PR_MEDIA_REG)) +#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) (false) /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. @@ -890,8 +796,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ #define HARD_REGNO_NREGS(REGNO, MODE) \ (XD_REGISTER_P (REGNO) \ ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \ - : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \ - ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ @@ -907,13 +811,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ floating-point mode. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ ((MODE1) == (MODE2) \ - || (TARGET_SHMEDIA \ - && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \ - && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \ || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ - && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \ - && (GET_MODE_SIZE (MODE2) <= 4)) \ - : ((MODE1) != SFmode && (MODE2) != SFmode)))) + && (((MODE1) != SFmode && (MODE2) != SFmode)))) /* Specify the modes required to caller save a given hard regno. */ #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ @@ -993,19 +892,13 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ #define ARG_POINTER_REGNUM AP_REG /* Register in which the static-chain is passed to a function. */ -#define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3) +#define STATIC_CHAIN_REGNUM (3) /* Don't default to pcc-struct-return, because we have already specified exactly how to return structures in the TARGET_RETURN_IN_MEMORY target hook. */ #define DEFAULT_PCC_STRUCT_RETURN 0 -#define SHMEDIA_REGS_STACK_ADJUST() \ - (TARGET_SHCOMPACT && crtl->saves_all_registers \ - ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \ - + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \ - : 0) - /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. @@ -1177,20 +1070,13 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 145,146,147,148,149,152,153,154,155 } /* The class value for index registers, and the one for base regs. */ -#define INDEX_REG_CLASS \ - (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS) -#define BASE_REG_CLASS GENERAL_REGS +#define INDEX_REG_CLASS R0_REGS +#define BASE_REG_CLASS GENERAL_REGS /* Defines for sh.md and constraints.md. */ #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ && ((HOST_WIDE_INT)(VALUE)) <= 127) -#define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \ - && ((HOST_WIDE_INT)(VALUE)) <= 32767) - -#define CONST_OK_FOR_J16(VALUE) \ - ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \ - || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 32))) #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ && ((HOST_WIDE_INT)(VALUE)) <= 255) @@ -1204,10 +1090,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; If TARGET_SHMEDIA, we need two FP registers per word. Otherwise we will need at most one register per word. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ - (TARGET_SHMEDIA \ - && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \ - ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \ - : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* If defined, gives a class of registers that cannot be used as the operand of a SUBREG that changes the mode of the object illegally. @@ -1222,17 +1105,17 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; These macros are used only in other macro definitions below. */ #define NPARM_REGS(MODE) \ (TARGET_FPU_ANY && (MODE) == SFmode \ - ? (TARGET_SH5 ? 12 : 8) \ + ? 8 \ : (TARGET_SH4 || TARGET_SH2A_DOUBLE) \ && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ - ? (TARGET_SH5 ? 12 : 8) \ - : (TARGET_SH5 ? 8 : 4)) + ? 8 \ + : 4) -#define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4)) -#define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0)) +#define FIRST_PARM_REG (FIRST_GENERAL_REG + 4) +#define FIRST_RET_REG (FIRST_GENERAL_REG + 0) -#define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4)) +#define FIRST_FP_PARM_REG (FIRST_FP_REG + 4) #define FIRST_FP_RET_REG FIRST_FP_REG /* Define this if pushing a word on the stack @@ -1261,10 +1144,8 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; /* Value is the number of bytes of arguments automatically popped when calling a subroutine. - CUM is the accumulated argument list. - - On SHcompact, the call trampoline pops arguments off the stack. */ -#define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0) + CUM is the accumulated argument list. */ +#define CALL_POPS_ARGS(CUM) (0) /* Some subroutine macros specific to this machine. */ @@ -1337,93 +1218,19 @@ struct sh_args { by reference. */ int byref; - /* call_cookie is a bitmask used by call expanders, as well as - function prologue and epilogues, to allow SHcompact to comply - with the SH5 32-bit ABI, that requires 64-bit registers to be - used even though only the lower 32-bit half is visible in - SHcompact mode. The strategy is to call SHmedia trampolines. - - The alternatives for each of the argument-passing registers are - (a) leave it unchanged; (b) pop it off the stack; (c) load its - contents from the address in it; (d) add 8 to it, storing the - result in the next register, then (c); (e) copy it from some - floating-point register, - - Regarding copies from floating-point registers, r2 may only be - copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe - copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2, - dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8. - r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or - dr10. - - The bit mask is structured as follows: - - - 1 bit to tell whether to set up a return trampoline. - - - 3 bits to count the number consecutive registers to pop off the - stack. - - - 4 bits for each of r9, r8, r7 and r6. - - - 3 bits for each of r5, r4, r3 and r2. - - - 3 bits set to 0 (the most significant ones) - - 3 2 1 0 - 1098 7654 3210 9876 5432 1098 7654 3210 - FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST - 2223 3344 4555 6666 7777 8888 9999 SSS- - - - If F is set, the register must be copied from an FP register, - whose number is encoded in the remaining bits. - - - Else, if L is set, the register must be loaded from the address - contained in it. If the P bit is *not* set, the address of the - following dword should be computed first, and stored in the - following register. - - - Else, if P is set, the register alone should be popped off the - stack. - - - After all this processing, the number of registers represented - in SSS will be popped off the stack. This is an optimization - for pushing/popping consecutive registers, typically used for - varargs and large arguments partially passed in registers. - - - If T is set, a return trampoline will be set up for 64-bit - return values to be split into 2 32-bit registers. */ - long call_cookie; - /* This is set to nonzero when the call in question must use the Renesas ABI, even without the -mrenesas option. */ int renesas_abi; }; -#define CALL_COOKIE_RET_TRAMP_SHIFT 0 -#define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT) -#define CALL_COOKIE_STACKSEQ_SHIFT 1 -#define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT) -#define CALL_COOKIE_STACKSEQ_GET(COOKIE) \ - (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7) -#define CALL_COOKIE_INT_REG_SHIFT(REG) \ - (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3) -#define CALL_COOKIE_INT_REG(REG, VAL) \ - ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG)) -#define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \ - (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15)) - #define CUMULATIVE_ARGS struct sh_args #define GET_SH_ARG_CLASS(MODE) \ ((TARGET_FPU_ANY && (MODE) == SFmode) \ ? SH_ARG_FLOAT \ - /* There's no mention of complex float types in the SH5 ABI, so we - should presumably handle them as aggregate types. */ \ - : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ - ? SH_ARG_INT \ : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ - ? SH_ARG_FLOAT : SH_ARG_INT) + ? SH_ARG_FLOAT : SH_ARG_INT) /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. @@ -1458,78 +1265,11 @@ struct sh_args { foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ #define FUNCTION_ARG_SCmode_WART 1 -/* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit - register in SHcompact mode, it must be padded in the most - significant end. This means that passing it by reference wouldn't - pad properly on a big-endian machine. In this particular case, we - pass this argument on the stack, in a way that the call trampoline - will load its value into the appropriate register. */ -#define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \ - ((MODE) == BLKmode \ - && TARGET_SHCOMPACT \ - && TARGET_BIG_ENDIAN \ - && int_size_in_bytes (TYPE) > 4 \ - && int_size_in_bytes (TYPE) < 8) - /* Minimum alignment for an argument to be passed by callee-copy reference. We need such arguments to be aligned to 8 byte boundaries, because they'll be loaded using quad loads. */ #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) -/* The SH5 ABI requires floating-point arguments to be passed to - functions without a prototype in both an FP register and a regular - register or the stack. When passing the argument in both FP and - general-purpose registers, list the FP register first. */ -#define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \ - (gen_rtx_PARALLEL \ - ((MODE), \ - gen_rtvec (2, \ - gen_rtx_EXPR_LIST \ - (VOIDmode, \ - ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ - ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ - + (CUM).arg_count[(int) SH_ARG_FLOAT]) \ - : NULL_RTX), \ - const0_rtx), \ - gen_rtx_EXPR_LIST \ - (VOIDmode, \ - ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ - ? gen_rtx_REG ((MODE), FIRST_PARM_REG \ - + (CUM).arg_count[(int) SH_ARG_INT]) \ - : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \ - + (CUM).arg_count[(int) SH_ARG_FLOAT])), \ - const0_rtx)))) - -/* The SH5 ABI requires regular registers or stack slots to be - reserved for floating-point arguments. Registers are taken care of - in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here. - Unfortunately, there's no way to just reserve a stack slot, so - we'll end up needlessly storing a copy of the argument in the - stack. For incoming arguments, however, the PARALLEL will be - optimized to the register-only form, and the value in the stack - slot won't be used at all. */ -#define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \ - ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \ - ? gen_rtx_REG ((MODE), (REG)) \ - : gen_rtx_PARALLEL ((MODE), \ - gen_rtvec (2, \ - gen_rtx_EXPR_LIST \ - (VOIDmode, NULL_RTX, \ - const0_rtx), \ - gen_rtx_EXPR_LIST \ - (VOIDmode, gen_rtx_REG ((MODE), \ - (REG)), \ - const0_rtx)))) - -#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ - (TARGET_SH5 \ - && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \ - || (MODE) == DCmode) \ - && ((CUM).arg_count[(int) SH_ARG_INT] \ - + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \ - : GET_MODE_SIZE (MODE)) \ - + 7) / 8) > NPARM_REGS (SImode)) - /* Perform any needed actions needed for a function that is receiving a variable number of arguments. */ @@ -1539,19 +1279,10 @@ struct sh_args { from the trapa instruction. */ #define FUNCTION_PROFILER(STREAM,LABELNO) \ { \ - if (TARGET_SHMEDIA) \ - { \ - fprintf((STREAM), "\tmovi\t33,r0\n"); \ - fprintf((STREAM), "\ttrapa\tr0\n"); \ - asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ - } \ - else \ - { \ - fprintf((STREAM), "\t.align\t2\n"); \ - fprintf((STREAM), "\ttrapa\t#33\n"); \ - fprintf((STREAM), "\t.align\t2\n"); \ - asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ - } \ + fprintf((STREAM), "\t.align\t2\n"); \ + fprintf((STREAM), "\ttrapa\t#33\n"); \ + fprintf((STREAM), "\t.align\t2\n"); \ + asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ } /* Define this macro if the code for function profiling should come @@ -1575,14 +1306,13 @@ struct sh_args { 6 000c 00000000 l2: .long function */ /* Length in units of the trampoline for entering a nested function. */ -#define TRAMPOLINE_SIZE \ - (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : TARGET_FDPIC ? 32 : 16) +#define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : 16) /* Alignment required for a trampoline in bits. */ #define TRAMPOLINE_ALIGNMENT \ ((CACHE_LOG < 3 \ - || (optimize_size && ! (TARGET_HARD_SH4 || TARGET_SH5))) ? 32 \ - : TARGET_SHMEDIA ? 256 : 64) + || (optimize_size && ! (TARGET_HARD_SH4))) ? 32 \ + : 64) /* A C expression whose value is RTL representing the value of the return address for the frame COUNT steps up from the current frame. @@ -1596,8 +1326,7 @@ struct sh_args { prologue. This RTL is either a REG, indicating that the return value is saved in REG, or a MEM representing a location in the stack. */ -#define INCOMING_RETURN_ADDR_RTX \ - gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) +#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PR_REG) /* Addressing modes, and classification of registers for them. */ #define HAVE_POST_INCREMENT TARGET_SH1 @@ -1627,10 +1356,7 @@ struct sh_args { (GENERAL_OR_AP_REGISTER_P (REGNO) \ || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) #define REGNO_OK_FOR_INDEX_P(REGNO) \ - (TARGET_SHMEDIA \ - ? (GENERAL_REGISTER_P (REGNO) \ - || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \ - : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) + ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) /* True if SYMBOL + OFFSET constants must refer to something within SYMBOL's section. */ @@ -1655,14 +1381,12 @@ struct sh_args { /* Nonzero if X is a reg that can be used as an index. */ #define REG_OK_FOR_INDEX_P(X, STRICT) \ - ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ - : REGNO (X) == R0_REG) \ + ((REGNO (X) == R0_REG) \ || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) /* Nonzero if X/OFFSET is a reg that can be used as an index. */ #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \ - ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \ - : REGNO (X) == R0_REG && OFFSET == 0) \ + ((REGNO (X) == R0_REG && OFFSET == 0) \ || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) /* Macros for extra constraints. */ @@ -1683,13 +1407,6 @@ struct sh_args { && !PIC_ADDR_P (OP) \ && GET_CODE (OP) != LABEL_REF))) -/* Check whether OP is a datalabel unspec. */ -#define DATALABEL_REF_NO_CONST_P(OP) \ - (GET_CODE (OP) == UNSPEC \ - && XINT ((OP), 1) == UNSPEC_DATALABEL \ - && XVECLEN ((OP), 0) == 1 \ - && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF) - #define GOT_ENTRY_P(OP) \ (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) @@ -1721,24 +1438,16 @@ struct sh_args { (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ || (GET_CODE (OP) == CONST \ && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \ - || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \ - || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \ + || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \ || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ - || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ - || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \ + || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \ && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) #define PIC_REFERENCE_P(OP) \ (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ || GOTOFF_P (OP) || PIC_ADDR_P (OP)) -#define MOVI_SHORI_BASE_OPERAND_P(OP) \ - (flag_pic \ - ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \ - || PCREL_SYMOFF_P (OP)) \ - : NON_PIC_REFERENCE_P (OP)) - #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \ ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \ || (GET_CODE (X) == SUBREG \ @@ -1766,8 +1475,6 @@ struct sh_args { #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false) #endif -#define ALLOW_INDEXED_ADDRESS \ - ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS) /* A C compound statement that attempts to replace X, which is an address that needs reloading, with a valid memory address for an operand of @@ -1808,10 +1515,10 @@ struct sh_args { #define DEFAULT_SIGNED_CHAR 1 /* The type of size_t unsigned int. */ -#define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int") +#define SIZE_TYPE ("unsigned int") #undef PTRDIFF_TYPE -#define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int") +#define PTRDIFF_TYPE ("int") #define WCHAR_TYPE "short unsigned int" #define WCHAR_TYPE_SIZE 16 @@ -1820,7 +1527,7 @@ struct sh_args { /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ -#define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4) +#define MOVE_MAX (4) /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever MOVE_MAX is not a compile-time constant. */ @@ -1828,7 +1535,7 @@ struct sh_args { /* Max number of bytes we want move_by_pieces to be able to copy efficiently. */ -#define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4) +#define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4) /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ @@ -1841,9 +1548,7 @@ struct sh_args { For SHmedia, we can truncate to QImode easier using zero extension. FP registers can load SImode values, but don't implicitly sign-extend them to DImode. */ -#define LOAD_EXTEND_OP(MODE) \ - (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \ - : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN) +#define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN) /* Define if loading short immediate values into registers sign extends. */ #define SHORT_IMMEDIATES_SIGN_EXTEND 1 @@ -1878,9 +1583,7 @@ struct sh_args { #define SHIFT_COUNT_TRUNCATED (0) /* All integers have the same format so truncation is easy. */ -/* But SHmedia must sign-extend DImode when truncating to SImode. */ -#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \ - (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64) +#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) (true) /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. @@ -1889,7 +1592,7 @@ struct sh_args { /*#define NO_FUNCTION_CSE 1*/ /* The machine modes of pointers and functions. */ -#define Pmode (TARGET_SHMEDIA64 ? DImode : SImode) +#define Pmode (SImode) #define FUNCTION_MODE Pmode /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 @@ -1929,8 +1632,7 @@ struct sh_args { ((! nonpic_symbol_mentioned_p (X) \ && (GET_CODE (X) != SYMBOL_REF \ || ! CONSTANT_POOL_ADDRESS_P (X) \ - || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \ - || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF)) + || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))) #define SYMBOLIC_CONST_P(X) \ ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ @@ -1944,7 +1646,7 @@ struct sh_args { register information here is not used for SFmode. */ #define REGCLASS_HAS_GENERAL_REG(CLASS) \ ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \ - || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) + || ((CLASS) == SIBCALL_REGS)) #define REGCLASS_HAS_FP_REG(CLASS) \ ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ @@ -1971,19 +1673,13 @@ struct sh_args { #define SET_ASM_OP "\t.set\t" /* How to change between sections. */ -#define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 \ - ? "\t.section\t.text..SHmedia32,\"ax\"" \ - : "\t.text") +#define TEXT_SECTION_ASM_OP "\t.text" #define DATA_SECTION_ASM_OP "\t.data" #if defined CRT_BEGIN || defined CRT_END /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ -# undef TEXT_SECTION_ASM_OP -# if __SHMEDIA__ == 1 && __SH5__ == 32 -# define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\"" -# else -# define TEXT_SECTION_ASM_OP "\t.text" -# endif +#undef TEXT_SECTION_ASM_OP +#define TEXT_SECTION_ASM_OP "\t.text" #endif #ifndef BSS_SECTION_ASM_OP @@ -2027,24 +1723,12 @@ struct sh_args { #define ASM_OUTPUT_REG_PUSH(file, v) \ { \ - if (TARGET_SHMEDIA) \ - { \ - fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \ - fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \ - } \ - else \ - fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ + fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ } #define ASM_OUTPUT_REG_POP(file, v) \ { \ - if (TARGET_SHMEDIA) \ - { \ - fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \ - fprintf ((file), "\taddi.l\tr15,8,r15\n"); \ - } \ - else \ - fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ + fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ } /* DBX register number for a given compiler register number. */ @@ -2064,34 +1748,32 @@ struct sh_args { #define SH_DBX_REGISTER_NUMBER(REGNO) \ (IN_RANGE ((REGNO), \ (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ - FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \ + FIRST_GENERAL_REG + 15U) \ ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ : ((int) (REGNO) >= FIRST_FP_REG \ && ((int) (REGNO) \ - <= (FIRST_FP_REG + \ - ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \ - ? ((unsigned) (REGNO) - FIRST_FP_REG \ - + (TARGET_SH5 ? 77 : 25)) \ + <= (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)))) \ + ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \ : XD_REGISTER_P (REGNO) \ - ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \ + ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \ : TARGET_REGISTER_P (REGNO) \ ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \ : (REGNO) == PR_REG \ - ? (TARGET_SH5 ? 18 : 17) \ + ? (17) \ : (REGNO) == PR_MEDIA_REG \ - ? (TARGET_SH5 ? 18 : (unsigned) -1) \ + ? ((unsigned) -1) \ : (REGNO) == GBR_REG \ - ? (TARGET_SH5 ? 238 : 18) \ + ? (18) \ : (REGNO) == MACH_REG \ - ? (TARGET_SH5 ? 239 : 20) \ + ? (20) \ : (REGNO) == MACL_REG \ - ? (TARGET_SH5 ? 240 : 21) \ + ? (21) \ : (REGNO) == T_REG \ - ? (TARGET_SH5 ? 242 : 22) \ + ? (22) \ : (REGNO) == FPUL_REG \ - ? (TARGET_SH5 ? 244 : 23) \ + ? (23) \ : (REGNO) == FPSCR_REG \ - ? (TARGET_SH5 ? 243 : 24) \ + ? (24) \ : (unsigned) -1) /* This is how to output a reference to a symbol_ref. On SH5, @@ -2099,8 +1781,6 @@ struct sh_args { #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ do \ { \ - if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \ - fputs ("datalabel ", (FILE)); \ assemble_name ((FILE), XSTR ((SYM), 0)); \ } \ while (0) @@ -2123,30 +1803,12 @@ struct sh_args { switch (GET_MODE (BODY)) \ { \ case SImode: \ - if (TARGET_SH5) \ - { \ - asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \ - (VALUE), (REL)); \ - break; \ - } \ asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ break; \ case HImode: \ - if (TARGET_SH5) \ - { \ - asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \ - (VALUE), (REL)); \ - break; \ - } \ asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ break; \ case QImode: \ - if (TARGET_SH5) \ - { \ - asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \ - (VALUE), (REL)); \ - break; \ - } \ asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ break; \ default: \ @@ -2188,8 +1850,7 @@ enum processor_type { PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4, - PROCESSOR_SH4A, - PROCESSOR_SH5 + PROCESSOR_SH4A }; #define sh_cpu_attr ((enum attr_cpu)sh_cpu) @@ -2240,10 +1901,9 @@ extern int current_function_interrupt; if (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \ - (MODE) = (TARGET_SH1 ? SImode \ - : TARGET_SHMEDIA32 ? SImode : DImode); + (MODE) = (TARGET_SH1 ? SImode : DImode); -#define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64) +#define MAX_FIXED_MODE_SIZE (64) /* Better to allocate once the maximum space for outgoing args in the prologue rather than duplicate around each call. */ @@ -2264,11 +1924,9 @@ extern int current_function_interrupt; #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \ && (REGNO) == FPSCR_REG) -#define DWARF_FRAME_RETURN_COLUMN \ - (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG)) +#define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (PR_REG)) -#define EH_RETURN_DATA_REGNO(N) \ - ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM) +#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 4U : INVALID_REGNUM) #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) @@ -2280,7 +1938,7 @@ extern int current_function_interrupt; ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \ : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \ - | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4))) + | ((CODE) ? 0 : DW_EH_PE_sdata4)) /* Handle special EH pointer encodings. Absolute, pc-relative, and indirect are handled automatically. */ @@ -2306,7 +1964,7 @@ extern int current_function_interrupt; } \ } while (0) -#if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ +#if (defined CRT_BEGIN || defined CRT_END) /* SH constant pool breaks the devices in crtstuff.c to control section in where code resides. We have to write it as asm code. */ #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ @@ -2318,6 +1976,6 @@ extern int current_function_interrupt; 0: .p2align 2\n\ 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ 2:\n" TEXT_SECTION_ASM_OP); -#endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */ +#endif /* (defined CRT_BEGIN || defined CRT_END) */ #endif /* ! GCC_SH_H */ diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 0bb0f2b3038..0e70ea2d9f2 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -123,10 +123,8 @@ (define_c_enum "unspec" [ ;; These are used with unspec. - UNSPEC_COMPACT_ARGS UNSPEC_MOVA UNSPEC_CASESI - UNSPEC_DATALABEL UNSPEC_BBR UNSPEC_SFUNC UNSPEC_PIC @@ -137,11 +135,9 @@ UNSPEC_GOTPLT UNSPEC_PCREL UNSPEC_ICACHE - UNSPEC_INIT_TRAMP UNSPEC_FCOSA UNSPEC_FSRRA UNSPEC_FSINA - UNSPEC_NSB UNSPEC_ALLOCO UNSPEC_TLSGD UNSPEC_TLSLDM @@ -150,22 +146,11 @@ UNSPEC_GOTTPOFF UNSPEC_TPOFF UNSPEC_RA - UNSPEC_DIV_INV_M0 - UNSPEC_DIV_INV_M1 - UNSPEC_DIV_INV_M2 - UNSPEC_DIV_INV_M3 - UNSPEC_DIV_INV20 - UNSPEC_DIV_INV_TABLE - UNSPEC_ASHIFTRT UNSPEC_THUNK UNSPEC_CHKADD UNSPEC_SP_SET UNSPEC_SP_TEST UNSPEC_MOVUA - ;; (unspec [VAL SHIFT] UNSPEC_EXTRACT_S16) computes (short) (VAL >> SHIFT). - ;; UNSPEC_EXTRACT_U16 is the unsigned equivalent. - UNSPEC_EXTRACT_S16 - UNSPEC_EXTRACT_U16 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR. UNSPEC_SYMOFF ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .). @@ -202,7 +187,7 @@ ;; Target CPU. (define_attr "cpu" - "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a,sh5" + "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a" (const (symbol_ref "sh_cpu_attr"))) (define_attr "endian" "big,little" @@ -218,10 +203,9 @@ (const (if_then_else (symbol_ref "TARGET_FMOVD") (const_string "yes") (const_string "no")))) ;; pipeline model -(define_attr "pipe_model" "sh1,sh4,sh5media" +(define_attr "pipe_model" "sh1,sh4" (const - (cond [(symbol_ref "TARGET_SHMEDIA") (const_string "sh5media") - (symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")] + (cond [(symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")] (const_string "sh1")))) ;; cbranch conditional branch instructions @@ -269,33 +253,6 @@ ;; fsrra square root reciprocal approximate ;; fsca sine and cosine approximate ;; tls_load load TLS related address -;; arith_media SHmedia arithmetic, logical, and shift instructions -;; cbranch_media SHmedia conditional branch instructions -;; cmp_media SHmedia compare instructions -;; dfdiv_media SHmedia double precision divide and square root -;; dfmul_media SHmedia double precision multiply instruction -;; dfparith_media SHmedia double precision floating point arithmetic -;; dfpconv_media SHmedia double precision floating point conversions -;; dmpy_media SHmedia longword multiply -;; fcmp_media SHmedia floating point compare instructions -;; fdiv_media SHmedia single precision divide and square root -;; fload_media SHmedia floating point register load instructions -;; fmove_media SHmedia floating point register moves (inc. fabs and fneg) -;; fparith_media SHmedia single precision floating point arithmetic -;; fpconv_media SHmedia single precision floating point conversions -;; fstore_media SHmedia floating point register store instructions -;; gettr_media SHmedia gettr instruction -;; invalidate_line_media SHmedia invalidate_line sequence -;; jump_media SHmedia unconditional branch instructions -;; load_media SHmedia general register load instructions -;; pt_media SHmedia pt instruction (expanded by assembler) -;; ptabs_media SHmedia ptabs instruction -;; store_media SHmedia general register store instructions -;; mcmp_media SHmedia multimedia compare, absolute, saturating ops -;; mac_media SHmedia mac-style fixed point operations -;; d2mpy_media SHmedia: two 32-bit integer multiplies -;; atrans_media SHmedia approximate transcendental functions -;; ustore_media SHmedia unaligned stores ;; nil no-op move, will be deleted. (define_attr "type" @@ -304,11 +261,7 @@ prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s, dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp, gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load, - arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media, - dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media, - fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media, - jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media, - d2mpy_media,atrans_media,ustore_media,nil,other" + nil,other" (const_string "other")) ;; We define a new attribute namely "insn_class".We use @@ -480,20 +433,11 @@ (match_test "flag_pic") (const_int 22) ] (const_int 14)) - (eq_attr "type" "pt_media") - (if_then_else (match_test "TARGET_SHMEDIA64") - (const_int 20) (const_int 12)) - (and (eq_attr "type" "jump_media") - (match_test "TARGET_SH5_CUT2_WORKAROUND")) - (const_int 8) - ] (if_then_else (match_test "TARGET_SHMEDIA") - (const_int 4) - (const_int 2)))) + ] (const_int 2))) ;; DFA descriptions for the pipelines (include "sh1.md") -(include "shmedia.md") (include "sh4.md") (include "iterators.md") @@ -533,9 +477,6 @@ (define_attr "is_sfunc" "" (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0))) -(define_attr "is_mac_media" "" - (if_then_else (eq_attr "type" "mac_media") (const_int 1) (const_int 0))) - (define_attr "branch_zero" "yes,no" (cond [(eq_attr "type" "!cbranch") (const_string "no") (ne (symbol_ref "(next_active_insn (insn)\ @@ -1176,12 +1117,7 @@ (clobber (reg:SI T_REG))] "" { - if (TARGET_SHMEDIA) - emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1], - operands[2], operands[3])); - else - expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1); - + expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1); DONE; }) @@ -1325,17 +1261,11 @@ (pc))) (clobber (match_dup 4)) (clobber (reg:SI T_REG))] - "TARGET_CBRANCHDI4 || TARGET_SH2 || TARGET_SHMEDIA" + "TARGET_CBRANCHDI4 || TARGET_SH2" { enum rtx_code comparison; - if (TARGET_SHMEDIA) - { - emit_jump_insn (gen_cbranchint4_media (operands[0], operands[1], - operands[2], operands[3])); - DONE; - } - else if (!TARGET_CBRANCHDI4) + if (!TARGET_CBRANCHDI4) { sh_emit_compare_and_branch (operands, DImode); DONE; @@ -1517,224 +1447,10 @@ [(set_attr "length" "8") (set_attr "type" "arith3")]) -(define_insn "cmpeqsi_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (match_operand:SI 1 "logical_operand" "%r") - (match_operand:SI 2 "cmp_operand" "Nr")))] - "TARGET_SHMEDIA" - "cmpeq %1, %N2, %0" - [(set_attr "type" "cmp_media")]) - -(define_insn "cmpeqdi_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "cmp_operand" "Nr")))] - "TARGET_SHMEDIA" - "cmpeq %1, %N2, %0" - [(set_attr "type" "cmp_media")]) - -(define_insn "cmpgtsi_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (gt:SI (match_operand:SI 1 "cmp_operand" "Nr") - (match_operand:SI 2 "cmp_operand" "rN")))] - "TARGET_SHMEDIA" - "cmpgt %N1, %N2, %0" - [(set_attr "type" "cmp_media")]) - -(define_insn "cmpgtdi_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (gt:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr") - (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))] - "TARGET_SHMEDIA" - "cmpgt %N1, %N2, %0" - [(set_attr "type" "cmp_media")]) - -(define_insn "cmpgtusi_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (gtu:SI (match_operand:SI 1 "cmp_operand" "Nr") - (match_operand:SI 2 "cmp_operand" "rN")))] - "TARGET_SHMEDIA" - "cmpgtu %N1, %N2, %0" - [(set_attr "type" "cmp_media")]) - -(define_insn "cmpgtudi_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (gtu:SI (match_operand:DI 1 "arith_reg_or_0_operand" "Nr") - (match_operand:DI 2 "arith_reg_or_0_operand" "rN")))] - "TARGET_SHMEDIA" - "cmpgtu %N1, %N2, %0" - [(set_attr "type" "cmp_media")]) - -; This pattern is for combine. -(define_insn "*cmpne0sisi_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (ne:SI (match_operand:SI 1 "arith_reg_operand" "r") (const_int 0)))] - "TARGET_SHMEDIA" - "cmpgtu %1,r63,%0" - [(set_attr "type" "cmp_media")]) - ;; ------------------------------------------------------------------------- ;; Conditional move instructions ;; ------------------------------------------------------------------------- -;; The insn names may seem reversed, but note that cmveq performs the move -;; if op1 == 0, and cmvne does it if op1 != 0. - -(define_insn "movdicc_false" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (if_then_else:DI (eq (match_operand:DI 1 "arith_reg_operand" "r") - (const_int 0)) - (match_operand:DI 2 "arith_reg_or_0_operand" "rN") - (match_operand:DI 3 "arith_reg_operand" "0")))] - "TARGET_SHMEDIA" - "cmveq %1, %N2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "movdicc_true" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (if_then_else:DI (ne (match_operand:DI 1 "arith_reg_operand" "r") - (const_int 0)) - (match_operand:DI 2 "arith_reg_or_0_operand" "rN") - (match_operand:DI 3 "arith_reg_operand" "0")))] - "TARGET_SHMEDIA" - "cmvne %1, %N2, %0" - [(set_attr "type" "arith_media")]) - -(define_peephole2 - [(set (match_operand:DI 0 "arith_reg_dest" "") - (if_then_else:DI (match_operator 3 "equality_comparison_operator" - [(match_operand:DI 1 "arith_reg_operand" "") - (const_int 0)]) - (match_operand:DI 2 "arith_reg_dest" "") - (match_dup 0))) - (set (match_dup 2) (match_dup 0))] - "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])" - [(set (match_dup 2) - (if_then_else:DI (match_dup 3) (match_dup 0) (match_dup 2)))] -{ - operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])), - VOIDmode, operands[1], CONST0_RTX (DImode)); -}) - -(define_peephole2 - [(set (match_operand:DI 0 "general_movdst_operand" "") - (match_operand:DI 1 "arith_reg_or_0_operand" "")) - (set (match_operand:DI 2 "arith_reg_dest" "") - (if_then_else:DI (match_operator 4 "equality_comparison_operator" - [(match_operand:DI 3 "arith_reg_operand" "") - (const_int 0)]) - (match_dup 0) - (match_dup 2)))] - "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])" - [(set (match_dup 2) - (if_then_else:DI (match_dup 4) (match_dup 1) (match_dup 2)))] - "") - -(define_expand "movdicc" - [(set (match_operand:DI 0 "register_operand" "") - (if_then_else:DI (match_operand 1 "comparison_operator" "") - (match_operand:DI 2 "register_operand" "") - (match_operand:DI 3 "register_operand" "")))] - "TARGET_SHMEDIA" -{ - if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE) - && GET_MODE (XEXP (operands[1], 0)) == DImode - && XEXP (operands[1], 1) == const0_rtx) - ; - else - { - if (!can_create_pseudo_p ()) - FAIL; - - operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]), - GET_CODE (operands[1]), - XEXP (operands[1], 0), - XEXP (operands[1], 1)); - if (!operands[1]) - FAIL; - } -}) - -;; Add SImode variants for cmveq / cmvne to compensate for not promoting -;; SImode to DImode. -(define_insn "movsicc_false" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (if_then_else:SI (eq (match_operand:SI 1 "arith_reg_operand" "r") - (const_int 0)) - (match_operand:SI 2 "arith_reg_or_0_operand" "rN") - (match_operand:SI 3 "arith_reg_operand" "0")))] - "TARGET_SHMEDIA" - "cmveq %1, %N2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "movsicc_true" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (if_then_else:SI (ne (match_operand:SI 1 "arith_reg_operand" "r") - (const_int 0)) - (match_operand:SI 2 "arith_reg_or_0_operand" "rN") - (match_operand:SI 3 "arith_reg_operand" "0")))] - "TARGET_SHMEDIA" - "cmvne %1, %N2, %0" - [(set_attr "type" "arith_media")]) - -(define_peephole2 - [(set (match_operand:SI 0 "arith_reg_dest" "") - (if_then_else:SI (match_operator 3 "equality_comparison_operator" - [(match_operand:SI 1 "arith_reg_operand" "") - (const_int 0)]) - (match_operand:SI 2 "arith_reg_dest" "") - (match_dup 0))) - (set (match_dup 2) (match_dup 0))] - "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0])" - [(set (match_dup 2) - (if_then_else:SI (match_dup 3) (match_dup 0) (match_dup 2)))] -{ - operands[3] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[3])), - VOIDmode, operands[1], CONST0_RTX (SImode)); -}) - -(define_peephole2 - [(set (match_operand:SI 0 "general_movdst_operand" "") - (match_operand:SI 1 "arith_reg_or_0_operand" "")) - (set (match_operand:SI 2 "arith_reg_dest" "") - (if_then_else:SI (match_operator 4 "equality_comparison_operator" - [(match_operand:SI 3 "arith_reg_operand" "") - (const_int 0)]) - (match_dup 0) - (match_dup 2)))] - "TARGET_SHMEDIA && peep2_reg_dead_p (2, operands[0]) - && (!REG_P (operands[1]) || GENERAL_REGISTER_P (REGNO (operands[1])))" - [(set (match_dup 2) - (if_then_else:SI (match_dup 4) (match_dup 1) (match_dup 2)))] -{ - replace_rtx (operands[4], operands[0], operands[1]); -}) - -;; The register allocator is rather clumsy in handling multi-way conditional -;; moves, so allow the combiner to make them, and we split them up after -;; reload. */ -(define_insn_and_split "*movsicc_umin" - [(set (match_operand:SI 0 "arith_reg_dest" "=&r") - (umin:SI (if_then_else:SI - (eq (match_operand:SI 1 "arith_reg_operand" "r") - (const_int 0)) - (match_operand:SI 2 "arith_reg_or_0_operand" "rN") - (match_operand:SI 3 "register_operand" "0")) - (match_operand:SI 4 "arith_reg_or_0_operand" "r"))) - (clobber (match_scratch:SI 5 "=&r"))] - "TARGET_SHMEDIA && !can_create_pseudo_p ()" - "#" - "TARGET_SHMEDIA && reload_completed" - [(pc)] -{ - emit_insn (gen_movsicc_false (operands[0], operands[1], operands[2], - operands[3])); - emit_insn (gen_cmpgtusi_media (operands[5], operands[4], operands[0])); - emit_insn (gen_movsicc_false (operands[0], operands[5], operands[4], - operands[0])); - DONE; -}) - (define_insn "*movsicc_t_false" [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") (if_then_else (eq (reg:SI T_REG) (const_int 0)) @@ -1774,70 +1490,35 @@ (if_then_else:SI (match_operand 1 "comparison_operator" "") (match_operand:SI 2 "arith_reg_or_0_operand" "") (match_operand:SI 3 "arith_reg_operand" "")))] - "TARGET_SHMEDIA || TARGET_PRETEND_CMOVE" + "TARGET_PRETEND_CMOVE" { - if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE) - && GET_MODE (XEXP (operands[1], 0)) == SImode - && (TARGET_SHMEDIA - || (REG_P (XEXP (operands[1], 0)) - && REGNO (XEXP (operands[1], 0)) == T_REG)) - && XEXP (operands[1], 1) == const0_rtx) - ; + rtx_code code = GET_CODE (operands[1]); + rtx_code new_code = code; + rtx op0 = XEXP (operands[1], 0); + rtx op1 = XEXP (operands[1], 1); - else if (TARGET_PRETEND_CMOVE) - { - enum rtx_code code = GET_CODE (operands[1]); - enum rtx_code new_code = code; - rtx op0 = XEXP (operands[1], 0); - rtx op1 = XEXP (operands[1], 1); + if (! currently_expanding_to_rtl) + FAIL; - if (! currently_expanding_to_rtl) - FAIL; - switch (code) - { - case LT: case LE: case LEU: case LTU: - if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT) - break; - case NE: - new_code = reverse_condition (code); - break; - case EQ: case GT: case GE: case GEU: case GTU: - break; - default: - FAIL; - } - sh_emit_scc_to_t (new_code, op0, op1); - operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode, - gen_rtx_REG (SImode, T_REG), const0_rtx); - } - else + switch (code) { - if (!can_create_pseudo_p ()) - FAIL; - - operands[1] = sh_emit_cheap_store_flag (GET_MODE (operands[0]), - GET_CODE (operands[1]), - XEXP (operands[1], 0), - XEXP (operands[1], 1)); - if (!operands[1]) + case LT: case LE: case LEU: case LTU: + if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT) + break; + case NE: + new_code = reverse_condition (code); + break; + case EQ: case GT: case GE: case GEU: case GTU: + break; + default: FAIL; } -}) -(define_expand "movqicc" - [(set (match_operand:QI 0 "register_operand" "") - (if_then_else:QI (match_operand 1 "comparison_operator" "") - (match_operand:QI 2 "register_operand" "") - (match_operand:QI 3 "register_operand" "")))] - "TARGET_SHMEDIA" -{ - operands[0] = simplify_gen_subreg (SImode, operands[0], QImode, 0); - operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0); - operands[3] = simplify_gen_subreg (SImode, operands[3], QImode, 0); - emit (gen_movsicc (operands[0], operands[1], operands[2], operands[3])); - DONE; + sh_emit_scc_to_t (new_code, op0, op1); + operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode, + gen_rtx_REG (SImode, T_REG), const0_rtx); }) - + ;; ------------------------------------------------------------------------- ;; Addition instructions ;; ------------------------------------------------------------------------- @@ -1856,37 +1537,6 @@ } }) -(define_insn "*adddi3_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,r") - (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r") - (match_operand:DI 2 "arith_operand" "r,I10")))] - "TARGET_SHMEDIA" - "@ - add %1, %2, %0 - addi %1, %2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "*adddisi3_media" - [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r,r") 0) - (plus:DI (match_operand:DI 1 "arith_reg_operand" "%r,r") - (match_operand:DI 2 "arith_operand" "r,I10")))] - "TARGET_SHMEDIA" - "@ - add.l %1, %2, %0 - addi.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_insn "adddi3z_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extend:DI - (plus:SI (match_operand:SI 1 "extend_reg_operand" "r") - (match_operand:SI 2 "extend_reg_or_0_operand" "rN"))))] - "TARGET_SHMEDIA" - "addz.l %1, %N2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - (define_insn_and_split "adddi3_compact" [(set (match_operand:DI 0 "arith_reg_dest") (plus:DI (match_operand:DI 1 "arith_reg_operand") @@ -2140,30 +1790,6 @@ } }) -(define_insn "addsi3_media" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (plus:SI (match_operand:SI 1 "extend_reg_operand" "%r,r") - (match_operand:SI 2 "arith_operand" "r,I10")))] - "TARGET_SHMEDIA" - "@ - add.l %1, %2, %0 - addi.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_insn "addsidi3_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,r") - (sign_extend:DI (plus:SI (match_operand:SI 1 "extend_reg_operand" - "%r,r") - (match_operand:SI 2 "arith_operand" - "r,I10"))))] - "TARGET_SHMEDIA" - "@ - add.l %1, %2, %0 - addi.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - ;; The *addsi3_compact is made an insn_and_split and accepts actually ;; impossible constraints to make LRA's register elimination work well on SH. ;; The problem is that LRA expects something like @@ -2317,23 +1943,6 @@ } }) -(define_insn "*subdi3_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN") - (match_operand:DI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "sub %N1, %2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "subdisi3_media" - [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0) - (minus:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rN") - (match_operand:DI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "sub.l %N1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - (define_insn_and_split "subdi3_compact" [(set (match_operand:DI 0 "arith_reg_dest") (minus:DI (match_operand:DI 1 "arith_reg_operand") @@ -2539,41 +2148,6 @@ "sub %2,%0" [(set_attr "type" "arith")]) -(define_insn_and_split "*subsi3_media" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (minus:SI (match_operand:SI 1 "minuend_operand" "rN") - (match_operand:SI 2 "extend_reg_operand" "r")))] - "TARGET_SHMEDIA - && (operands[1] != constm1_rtx - || (GET_CODE (operands[2]) != TRUNCATE - && GET_CODE (operands[2]) != SUBREG))" - "sub.l %N1, %2, %0" - "operands[1] == constm1_rtx" - [(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))] - "" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_split - [(set (match_operand:SI 0 "arith_reg_dest" "") - (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1 - "general_extend_operand" - "") 0)) 0)))] - "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN" - [(set (match_dup 0) (zero_extend:SI (match_dup 1))) - (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))] - "") - -(define_split - [(set (match_operand:SI 0 "arith_reg_dest" "") - (zero_extend:SI (subreg:QI (not:SI (subreg:SI (match_operand:QI 1 - "general_extend_operand" - "") 0)) 3)))] - "TARGET_SHMEDIA && TARGET_BIG_ENDIAN" - [(set (match_dup 0) (zero_extend:SI (match_dup 1))) - (set (match_dup 0) (xor:SI (match_dup 0) (const_int 255)))] - "") - ;; Convert ;; constant - reg ;; to @@ -2597,14 +2171,6 @@ emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); DONE; } - if (TARGET_SHMEDIA) - { - if (!can_create_pseudo_p () - && ! arith_reg_or_0_operand (operands[1], SImode)) - FAIL; - if (operands[1] != const0_rtx && GET_CODE (operands[1]) != SUBREG) - operands[1] = force_reg (SImode, operands[1]); - } }) ;; ------------------------------------------------------------------------- @@ -2658,50 +2224,6 @@ [(set_attr "type" "sfunc") (set_attr "needs_delay_slot" "yes")]) -; Since shmedia-nofpu code could be linked against shcompact code, and -; the udivsi3 libcall has the same name, we must consider all registers -; clobbered that are in the union of the registers clobbered by the -; shmedia and the shcompact implementation. Note, if the shcompact -; implementation actually used shcompact code, we'd need to clobber -; also r23 and fr23. -(define_insn "udivsi3_i1_media" - [(set (match_operand:SI 0 "register_operand" "=z") - (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) - (clobber (reg:SI T_MEDIA_REG)) - (clobber (reg:SI PR_MEDIA_REG)) - (clobber (reg:SI R20_REG)) - (clobber (reg:SI R21_REG)) - (clobber (reg:SI R22_REG)) - (clobber (reg:DI TR0_REG)) - (clobber (reg:DI TR1_REG)) - (clobber (reg:DI TR2_REG)) - (use (match_operand 1 "target_reg_operand" "b"))] - "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)" - "blink %1, r18" - [(set_attr "type" "sfunc") - (set_attr "needs_delay_slot" "yes")]) - -(define_expand "udivsi3_i4_media" - [(set (match_dup 3) - (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) - (set (match_dup 4) - (zero_extend:DI (match_operand:SI 2 "register_operand" ""))) - (set (match_dup 5) (float:DF (match_dup 3))) - (set (match_dup 6) (float:DF (match_dup 4))) - (set (match_dup 7) (div:DF (match_dup 5) (match_dup 6))) - (set (match_dup 8) (fix:DI (match_dup 7))) - (set (match_operand:SI 0 "register_operand" "") - (truncate:SI (match_dup 8)))] - "TARGET_SHMEDIA_FPU" -{ - operands[3] = gen_reg_rtx (DImode); - operands[4] = gen_reg_rtx (DImode); - operands[5] = gen_reg_rtx (DFmode); - operands[6] = gen_reg_rtx (DFmode); - operands[7] = gen_reg_rtx (DFmode); - operands[8] = gen_reg_rtx (DImode); -}) - (define_insn "udivsi3_i4" [(set (match_operand:SI 0 "register_operand" "=y,y") (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) @@ -2740,7 +2262,7 @@ (clobber (reg:SI R5_REG)) (use (match_operand:SI 1 "arith_reg_operand" "r,r")) (use (match_operand 2 "" "Z,Ccl"))] - "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT) + "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE) && TARGET_FPU_SINGLE" "@ jsr @%1%# @@ -2809,13 +2331,6 @@ else last = gen_udivsi3_i4 (operands[0], operands[3], lab); } - else if (TARGET_SHMEDIA_FPU) - { - operands[1] = force_reg (SImode, operands[1]); - operands[2] = force_reg (SImode, operands[2]); - emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2])); - DONE; - } else if (TARGET_SH2A) { operands[1] = force_reg (SImode, operands[1]); @@ -2823,19 +2338,6 @@ emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2])); DONE; } - else if (TARGET_SH5) - { - function_symbol (operands[3], - TARGET_FPU_ANY ? "__udivsi3_i4" : "__udivsi3", - SFUNC_STATIC); - - if (TARGET_SHMEDIA) - last = gen_udivsi3_i1_media (operands[0], operands[3]); - else if (TARGET_FPU_ANY) - last = gen_udivsi3_i4_single (operands[0], operands[3], const0_rtx); - else - last = gen_udivsi3_i1 (operands[0], operands[3], const0_rtx); - } else { rtx lab = function_symbol (operands[3], "__udivsi3", SFUNC_STATIC).lab; @@ -2870,122 +2372,6 @@ [(set_attr "type" "sfunc") (set_attr "needs_delay_slot" "yes")]) -(define_insn "divsi3_i1_media" - [(set (match_operand:SI 0 "register_operand" "=z") - (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) - (clobber (reg:SI T_MEDIA_REG)) - (clobber (reg:SI PR_MEDIA_REG)) - (clobber (reg:SI R1_REG)) - (clobber (reg:SI R20_REG)) - (clobber (reg:SI R21_REG)) - (clobber (reg:SI TR0_REG)) - (use (match_operand 1 "target_reg_operand" "b"))] - "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)" - "blink %1, r18" - [(set_attr "type" "sfunc")]) - -(define_insn "divsi3_media_2" - [(set (match_operand:SI 0 "register_operand" "=z") - (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) - (clobber (reg:SI T_MEDIA_REG)) - (clobber (reg:SI PR_MEDIA_REG)) - (clobber (reg:SI R1_REG)) - (clobber (reg:SI R21_REG)) - (clobber (reg:SI TR0_REG)) - (use (reg:SI R20_REG)) - (use (match_operand 1 "target_reg_operand" "b"))] - "TARGET_SHMEDIA && (! TARGET_SHMEDIA_FPU || ! TARGET_DIVIDE_FP)" - "blink %1, r18" - [(set_attr "type" "sfunc")]) - -;; This pattern acts as a placeholder for -mdiv=inv:call to carry -;; hard reg clobbers and data dependencies that we need when we want -;; to rematerialize the division into a call. -(define_insn_and_split "divsi_inv_call" - [(set (match_operand:SI 0 "register_operand" "=r") - (div:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r"))) - (clobber (reg:SI R4_REG)) - (clobber (reg:SI R5_REG)) - (clobber (reg:SI T_MEDIA_REG)) - (clobber (reg:SI PR_MEDIA_REG)) - (clobber (reg:SI R1_REG)) - (clobber (reg:SI R21_REG)) - (clobber (reg:SI TR0_REG)) - (clobber (reg:SI R20_REG)) - (use (match_operand:SI 3 "register_operand" "r"))] - "TARGET_SHMEDIA" - "#" - "&& (reload_in_progress || reload_completed)" - [(set (match_dup 0) (match_dup 3))] - "" - [(set_attr "highpart" "must_split")]) - -;; This is the combiner pattern for -mdiv=inv:call . -(define_insn_and_split "*divsi_inv_call_combine" - [(set (match_operand:SI 0 "register_operand" "=z") - (div:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r"))) - (clobber (reg:SI R4_REG)) - (clobber (reg:SI R5_REG)) - (clobber (reg:SI T_MEDIA_REG)) - (clobber (reg:SI PR_MEDIA_REG)) - (clobber (reg:SI R1_REG)) - (clobber (reg:SI R21_REG)) - (clobber (reg:SI TR0_REG)) - (clobber (reg:SI R20_REG)) - (use (unspec:SI [(match_dup 1) - (match_operand:SI 3 "" "") - (unspec:SI [(match_operand:SI 4 "" "") - (match_dup 3) - (match_operand:DI 5 "" "")] - UNSPEC_DIV_INV_M2) - (match_operand:DI 6 "" "") - (const_int 0) - (const_int 0)] - UNSPEC_DIV_INV_M3))] - "TARGET_SHMEDIA" - "#" - "&& (reload_in_progress || reload_completed)" - [(pc)] -{ - const char *name = sh_divsi3_libfunc; - enum sh_function_kind kind = SFUNC_GOT; - rtx sym; - - emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]); - while (TARGET_DIVIDE_INV_CALL2) - { - rtx x = operands[3]; - - if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_DIV_INV_M1) - break; - x = XVECEXP (x, 0, 0); - name = "__sdivsi3_2"; - kind = SFUNC_STATIC; - emit_move_insn (gen_rtx_REG (DImode, R20_REG), x); - break; - } - sym = function_symbol (NULL, name, kind).sym; - emit_insn (gen_divsi3_media_2 (operands[0], sym)); - DONE; -} - [(set_attr "highpart" "must_split")]) - -(define_expand "divsi3_i4_media" - [(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r"))) - (set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r"))) - (set (match_dup 5) (div:DF (match_dup 3) (match_dup 4))) - (set (match_operand:SI 0 "register_operand" "=r") - (fix:SI (match_dup 5)))] - "TARGET_SHMEDIA_FPU" -{ - operands[3] = gen_reg_rtx (DFmode); - operands[4] = gen_reg_rtx (DFmode); - operands[5] = gen_reg_rtx (DFmode); -}) - (define_insn "divsi3_i4" [(set (match_operand:SI 0 "register_operand" "=y,y") (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) @@ -3013,7 +2399,7 @@ (clobber (reg:SI R2_REG)) (use (match_operand:SI 1 "arith_reg_operand" "r,r")) (use (match_operand 2 "" "Z,Ccl"))] - "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT) + "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE) && TARGET_FPU_SINGLE" "@ jsr @%1%# @@ -3075,116 +2461,6 @@ emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2])); DONE; } - else if (TARGET_DIVIDE_INV) - { - rtx dividend = operands[1]; - rtx divisor = operands[2]; - rtx tab_base; - rtx nsb_res = gen_reg_rtx (DImode); - rtx norm64 = gen_reg_rtx (DImode); - rtx tab_ix = gen_reg_rtx (DImode); - rtx norm32 = gen_reg_rtx (SImode); - rtx i92 = force_reg (DImode, GEN_INT (92)); - rtx scratch0a = gen_reg_rtx (DImode); - rtx scratch0b = gen_reg_rtx (DImode); - rtx inv0 = gen_reg_rtx (SImode); - rtx scratch1a = gen_reg_rtx (DImode); - rtx scratch1b = gen_reg_rtx (DImode); - rtx shift = gen_reg_rtx (DImode); - rtx i2p27, i43; - rtx inv1 = gen_reg_rtx (SImode); - rtx scratch2a = gen_reg_rtx (DImode); - rtx scratch2b = gen_reg_rtx (SImode); - rtx inv2 = gen_reg_rtx (SImode); - rtx scratch3a = gen_reg_rtx (DImode); - rtx scratch3b = gen_reg_rtx (DImode); - rtx scratch3c = gen_reg_rtx (DImode); - rtx scratch3d = gen_reg_rtx (SImode); - rtx scratch3e = gen_reg_rtx (DImode); - rtx result = gen_reg_rtx (SImode); - - if (! arith_reg_or_0_operand (dividend, SImode)) - dividend = force_reg (SImode, dividend); - if (! arith_reg_operand (divisor, SImode)) - divisor = force_reg (SImode, divisor); - if (flag_pic && Pmode != DImode) - { - tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table"); - tab_base = gen_datalabel_ref (tab_base); - tab_base = force_reg (DImode, gen_rtx_SIGN_EXTEND (DImode, tab_base)); - } - else - { - tab_base = gen_rtx_SYMBOL_REF (DImode, "__div_table"); - tab_base = gen_datalabel_ref (tab_base); - tab_base = force_reg (DImode, tab_base); - } - if (TARGET_DIVIDE_INV20U) - i2p27 = force_reg (DImode, GEN_INT ((unsigned HOST_WIDE_INT)-2 << 27)); - else - i2p27 = GEN_INT (0); - if (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L) - i43 = force_reg (DImode, GEN_INT (43)); - else - i43 = GEN_INT (0); - emit_insn (gen_nsbdi (nsb_res, - simplify_gen_subreg (DImode, divisor, SImode, 0))); - emit_insn (gen_ashldi3_media (norm64, - gen_rtx_SUBREG (DImode, divisor, 0), - nsb_res)); - emit_insn (gen_ashrdi3_media (tab_ix, norm64, GEN_INT (58))); - emit_insn (gen_ashrdisi3_media_high (norm32, norm64, GEN_INT (32))); - emit_insn (gen_divsi_inv_m1 (inv1, tab_base, tab_ix, norm32, - inv0, scratch0a, scratch0b, - scratch1a, scratch1b)); - emit_insn (gen_subdi3 (shift, i92, nsb_res)); - emit_insn (gen_divsi_inv_m2 (inv2, norm32, inv1, i92, - scratch2a)); - emit_insn (gen_divsi_inv_m3 (result, dividend, inv1, inv2, shift, - i2p27, i43, - scratch3a, scratch3b, scratch3c, - scratch2a, scratch2b, scratch3d, scratch3e)); - if (TARGET_DIVIDE_INV_CALL || TARGET_DIVIDE_INV_CALL2) - emit_insn (gen_divsi_inv_call (operands[0], dividend, divisor, result)); - else if (TARGET_DIVIDE_INV_FP) - emit_insn (gen_divsi_inv_fp (operands[0], dividend, divisor, result, - gen_reg_rtx (SImode), gen_reg_rtx (SImode), - gen_reg_rtx (DFmode), gen_reg_rtx (DFmode), - gen_reg_rtx (DFmode))); - else - emit_move_insn (operands[0], result); - DONE; - } - else if (TARGET_SHMEDIA_FPU && TARGET_DIVIDE_FP) - { - operands[1] = force_reg (SImode, operands[1]); - operands[2] = force_reg (SImode, operands[2]); - emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2])); - DONE; - } - else if (TARGET_SH5) - { - if (TARGET_DIVIDE_CALL2) - { - rtx tab_base = gen_rtx_SYMBOL_REF (Pmode, "__div_table"); - tab_base = gen_datalabel_ref (tab_base); - emit_move_insn (gen_rtx_REG (Pmode, R20_REG), tab_base); - } - if (TARGET_FPU_ANY && TARGET_SH1) - function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC); - else if (TARGET_DIVIDE_CALL2) - function_symbol (operands[3], "__sdivsi3_2", SFUNC_STATIC); - else - function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT); - - if (TARGET_SHMEDIA) - last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media) - (operands[0], operands[3])); - else if (TARGET_FPU_ANY) - last = gen_divsi3_i4_single (operands[0], operands[3], const0_rtx); - else - last = gen_divsi3_i1 (operands[0], operands[3]); - } else { function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT); @@ -3196,445 +2472,6 @@ DONE; }) -;; operands: scratch, tab_base, tab_ix -;; These are unspecs because we could generate an indexed addressing mode -;; even if -m5-32media, where INDEX_REG_CLASS == NO_REGS, and this would -;; confuse reload. See PR27117. -(define_insn "divsi_inv_qitable" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (unspec:QI [(match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r")] - UNSPEC_DIV_INV_TABLE)))] - "TARGET_SHMEDIA" - "ldx.ub %1, %2, %0" - [(set_attr "type" "load_media") - (set_attr "highpart" "user")]) - -;; operands: scratch, tab_base, tab_ix -(define_insn "divsi_inv_hitable" - [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (unspec:HI [(match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r")] - UNSPEC_DIV_INV_TABLE)))] - "TARGET_SHMEDIA" - "ldx.w %1, %2, %0" - [(set_attr "type" "load_media") - (set_attr "highpart" "user")]) - -;; operands: inv0, tab_base, tab_ix, norm32 -;; scratch equiv in sdivsi3_2: r19, r21 -(define_expand "divsi_inv_m0" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r") - (match_operand:SI 3 "register_operand" "r")] - UNSPEC_DIV_INV_M0)) - (clobber (match_operand:DI 4 "register_operand" "=r")) - (clobber (match_operand:DI 5 "register_operand" "=r"))] - "TARGET_SHMEDIA" -{ -/* -tab_base: r20 -tab_ix: r21 -norm32: r25 - ldx.ub r20, r21, r19 // u0.8 - shlli r21, 1, r21 - muls.l r25, r19, r19 // s2.38 - ldx.w r20, r21, r21 // s2.14 - shari r19, 24, r19 // truncate to s2.14 - sub r21, r19, r19 // some 11 bit inverse in s1.14 -*/ - - rtx inv0 = operands[0]; - rtx tab_base = operands[1]; - rtx tab_ix = operands[2]; - rtx norm32 = operands[3]; - rtx scratch0 = operands[4]; - rtx scratch0_si = gen_lowpart (SImode, scratch0); - rtx scratch1 = operands[5]; - - emit_insn (gen_divsi_inv_qitable (scratch0, tab_base, tab_ix)); - emit_insn (gen_ashldi3_media (scratch1, tab_ix, GEN_INT (1))); - emit_insn (gen_mulsidi3_media (scratch0, norm32, scratch0_si)); - emit_insn (gen_divsi_inv_hitable (scratch1, tab_base, scratch1)); - emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (24))); - emit_insn (gen_subdisi3_media (inv0, scratch1, scratch0)); - DONE; -}) - -;; operands: inv1, tab_base, tab_ix, norm32 -(define_insn_and_split "divsi_inv_m1" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r") - (match_operand:SI 3 "register_operand" "r")] - UNSPEC_DIV_INV_M1)) - (clobber (match_operand:SI 4 "register_operand" "=r")) - (clobber (match_operand:DI 5 "register_operand" "=r")) - (clobber (match_operand:DI 6 "register_operand" "=r")) - (clobber (match_operand:DI 7 "register_operand" "=r")) - (clobber (match_operand:DI 8 "register_operand" "=r"))] - "TARGET_SHMEDIA" - "#" - "&& !can_create_pseudo_p ()" - [(pc)] -{ -/* inv0: r19 - muls.l r19, r19, r18 // u0.28 - muls.l r25, r18, r18 // s2.58 - shlli r19, 45, r0 // multiply by two and convert to s2.58 - sub r0, r18, r18 - shari r18, 28, r18 // some 18 bit inverse in s1.30 -*/ - - rtx inv1 = operands[0]; - rtx tab_base = operands[1]; - rtx tab_ix = operands[2]; - rtx norm32 = operands[3]; - rtx inv0 = operands[4]; - rtx inv0_di = simplify_gen_subreg (DImode, inv0, SImode, 0); - rtx scratch0a = operands[5]; - rtx scratch0b = operands[6]; - rtx scratch0 = operands[7]; - rtx scratch1 = operands[8]; - rtx scratch1_si = gen_lowpart (SImode, scratch1); - - emit_insn (gen_divsi_inv_m0 (inv0, tab_base, tab_ix, norm32, - scratch0a, scratch0b)); - emit_insn (gen_mulsidi3_media (scratch1, inv0, inv0)); - emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si)); - emit_insn (gen_ashldi3_media (scratch0, inv0_di, GEN_INT (45))); - emit_insn (gen_subdi3 (scratch1, scratch0, scratch1)); - emit_insn (gen_ashrdisi3_media_opaque (inv1, scratch1, GEN_INT (28))); - DONE; -}) - -;; operands: inv2, norm32, inv1, i92 -(define_insn_and_split "divsi_inv_m2" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r") - (match_operand:DI 3 "register_operand" "r")] - UNSPEC_DIV_INV_M2)) - (clobber (match_operand:DI 4 "register_operand" "=r"))] - "TARGET_SHMEDIA" - "#" - "&& !can_create_pseudo_p ()" - [(pc)] -{ -/* - muls.l r18, r25, r0 // s2.60 - shari r0, 16, r0 // s-16.44 - sub - muls.l r0, r18, r19 // s-16.74 - shari r19, 30, r19 // s-16.44 -*/ - rtx inv2 = operands[0]; - rtx norm32 = operands[1]; - rtx inv1 = operands[2]; - rtx i92 = operands[3]; - rtx scratch0 = operands[4]; - rtx scratch0_si = gen_lowpart (SImode, scratch0); - - emit_insn (gen_mulsidi3_media (scratch0, inv1, norm32)); - emit_insn (gen_ashrdi3_media (scratch0, scratch0, GEN_INT (16))); - emit_insn (gen_subdi3 (scratch0, i92, scratch0)); - emit_insn (gen_mulsidi3_media (scratch0, scratch0_si, inv1)); - emit_insn (gen_ashrdisi3_media_opaque (inv2, scratch0, GEN_INT (30))); - DONE; -}) - -(define_insn_and_split "divsi_inv_m3" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN") - (match_operand:SI 2 "register_operand" "r") - (match_operand:SI 3 "register_operand" "r") - (match_operand:DI 4 "register_operand" "r") - (match_operand:DI 5 "arith_reg_or_0_operand" "rN") - (match_operand:DI 6 "arith_reg_or_0_operand" "rN")] - UNSPEC_DIV_INV_M3)) - (clobber (match_operand:DI 7 "register_operand" "=r")) - (clobber (match_operand:DI 8 "register_operand" "=r")) - (clobber (match_operand:DI 9 "register_operand" "=r")) - (clobber (match_operand:DI 10 "register_operand" "=r")) - (clobber (match_operand:SI 11 "register_operand" "=r")) - (clobber (match_operand:SI 12 "register_operand" "=r")) - (clobber (match_operand:DI 13 "register_operand" "=r"))] - "TARGET_SHMEDIA" - "#" - "&& !can_create_pseudo_p ()" - [(pc)] -{ -/* - r0: result r1: shift r4: dividend r18: inv1 r19: inv2 - r0: scratch0 r19: scratch1 r21: scratch2 - - muls.l r18, r4, r25 // s32.30 - muls.l r19, r4, r19 // s15.30 - shari r25, 63, r21 - shari r19, 14, r19 // s18.-14 - sub r25, r19, r0 - shard r0, r1, r0 - sub r0, r21, r0 -*/ - - rtx result = operands[0]; - rtx dividend = operands[1]; - rtx inv1 = operands[2]; - rtx inv2 = operands[3]; - rtx shift = operands[4]; - rtx scratch0 = operands[7]; - rtx scratch1 = operands[8]; - rtx scratch2 = operands[9]; - - if (satisfies_constraint_N (dividend)) - { - emit_move_insn (result, dividend); - DONE; - } - - emit_insn (gen_mulsidi3_media (scratch0, inv1, dividend)); - emit_insn (gen_mulsidi3_media (scratch1, inv2, dividend)); - emit_insn (gen_ashrdi3_media (scratch2, scratch0, GEN_INT (63))); - emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (14))); - emit_insn (gen_adddi3 (scratch0, scratch0, scratch1)); - emit_insn (gen_ashrdi3_media (scratch0, scratch0, shift)); - emit_insn (gen_subdisi3_media (result, scratch0, scratch2)); - DONE; -}) - -;; operands: quotient, dividend, inv1, inv2, shift, i2p27, i43 -;; inv1: tab_base, tab_ix, norm32 -;; inv2: norm32, inv1, i92 -(define_insn_and_split "divsi_inv_m1_3" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:SI 1 "arith_reg_or_0_operand" "rN") - (unspec:SI [(match_operand:DI 2 "register_operand" "r") - (match_operand:DI 3 "register_operand" "r") - (match_operand:SI 4 "register_operand" "r")] - UNSPEC_DIV_INV_M1) - (unspec:SI [(match_dup 4) - (unspec:SI [(match_dup 2) - (match_dup 3) - (match_dup 4)] UNSPEC_DIV_INV_M1) - (match_operand:SI 5 "" "")] - UNSPEC_DIV_INV_M2) - (match_operand:DI 6 "register_operand" "r") - (match_operand:DI 7 "arith_reg_or_0_operand" "rN") - (match_operand:DI 8 "arith_reg_or_0_operand" "rN")] - UNSPEC_DIV_INV_M3)) - (clobber (match_operand:DI 9 "register_operand" "=r")) - (clobber (match_operand:DI 10 "register_operand" "=r")) - (clobber (match_operand:DI 11 "register_operand" "=r")) - (clobber (match_operand:DI 12 "register_operand" "=r")) - (clobber (match_operand:SI 13 "register_operand" "=r")) - (clobber (match_operand:SI 14 "register_operand" "=r")) - (clobber (match_operand:DI 15 "register_operand" "=r"))] - "TARGET_SHMEDIA - && (TARGET_DIVIDE_INV_MINLAT - || TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)" - "#" - "&& !can_create_pseudo_p ()" - [(pc)] -{ - rtx result = operands[0]; - rtx dividend = operands[1]; - rtx tab_base = operands[2]; - rtx tab_ix = operands[3]; - rtx norm32 = operands[4]; - /* rtx i92 = operands[5]; */ - rtx shift = operands[6]; - rtx i2p27 = operands[7]; - rtx i43 = operands[8]; - rtx scratch0 = operands[9]; - rtx scratch0_si = gen_lowpart (SImode, scratch0); - rtx scratch1 = operands[10]; - rtx scratch1_si = gen_lowpart (SImode, scratch1); - rtx scratch2 = operands[11]; - rtx scratch3 = operands[12]; - rtx scratch4 = operands[13]; - rtx scratch4_di = simplify_gen_subreg (DImode, scratch4, SImode, 0); - rtx scratch5 = operands[14]; - rtx scratch5_di = simplify_gen_subreg (DImode, scratch5, SImode, 0); - rtx scratch6 = operands[15]; - - emit_insn (gen_divsi_inv_m0 (scratch4, tab_base, tab_ix, norm32, - scratch0, scratch1)); - /* inv0 == scratch4 */ - if (! TARGET_DIVIDE_INV20U) - { - emit_insn (gen_mulsidi3_media (scratch0, scratch4, scratch4)); - i2p27 = scratch0; - emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch0_si)); - } - else - { - emit_insn (gen_mulsidi3_media (scratch1, scratch4, scratch4)); - emit_insn (gen_mulsidi3_media (scratch1, norm32, scratch1_si)); - } - emit_insn (gen_ashldi3_media (scratch2, scratch4_di, GEN_INT (45))); - emit_insn (gen_subdi3 (scratch1, scratch2, scratch1)); - emit_insn (gen_ashrdisi3_media_opaque (scratch4, scratch1, GEN_INT (28))); - /* inv1 == scratch4 */ - - if (TARGET_DIVIDE_INV_MINLAT) - { - emit_insn (gen_mulsidi3_media (scratch1, scratch4, norm32)); - emit_insn (gen_mulsidi3_media (scratch2, dividend, scratch4)); - emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (16))); - emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch4)); - emit_insn (gen_ashrdi3_media (scratch3, scratch2, GEN_INT (63))); - emit_insn (gen_ashrsi3_media (scratch5, dividend, GEN_INT (14))); - emit_insn (gen_ashrdi3_media (scratch1, scratch1, GEN_INT (30))); - emit_insn (gen_mulsidi3_media (scratch1, scratch1_si, scratch5)); - emit_insn (gen_xordi3 (scratch0, scratch3, i2p27)); - emit_insn (gen_adddi3 (scratch2, scratch2, scratch0)); - emit_insn (gen_subdi3 (scratch2, scratch2, scratch1)); - } - else - { - rtx label = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ()); - /* Use separate scratch regs for nsb and sign to allow scheduling. */ - emit_insn (gen_nsbdi (scratch6, - simplify_gen_subreg (DImode, dividend, SImode, 0))); - emit_insn (gen_xorsi3 (scratch5, dividend, norm32)); - emit_insn (gen_ashrdi3_media (scratch3, scratch5_di, GEN_INT (63))); - emit_insn (gen_divsi_inv20 (scratch2, - norm32, scratch4, dividend, - scratch6, scratch3, i43, - /* scratch0 may be shared with i2p27. */ - scratch0, scratch1, scratch5, - label, label, i2p27)); - } - emit_insn (gen_ashrdi3_media (scratch2, scratch2, shift)); - emit_insn (gen_subdisi3_media (result, scratch2, scratch3)); - DONE; -}) - -(define_insn "divsi_inv20" - [(set (match_operand:DI 0 "register_operand" "=&r") - (unspec:DI [(match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r") - (match_operand:SI 3 "register_operand" "r") - (match_operand:DI 4 "register_operand" "r") - (match_operand:DI 5 "register_operand" "r") - (match_operand:DI 6 "register_operand" "r") - (match_operand:DI 12 "register_operand" "r") - (match_operand 10 "target_operand" "b") - (match_operand 11 "immediate_operand" "i")] - UNSPEC_DIV_INV20)) - (clobber (match_operand:DI 7 "register_operand" "=&r")) - (clobber (match_operand:DI 8 "register_operand" "=&r")) - (clobber (match_operand:SI 9 "register_operand" "=r"))] - "TARGET_SHMEDIA - && (TARGET_DIVIDE_INV20U || TARGET_DIVIDE_INV20L)" -{ -/* operands: %0 div_result, %1 norm32, %2 inv1, %3 dividend, - %4 dividend_nsb, %5 result_sign, %6 i43, %12 i2p27, - %7 round_scratch, %8 scratch0 (di), %9 scratch1 (si) - %10 label (tr), %11 label (imm) - - muls.l inv1, norm32, scratch0 // s2.60 - muls.l inv1, dividend, result // s32.30 - xor i2p27, result_sign, round_scratch - bge/u dividend_nsb, i43, tr.. (label) - shari scratch0, 16, scratch0 // s-16.44 - muls.l sratch0_si, inv1, scratch0 // s-16.74 - sub result, round_scratch, result - shari dividend, 14, scratch1 // s19.-14 - shari scratch0, 30, scratch0 // s-16.44 - muls.l scratch0, scratch1, round_scratch // s15.30 -label: - sub result, round_scratch, result */ - - const bool likely = TARGET_DIVIDE_INV20L; - if (likely) - return - "muls.l %2, %3, %0" "\n" - " xor %12, %5, %7" "\n" - " bge/l %4, %6, %10" "\n" - " muls.l %2, %1, %8" "\n" - " shari %8, 16, %8" "\n" - " muls.l %8, %2, %8" "\n" - " shari %3, 14, %9" "\n" - " shari %8, 30, %8" "\n" - " muls.l %8, %9, %8" "\n" - " sub %0, %8, %0" "\n" - "%11: add %0, %7, %0"; - else - return - "muls.l %2, %1, %8" "\n" - " muls.l %2, %3, %0" "\n" - " xor %12, %5, %7" "\n" - " bge/u %4, %6, %10" "\n" - " shari %8, 16, %8" "\n" - " muls.l %8, %2, %8" "\n" - " sub %0, %7, %0" "\n" - " shari %3, 14, %9" "\n" - " shari %8, 30, %8" "\n" - " muls.l %8, %9, %7" "\n" - "%11: sub %0, %7, %0"; -}) - -(define_insn_and_split "divsi_inv_fp" - [(set (match_operand:SI 0 "general_movdst_operand" "=rf") - (div:SI (match_operand:SI 1 "general_movsrc_operand" "rf") - (match_operand:SI 2 "register_operand" "rf"))) - (use (match_operand:SI 3 "general_movsrc_operand" "r")) - (clobber (match_operand:SI 4 "register_operand" "=r")) - (clobber (match_operand:SI 5 "register_operand" "=r")) - (clobber (match_operand:DF 6 "register_operand" "=r")) - (clobber (match_operand:DF 7 "register_operand" "=r")) - (clobber (match_operand:DF 8 "register_operand" "=r"))] - "TARGET_SHMEDIA_FPU" - "#" - "&& (reload_in_progress || reload_completed)" - [(set (match_dup 0) (match_dup 3))] - "" - [(set_attr "highpart" "must_split")]) - -;; If a matching group of divide-by-inverse instructions is in the same -;; basic block after gcse & loop optimizations, we want to transform them -;; to a straight division using floating point for TARGET_DIVIDE_INV_FP. -(define_insn_and_split "*divsi_inv_fp_combine" - [(set (match_operand:SI 0 "register_operand" "=f") - (div:SI (match_operand:SI 1 "register_operand" "f") - (match_operand:SI 2 "register_operand" "f"))) - (use (unspec:SI [(match_dup 1) - (match_operand:SI 3 "" "") - (unspec:SI [(match_operand:SI 4 "" "") - (match_dup 3) - (match_operand:DI 5 "" "")] UNSPEC_DIV_INV_M2) - (match_operand:DI 6 "" "") - (const_int 0) - (const_int 0)] UNSPEC_DIV_INV_M3)) - (clobber (match_operand:SI 7 "fp_arith_reg_operand" "")) - (clobber (match_operand:SI 8 "fp_arith_reg_operand" "")) - (clobber (match_operand:DF 9 "fp_arith_reg_operand" "")) - (clobber (match_operand:DF 10 "fp_arith_reg_operand" "")) - (clobber (match_operand:DF 11 "fp_arith_reg_operand" ""))] - "TARGET_SHMEDIA_FPU && TARGET_DIVIDE_INV_FP && !can_create_pseudo_p ()" - "#" - "&& 1" - [(set (match_dup 9) (float:DF (match_dup 1))) - (set (match_dup 10) (float:DF (match_dup 2))) - (set (match_dup 11) (div:DF (match_dup 9) (match_dup 10))) - (set (match_dup 8) - (fix:SI (match_dup 11))) - (set (match_dup 0) (match_dup 8))] -{ - if (! fp_arith_reg_operand (operands[1], SImode)) - { - emit_move_insn (operands[7], operands[1]); - operands[1] = operands[7]; - } - if (! fp_arith_reg_operand (operands[2], SImode)) - { - emit_move_insn (operands[8], operands[2]); - operands[2] = operands[8]; - } -} - [(set_attr "highpart" "must_split")]) ;; ------------------------------------------------------------------------- ;; Multiplication instructions @@ -3819,24 +2656,12 @@ label: [(set (match_operand:DI 0 "arith_reg_dest" "") (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "")) (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))] - "TARGET_SH2 || TARGET_SHMEDIA" + "TARGET_SH2" { - if (TARGET_SH2) - { - emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "mulsidi3_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r")) - (sign_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))] - "TARGET_SHMEDIA" - "muls.l %1, %2, %0" - [(set_attr "type" "dmpy_media") - (set_attr "highpart" "ignore")]) - (define_insn_and_split "mulsidi3_compact" [(set (match_operand:DI 0 "arith_reg_dest" "=r") (mult:DI @@ -3880,24 +2705,12 @@ label: [(set (match_operand:DI 0 "arith_reg_dest" "") (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "")) (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))] - "TARGET_SH2 || TARGET_SHMEDIA" + "TARGET_SH2" { - if (TARGET_SH2) - { - emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "umulsidi3_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (mult:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "%r")) - (zero_extend:DI (match_operand:SI 2 "extend_reg_operand" "r"))))] - "TARGET_SHMEDIA" - "mulu.l %1, %2, %0" - [(set_attr "type" "dmpy_media") - (set_attr "highpart" "ignore")]) - (define_insn_and_split "umulsidi3_compact" [(set (match_operand:DI 0 "arith_reg_dest" "=r") (mult:DI @@ -4011,45 +2824,6 @@ label: DONE; }) -(define_insn_and_split "muldi3" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (mult:DI (match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "arith_reg_operand" "r"))) - (clobber (match_scratch:DI 3 "=&r")) - (clobber (match_scratch:DI 4 "=r"))] - "TARGET_SHMEDIA" - "#" - "reload_completed" - [(const_int 0)] -{ - rtx op3_v2si, op2_v2si; - - op3_v2si = operands[3]; - if (GET_CODE (op3_v2si) == SIGN_EXTEND) - { - op3_v2si = XEXP (op3_v2si, 0); - op3_v2si = simplify_gen_subreg (DImode, op3_v2si, GET_MODE (op3_v2si), 0); - } - op3_v2si = simplify_gen_subreg (V2SImode, op3_v2si, DImode, 0); - op2_v2si = operands[2]; - if (GET_CODE (op2_v2si) == SIGN_EXTEND) - { - op2_v2si = XEXP (op2_v2si, 0); - op2_v2si = simplify_gen_subreg (DImode, op2_v2si, GET_MODE (op2_v2si), 0); - } - op2_v2si = simplify_gen_subreg (V2SImode, op2_v2si, DImode, 0); - emit_insn (gen_rotldi3 (operands[3], operands[1], GEN_INT (32))); - emit_insn (gen_mulv2si3 (op3_v2si, op3_v2si, op2_v2si)); - emit_insn (gen_umulsidi3_media (operands[4], - sh_gen_truncate (SImode, operands[1], 0), - sh_gen_truncate (SImode, operands[2], 0))); - emit_insn (gen_anddi3 (operands[0], operands[3], GEN_INT (0xffffffff00000000LL))); - emit_insn (gen_ashldi3_media (operands[3], operands[3], GEN_INT (32))); - emit_insn (gen_adddi3 (operands[0], operands[3], operands[0])); - emit_insn (gen_adddi3 (operands[0], operands[4], operands[0])); - DONE; -}) - ;; ------------------------------------------------------------------------- ;; Logical operations ;; ------------------------------------------------------------------------- @@ -4105,16 +2879,6 @@ label: } [(set_attr "type" "arith")]) -(define_insn "*andsi3_media" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (and:SI (match_operand:SI 1 "logical_reg_operand" "%r,r") - (match_operand:SI 2 "logical_operand" "r,I10")))] - "TARGET_SHMEDIA" - "@ - and %1, %2, %0 - andi %1, %2, %0" - [(set_attr "type" "arith_media")]) - (define_insn "*andsi3_bclr" [(set (match_operand:SI 0 "arith_reg_dest" "=r") (and:SI (match_operand:SI 1 "arith_reg_operand" "%0") @@ -4123,43 +2887,6 @@ label: "bclr %W2,%0" [(set_attr "type" "arith")]) -(define_insn_and_split "anddi3" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r") - (and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r") - (match_operand:DI 2 "and_operand" "r,I10,J16")))] - "TARGET_SHMEDIA" - "@ - and %1, %2, %0 - andi %1, %2, %0 - #" - "reload_completed - && ! logical_operand (operands[2], DImode)" - [(const_int 0)] -{ - if ((unsigned)INTVAL (operands[2]) == (unsigned) 0xffffffff) - emit_insn (gen_mshflo_l_di (operands[0], operands[1], CONST0_RTX (DImode))); - else - emit_insn (gen_mshfhi_l_di (operands[0], CONST0_RTX (DImode), operands[1])); - DONE; -} - [(set_attr "type" "arith_media")]) - -(define_insn "andcsi3" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (and:SI (match_operand:SI 1 "arith_reg_operand" "r") - (not:SI (match_operand:SI 2 "arith_reg_operand" "r"))))] - "TARGET_SHMEDIA" - "andc %1,%2,%0" - [(set_attr "type" "arith_media")]) - -(define_insn "andcdi3" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (and:DI (match_operand:DI 1 "arith_reg_operand" "r") - (not:DI (match_operand:DI 2 "arith_reg_operand" "r"))))] - "TARGET_SHMEDIA" - "andc %1,%2,%0" - [(set_attr "type" "arith_media")]) - (define_expand "iorsi3" [(set (match_operand:SI 0 "arith_reg_operand" "") (ior:SI (match_operand:SI 1 "logical_reg_operand" "") @@ -4176,16 +2903,6 @@ label: "or %2,%0" [(set_attr "type" "arith")]) -(define_insn "*iorsi3_media" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (ior:SI (match_operand:SI 1 "logical_reg_operand" "%r,r") - (match_operand:SI 2 "logical_operand" "r,I10")))] - "TARGET_SHMEDIA" - "@ - or %1, %2, %0 - ori %1, %2, %0" - [(set_attr "type" "arith_media")]) - (define_insn "*iorsi3_bset" [(set (match_operand:SI 0 "arith_reg_dest" "=r") (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0") @@ -4194,58 +2911,10 @@ label: "bset %V2,%0" [(set_attr "type" "arith")]) -(define_insn "iordi3" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,r") - (ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r") - (match_operand:DI 2 "logical_operand" "r,I10")))] - "TARGET_SHMEDIA" - "@ - or %1, %2, %0 - ori %1, %2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn_and_split "*logical_sidi3" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,r") - (sign_extend:DI (match_operator:SI 3 "logical_operator" - [(match_operand:SI 1 "arith_reg_operand" "%r,r") - (match_operand:SI 2 "logical_operand" "r,I10")])))] - "TARGET_SHMEDIA" - "#" - "&& reload_completed" - [(set (match_dup 0) (match_dup 3))] -{ - operands[3] - = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, - simplify_gen_subreg (DImode, operands[1], SImode, 0), - simplify_gen_subreg (DImode, operands[2], SImode, 0)); -}) - -(define_insn_and_split "*logical_sidisi3" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (truncate:SI (sign_extend:DI - (match_operator:SI 3 "logical_operator" - [(match_operand:SI 1 "arith_reg_operand" "%r,r") - (match_operand:SI 2 "logical_operand" "r,I10")]))))] - "TARGET_SHMEDIA" - "#" - "&& 1" - [(set (match_dup 0) (match_dup 3))]) - -(define_insn_and_split "*logical_sidi3_2" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,r") - (sign_extend:DI (truncate:SI (sign_extend:DI - (match_operator:SI 3 "logical_operator" - [(match_operand:SI 1 "arith_reg_operand" "%r,r") - (match_operand:SI 2 "logical_operand" "r,I10")])))))] - "TARGET_SHMEDIA" - "#" - "&& 1" - [(set (match_dup 0) (sign_extend:DI (match_dup 3)))]) - (define_expand "xorsi3" [(set (match_operand:SI 0 "arith_reg_operand" "") (xor:SI (match_operand:SI 1 "logical_reg_operand" "") - (match_operand:SI 2 "xor_operand" "")))] + (match_operand:SI 2 "logical_operand" "")))] "" "") @@ -4277,51 +2946,6 @@ label: operands[1], operands[4]); }) -(define_insn "*xorsi3_media" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (xor:SI (match_operand:SI 1 "logical_reg_operand" "%r,r") - (match_operand:SI 2 "xor_operand" "r,I06")))] - "TARGET_SHMEDIA" - "@ - xor %1, %2, %0 - xori %1, %2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "xordi3" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,r") - (xor:DI (match_operand:DI 1 "arith_reg_operand" "%r,r") - (match_operand:DI 2 "xor_operand" "r,I06")))] - "TARGET_SHMEDIA" - "@ - xor %1, %2, %0 - xori %1, %2, %0" - [(set_attr "type" "arith_media")]) - -;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate. -;; converts 2 * sign extend -> logical op into logical op -> sign extend -(define_split - [(set (match_operand:DI 0 "arith_reg_dest" "") - (sign_extend:DI (match_operator 4 "binary_logical_operator" - [(match_operand 1 "any_register_operand" "") - (match_operand 2 "any_register_operand" "")])))] - "TARGET_SHMEDIA" - [(set (match_dup 5) (match_dup 4)) - (set (match_dup 0) (sign_extend:DI (match_dup 5)))] -{ - machine_mode inmode = GET_MODE (operands[1]); - int offset = 0; - - if (GET_CODE (operands[0]) == SUBREG) - { - offset = SUBREG_BYTE (operands[0]); - operands[0] = SUBREG_REG (operands[0]); - } - gcc_assert (REG_P (operands[0])); - if (TARGET_BIG_ENDIAN) - offset += 8 - GET_MODE_SIZE (inmode); - operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset); -}) - ;; ------------------------------------------------------------------------- ;; Shifts and rotates ;; ------------------------------------------------------------------------- @@ -4355,67 +2979,6 @@ label: emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0])); }) -(define_expand "rotldi3" - [(set (match_operand:DI 0 "arith_reg_dest" "") - (rotate:DI (match_operand:DI 1 "arith_reg_operand" "") - (match_operand:HI 2 "mextr_bit_offset" "")))] - "TARGET_SHMEDIA" -{ - if (! mextr_bit_offset (operands[2], HImode)) - FAIL; -}) - -(define_insn "rotldi3_mextr" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (rotate:DI (match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:HI 2 "mextr_bit_offset" "i")))] - "TARGET_SHMEDIA" -{ - static char templ[16]; - sprintf (templ, "mextr%d %%1,%%1,%%0", - 8 - (int) (INTVAL (operands[2]) >> 3)); - return templ; -} - [(set_attr "type" "arith_media")]) - -(define_expand "rotrdi3" - [(set (match_operand:DI 0 "arith_reg_dest" "") - (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "") - (match_operand:HI 2 "mextr_bit_offset" "")))] - "TARGET_SHMEDIA" -{ - if (! mextr_bit_offset (operands[2], HImode)) - FAIL; -}) - -(define_insn "rotrdi3_mextr" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (rotatert:DI (match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:HI 2 "mextr_bit_offset" "i")))] - "TARGET_SHMEDIA" -{ - static char templ[16]; - sprintf (templ, "mextr%d %%1,%%1,%%0", (int) INTVAL (operands[2]) >> 3); - return templ; -} - [(set_attr "type" "arith_media")]) - -(define_split - [(set (match_operand:DI 0 "arith_reg_dest" "") - (ior:DI (zero_extend:DI (mem:QI (match_operand 1 - "ua_address_operand" ""))) - (ashift:DI (match_operand:DI 2 "arith_reg_operand" "") - (const_int 8)))) - (clobber (match_operand:DI 3 "register_operand" ""))] - "TARGET_SHMEDIA" - [(match_dup 4) (match_dup 5)] -{ - operands[4] = ((TARGET_LITTLE_ENDIAN ? gen_ldhi_q : gen_ldlo_q) - (operands[3], operands[1])); - operands[5] = gen_mextr_rl (operands[0], operands[3], operands[2], - GEN_INT (56), GEN_INT (8)); -}) - (define_expand "rotrsi3" [(set (match_operand:SI 0 "arith_reg_dest") (rotatert:SI (match_operand:SI 1 "arith_reg_operand") @@ -5007,17 +3570,6 @@ label: (match_operand:SI 2 "shift_count_operand" "")))] "" { - if (TARGET_SHMEDIA) - { - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0) - { - operands[2] = GEN_INT (-INTVAL (operands[2])); - emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2])); - DONE; - } - emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2])); - DONE; - } if (TARGET_DYNSHIFT && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2])) { @@ -5196,17 +3748,6 @@ label: DONE; }) -(define_insn "ashlsi3_media" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (ashift:SI (match_operand:SI 1 "extend_reg_operand" "r,r") - (match_operand:SI 2 "shift_count_operand" "r,n")))] - "TARGET_SHMEDIA" - "@ - shlld.l %1, %2, %0 - shlli.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;; HImode shift left @@ -5259,17 +3800,6 @@ label: (clobber (reg:SI T_REG))])] "" { - if (TARGET_SHMEDIA) - { - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0) - { - operands[2] = GEN_INT (-INTVAL (operands[2])); - emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2])); - DONE; - } - emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2])); - DONE; - } if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1) { emit_insn (gen_ashldi3_k (operands[0], operands[1])); @@ -5324,25 +3854,6 @@ label: DONE; }) -(define_insn "ashldi3_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,r") - (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r,r") - (match_operand:DI 2 "shift_count_operand" "r,n")))] - "TARGET_SHMEDIA" - "@ - shlld %1, %2, %0 - shlli %1, %2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "*ashldisi3_media" - [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0) - (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "const_int_operand" "n")))] - "TARGET_SHMEDIA && INTVAL (operands[2]) < 32" - "shlli.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;; SImode arithmetic shift right ;; @@ -5358,17 +3869,6 @@ label: (clobber (reg:SI T_REG))])] "" { - if (TARGET_SHMEDIA) - { - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0) - { - operands[2] = GEN_INT (-INTVAL (operands[2])); - emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2])); - DONE; - } - emit_insn (gen_ashrsi3_media (operands[0], operands[1], operands[2])); - DONE; - } if (expand_ashiftrt (operands)) DONE; else @@ -5460,17 +3960,6 @@ label: [(set_attr "type" "sfunc") (set_attr "needs_delay_slot" "yes")]) -(define_insn "ashrsi3_media" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (ashiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r") - (match_operand:SI 2 "shift_count_operand" "r,n")))] - "TARGET_SHMEDIA" - "@ - shard.l %1, %2, %0 - shari.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;; DImode arithmetic shift right @@ -5481,17 +3970,6 @@ label: (clobber (reg:SI T_REG))])] "" { - if (TARGET_SHMEDIA) - { - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0) - { - operands[2] = GEN_INT (-INTVAL (operands[2])); - emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2])); - DONE; - } - emit_insn (gen_ashrdi3_media (operands[0], operands[1], operands[2])); - DONE; - } if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1) FAIL; }) @@ -5513,45 +3991,6 @@ label: DONE; }) -(define_insn "ashrdi3_media" - [(set (match_operand:DI 0 "ext_dest_operand" "=r,r") - (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r") - (match_operand:DI 2 "shift_count_operand" "r,n")))] - "TARGET_SHMEDIA - && (arith_reg_dest (operands[0], DImode) - || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 32))" - "@ - shard %1, %2, %0 - shari %1, %2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "*ashrdisi3_media" - [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0) - (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "const_int_operand" "n")))] - "TARGET_SHMEDIA && INTVAL (operands[2]) < 32" - "shari.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_insn "ashrdisi3_media_high" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (truncate:SI - (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "const_int_operand" "n"))))] - "TARGET_SHMEDIA && INTVAL (operands[2]) >= 32" - "shari %1, %2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "ashrdisi3_media_opaque" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (unspec:SI [(match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "const_int_operand" "n")] - UNSPEC_ASHIFTRT))] - "TARGET_SHMEDIA" - "shari %1, %2, %0" - [(set_attr "type" "arith_media")]) - ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;; SImode logical shift right @@ -5561,18 +4000,6 @@ label: (match_operand:SI 2 "shift_count_operand" "")))] "" { - if (TARGET_SHMEDIA) - { - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0) - { - operands[2] = GEN_INT (-INTVAL (operands[2])); - emit_insn (gen_ashlsi3_media (operands[0], operands[1], operands[2])); - DONE; - } - emit_insn (gen_lshrsi3_media (operands[0], operands[1], operands[2])); - DONE; - } - /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn here, otherwise the pattern will never match due to the shift amount reg negation. */ @@ -5748,17 +4175,6 @@ label: "shlr %0" [(set_attr "type" "arith")]) -(define_insn "lshrsi3_media" - [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") - (lshiftrt:SI (match_operand:SI 1 "extend_reg_operand" "r,r") - (match_operand:SI 2 "shift_count_operand" "r,n")))] - "TARGET_SHMEDIA" - "@ - shlrd.l %1, %2, %0 - shlri.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;; DImode logical shift right @@ -5769,17 +4185,6 @@ label: (clobber (reg:SI T_REG))])] "" { - if (TARGET_SHMEDIA) - { - if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0) - { - operands[2] = GEN_INT (-INTVAL (operands[2])); - emit_insn (gen_ashldi3_media (operands[0], operands[1], operands[2])); - DONE; - } - emit_insn (gen_lshrdi3_media (operands[0], operands[1], operands[2])); - DONE; - } if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1) FAIL; }) @@ -5801,27 +4206,6 @@ label: DONE; }) -(define_insn "lshrdi3_media" - [(set (match_operand:DI 0 "ext_dest_operand" "=r,r") - (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r,r") - (match_operand:DI 2 "shift_count_operand" "r,n")))] - "TARGET_SHMEDIA - && (arith_reg_dest (operands[0], DImode) - || (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 32))" - "@ - shlrd %1, %2, %0 - shlri %1, %2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "*lshrdisi3_media" - [(set (subreg:DI (match_operand:SI 0 "arith_reg_operand" "=r") 0) - (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "const_int_operand" "n")))] - "TARGET_SHMEDIA && INTVAL (operands[2]) < 32" - "shlri.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ;; Combined left/right shifts @@ -6082,13 +4466,6 @@ label: DONE; }); -(define_insn "*negdi_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (neg:DI (match_operand:DI 1 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "sub r63, %1, %0" - [(set_attr "type" "arith_media")]) - ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI) ;; can be combined. (define_expand "negdi2" @@ -6178,12 +4555,6 @@ label: } [(set_attr "type" "arith")]) -(define_expand "one_cmpldi2" - [(set (match_operand:DI 0 "arith_reg_dest" "") - (xor:DI (match_operand:DI 1 "arith_reg_operand" "") - (const_int -1)))] - "TARGET_SHMEDIA" "") - (define_expand "abs2" [(parallel [(set (match_operand:SIDI 0 "arith_reg_dest") (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))) @@ -6419,64 +4790,6 @@ label: ;; Zero extension instructions ;; ------------------------------------------------------------------------- -(define_insn "zero_extendsidi2" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extend:DI (match_operand:SI 1 "extend_reg_operand" "r")))] - "TARGET_SHMEDIA" - "addz.l %1, r63, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "extend")]) - -(define_insn "zero_extendhidi2" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))] - "TARGET_SHMEDIA" - "@ - # - ld%M1.uw %m1, %0" - [(set_attr "type" "*,load_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))] - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48))) - (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))] -{ - if (GET_CODE (operands[1]) == TRUNCATE) - operands[1] = XEXP (operands[1], 0); -}) - -;; ??? when a truncated input to a zero_extend is reloaded, reload will -;; reload the entire truncate expression. -(define_insn_and_split "*loaddi_trunc" - [(set (match_operand 0 "any_register_operand" "=r") - (truncate (match_operand:DI 1 "memory_operand" "m")))] - "TARGET_SHMEDIA && reload_completed" - "#" - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 0) (match_dup 1))] -{ - operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0])); -}) - -(define_insn "zero_extendqidi2" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (zero_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))] - "TARGET_SHMEDIA" - "@ - andi %1, 255, %0 - ld%M1.ub %m1, %0" - [(set_attr "type" "arith_media,load_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - (define_expand "zero_extendsi2" [(set (match_operand:SI 0 "arith_reg_dest") (zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))]) @@ -6502,48 +4815,6 @@ label: } [(set_attr "type" "arith")]) -(define_insn "*zero_extendhisi2_media" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))] - "TARGET_SHMEDIA" - "@ - # - ld%M1.uw %m1, %0" - [(set_attr "type" "arith_media,load_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))] - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) - (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] -{ - rtx op1 = operands[1]; - - if (GET_CODE (op1) == TRUNCATE) - op1 = XEXP (op1, 0); - operands[2] - = simplify_gen_subreg (SImode, op1, GET_MODE (op1), - subreg_lowpart_offset (SImode, GET_MODE (op1))); -}) - -(define_insn "*zero_extendqisi2_media" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))] - "TARGET_SHMEDIA" - "@ - andi %1, 255, %0 - ld%M1.ub %m1, %0" - [(set_attr "type" "arith_media,load_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "arith_reg_dest" "=r") (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))] @@ -6633,100 +4904,11 @@ label: ;; ??? Or perhaps it should be dropped? ;; convert_move generates good code for SH[1-4]. -(define_insn "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "=r,r,r") - (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,?f")))] - "TARGET_SHMEDIA" - "@ - add.l %1, r63, %0 - ld%M1.l %m1, %0 - fmov.sl %1, %0" - [(set_attr "type" "arith_media,load_media,fpconv_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "extend")))]) - -(define_insn "extendhidi2" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (sign_extend:DI (match_operand:HI 1 "general_extend_operand" "r,m")))] - "TARGET_SHMEDIA" - "@ - # - ld%M1.w %m1, %0" - [(set_attr "type" "*,load_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))] - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48))) - (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))] -{ - if (GET_CODE (operands[1]) == TRUNCATE) - operands[1] = XEXP (operands[1], 0); -}) - -(define_insn "extendqidi2" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (sign_extend:DI (match_operand:QI 1 "general_extend_operand" "r,m")))] - "TARGET_SHMEDIA" - "@ - # - ld%M1.b %m1, %0" - [(set_attr "type" "*,load_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))] - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56))) - (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))] -{ - if (GET_CODE (operands[1]) == TRUNCATE) - operands[1] = XEXP (operands[1], 0); -}) (define_expand "extendsi2" [(set (match_operand:SI 0 "arith_reg_dest") (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))]) -(define_insn "*extendhisi2_media" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:HI 1 "general_extend_operand" "r,m")))] - "TARGET_SHMEDIA" - "@ - # - ld%M1.w %m1, %0" - [(set_attr "type" "arith_media,load_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))] - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) - (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))] -{ - rtx op1 = operands[1]; - if (GET_CODE (op1) == TRUNCATE) - op1 = XEXP (op1, 0); - operands[2] - = simplify_gen_subreg (SImode, op1, GET_MODE (op1), - subreg_lowpart_offset (SImode, GET_MODE (op1))); -}) - (define_insn_and_split "*extendsi2_compact_reg" [(set (match_operand:SI 0 "arith_reg_dest" "=r") (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))] @@ -6789,34 +4971,6 @@ label: "mov. %1,%0" [(set_attr "type" "load")]) -(define_insn "*extendqisi2_media" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:QI 1 "general_extend_operand" "r,m")))] - "TARGET_SHMEDIA" - "@ - # - ld%M1.b %m1, %0" - [(set_attr "type" "arith_media,load_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))] - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 24))) - (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))] -{ - rtx op1 = operands[1]; - if (GET_CODE (op1) == TRUNCATE) - op1 = XEXP (op1, 0); - operands[2] - = simplify_gen_subreg (SImode, op1, GET_MODE (op1), - subreg_lowpart_offset (SImode, GET_MODE (op1))); -}) - (define_expand "extendqihi2" [(set (match_operand:HI 0 "arith_reg_dest") (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))] @@ -6829,94 +4983,27 @@ label: "exts.b %1,%0" [(set_attr "type" "arith")]) -;; It would seem useful to combine the truncXi patterns into the movXi -;; patterns, but unary operators are ignored when matching constraints, -;; so we need separate patterns. -(define_insn "truncdisi2" - [(set (match_operand:SI 0 "general_movdst_operand" "=r,m,m,f,r,f") - (truncate:SI (match_operand:DI 1 "register_operand" "r,r,f,r,f,f")))] - "TARGET_SHMEDIA" - "@ - add.l %1, r63, %0 - st%M0.l %m0, %1 - fst%M0.s %m0, %T1 - fmov.ls %1, %0 - fmov.sl %T1, %0 - fmov.s %T1, %0" - [(set_attr "type" "arith_media,store_media,fstore_media,fload_media, - fpconv_media,fmove_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "extend")))]) - -(define_insn "truncdihi2" - [(set (match_operand:HI 0 "general_movdst_operand" "=?r,m") - (truncate:HI (match_operand:DI 1 "register_operand" "r,r")))] - "TARGET_SHMEDIA" -{ - static const char* alt[] = - { - "shlli %1,48,%0" "\n" - " shlri %0,48,%0", - - "st%M0.w %m0, %1" - }; - return alt[which_alternative]; -} - [(set_attr "type" "arith_media,store_media") - (set_attr "length" "8,4") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "extend")))]) - -; N.B. This should agree with LOAD_EXTEND_OP and movqi. -; Because we use zero extension, we can't provide signed QImode compares -; using a simple compare or conditional branch insn. -(define_insn "truncdiqi2" - [(set (match_operand:QI 0 "general_movdst_operand" "=r,m") - (truncate:QI (match_operand:DI 1 "register_operand" "r,r")))] - "TARGET_SHMEDIA" - "@ - andi %1, 255, %0 - st%M0.b %m0, %1" - [(set_attr "type" "arith_media,store") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "extend")))]) - ;; ------------------------------------------------------------------------- ;; Move instructions ;; ------------------------------------------------------------------------- -;; define push and pop so it is easy for sh.c -;; We can't use push and pop on SHcompact because the stack must always -;; be 8-byte aligned. (define_expand "push" [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) - (match_operand:SI 0 "register_operand" "r,l,x"))] - "TARGET_SH1 && ! TARGET_SH5" - "") + (match_operand:SI 0 "register_operand" "r,l,x"))]) (define_expand "pop" [(set (match_operand:SI 0 "register_operand" "=r,l,x") - (mem:SI (post_inc:SI (reg:SI SP_REG))))] - "TARGET_SH1 && ! TARGET_SH5" - "") + (mem:SI (post_inc:SI (reg:SI SP_REG))))]) (define_expand "push_e" [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (match_operand:SF 0 "" "")) (use (reg:SI FPSCR_MODES_REG)) - (clobber (scratch:SI))])] - "TARGET_SH1 && ! TARGET_SH5" - "") + (clobber (scratch:SI))])]) (define_insn "push_fpul" [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))] - "TARGET_SH2E && ! TARGET_SH5" + "TARGET_SH2E" "sts.l fpul,@-r15" [(set_attr "type" "fstore") (set_attr "late_fp_use" "yes") @@ -6928,21 +5015,17 @@ label: [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG))) (match_operand:DF 0 "" "")) (use (reg:SI FPSCR_MODES_REG)) - (clobber (scratch:SI))])] - "TARGET_SH1 && ! TARGET_SH5" - "") + (clobber (scratch:SI))])]) (define_expand "pop_e" [(parallel [(set (match_operand:SF 0 "" "") (mem:SF (post_inc:SI (reg:SI SP_REG)))) (use (reg:SI FPSCR_MODES_REG)) - (clobber (scratch:SI))])] - "TARGET_SH1 && ! TARGET_SH5" - "") + (clobber (scratch:SI))])]) (define_insn "pop_fpul" [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))] - "TARGET_SH2E && ! TARGET_SH5" + "TARGET_SH2E" "lds.l @r15+,fpul" [(set_attr "type" "load") (set_attr "hit_stack" "yes")]) @@ -6951,9 +5034,7 @@ label: [(parallel [(set (match_operand:DF 0 "" "") (mem:DF (post_inc:SI (reg:SI SP_REG)))) (use (reg:SI FPSCR_MODES_REG)) - (clobber (scratch:SI))])] - "TARGET_SH1 && ! TARGET_SH5" - "") + (clobber (scratch:SI))])]) (define_expand "push_fpscr" [(const_int 0)] @@ -7251,168 +5332,24 @@ label: "TARGET_SH1" "#" "&& ! currently_expanding_to_rtl" - [(set (match_dup 0) (match_dup 1))] + [(set (match_dup 0) (match_dup 1))]) + +(define_expand "movsi" + [(set (match_operand:SI 0 "general_movdst_operand" "") + (match_operand:SI 1 "general_movsrc_operand" ""))] + "" { - if (TARGET_SHCOMPACT && crtl->saves_all_registers) - operands[1] = gen_frame_mem (SImode, return_address_pointer_rtx); + prepare_move_operands (operands, SImode); }) -;; The '?'s in the following constraints may not reflect the time taken -;; to perform the move. They are there to discourage the use of floating- -;; point registers for storing integer values. -(define_insn "*movsi_media" - [(set (match_operand:SI 0 "general_movdst_operand" - "=r,r,r,r,m,f?,m,f?,r,f?,*b,r,b") - (match_operand:SI 1 "general_movsrc_operand" - "r,I16Css,nCpg,m,rZ,m,f?,rZ,f?,f?,r,*b,Csy"))] - "TARGET_SHMEDIA_FPU - && (register_operand (operands[0], SImode) - || sh_register_operand (operands[1], SImode) - || GET_CODE (operands[1]) == TRUNCATE)" - "@ - add.l %1, r63, %0 - movi %1, %0 - # - ld%M1.l %m1, %0 - st%M0.l %m0, %N1 - fld%M1.s %m1, %0 - fst%M0.s %m0, %1 - fmov.ls %N1, %0 - fmov.sl %1, %0 - fmov.s %1, %0 - ptabs %1, %0 - gettr %1, %0 - pt %1, %0" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media, - fload_media,fstore_media,fload_media,fpconv_media, - fmove_media,ptabs_media,gettr_media,pt_media") - (set_attr "length" "4,4,8,4,4,4,4,4,4,4,4,4,12") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_insn "*movsi_media_nofpu" - [(set (match_operand:SI 0 "general_movdst_operand" - "=r,r,r,r,m,*b,r,*b") - (match_operand:SI 1 "general_movsrc_operand" - "r,I16Css,nCpg,m,rZ,r,*b,Csy"))] - "TARGET_SHMEDIA - && (register_operand (operands[0], SImode) - || sh_register_operand (operands[1], SImode) - || GET_CODE (operands[1]) == TRUNCATE)" - "@ - add.l %1, r63, %0 - movi %1, %0 - # - ld%M1.l %m1, %0 - st%M0.l %m0, %N1 - ptabs %1, %0 - gettr %1, %0 - pt %1, %0" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media, - ptabs_media,gettr_media,pt_media") - (set_attr "length" "4,4,8,4,4,4,4,12") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_expand "movsi_const" - [(set (match_operand:SI 0 "arith_reg_operand" "=r") - (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s") - (const_int 16)] UNSPEC_EXTRACT_S16))) - (set (match_dup 0) - (ior:SI (ashift:SI (match_dup 0) (const_int 16)) - (const:SI (unspec:SI [(match_dup 1) - (const_int 0)] UNSPEC_EXTRACT_U16))))] - "TARGET_SHMEDIA && reload_completed - && MOVI_SHORI_BASE_OPERAND_P (operands[1])" -{ - if (GET_CODE (operands[1]) == LABEL_REF - && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL) - LABEL_NUSES (XEXP (operands[1], 0)) += 2; - else if (GOTOFF_P (operands[1])) - { - rtx unspec = XEXP (operands[1], 0); - - if (! UNSPEC_GOTOFF_P (unspec)) - { - unspec = XEXP (unspec, 0); - if (! UNSPEC_GOTOFF_P (unspec)) - abort (); - } - if (GET_CODE (XVECEXP (unspec , 0, 0)) == LABEL_REF - && (GET_CODE (XEXP (XVECEXP (unspec, 0, 0), 0)) == CODE_LABEL)) - LABEL_NUSES (XEXP (XVECEXP (unspec, 0, 0), 0)) += 2; - } -}) - -(define_expand "movsi_const_16bit" - [(set (match_operand:SI 0 "arith_reg_operand" "=r") - (const:SI (unspec:SI [(match_operand:DI 1 "immediate_operand" "s") - (const_int 0)] UNSPEC_EXTRACT_S16)))] - "TARGET_SHMEDIA && flag_pic && reload_completed - && GET_CODE (operands[1]) == SYMBOL_REF" - "") - -(define_split - [(set (match_operand:SI 0 "arith_reg_dest" "") - (match_operand:SI 1 "immediate_operand" ""))] - "TARGET_SHMEDIA && reload_completed - && MOVI_SHORI_BASE_OPERAND_P (operands[1])" - [(const_int 0)] -{ - rtx insn = emit_insn (gen_movsi_const (operands[0], operands[1])); - - set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1])); - - DONE; -}) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "immediate_operand" ""))] - "TARGET_SHMEDIA && reload_completed - && ((CONST_INT_P (operands[1]) - && ! satisfies_constraint_I16 (operands[1])) - || GET_CODE (operands[1]) == CONST_DOUBLE)" - [(set (subreg:DI (match_dup 0) 0) (match_dup 1))]) - -(define_expand "movsi" - [(set (match_operand:SI 0 "general_movdst_operand" "") - (match_operand:SI 1 "general_movsrc_operand" ""))] - "" -{ - prepare_move_operands (operands, SImode); -}) - -(define_expand "ic_invalidate_line" - [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r") - (match_dup 1)] UNSPEC_ICACHE) - (clobber (scratch:SI))])] - "TARGET_HARD_SH4 || TARGET_SH5" -{ - if (TARGET_SHMEDIA) - { - emit_insn (gen_ic_invalidate_line_media (operands[0])); - DONE; - } - else if (TARGET_SHCOMPACT) - { - operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC).sym; - operands[1] = force_reg (Pmode, operands[1]); - emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1])); - DONE; - } - else if (TARGET_SH4A || TARGET_SH4_300) - { - emit_insn (gen_ic_invalidate_line_sh4a (operands[0])); - DONE; - } - operands[0] = force_reg (Pmode, operands[0]); - operands[1] = force_reg (Pmode, GEN_INT (trunc_int_for_mode (0xf0000008, - Pmode))); +(define_expand "ic_invalidate_line" + [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r") + (match_dup 1)] UNSPEC_ICACHE) + (clobber (scratch:SI))])] + "TARGET_HARD_SH4" +{ + emit_insn (gen_ic_invalidate_line_sh4a (operands[0])); + DONE; }) ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing @@ -7447,61 +5384,6 @@ label: [(set_attr "length" "16") ;; FIXME: Why 16 and not 6? Looks like typo. (set_attr "type" "cwb")]) -;; ??? could make arg 0 an offsettable memory operand to allow to save -;; an add in the code that calculates the address. -(define_insn "ic_invalidate_line_media" - [(unspec_volatile [(match_operand 0 "any_register_operand" "r")] - UNSPEC_ICACHE)] - "TARGET_SHMEDIA" -{ - return "ocbwb %0,0" "\n" - " synco" "\n" - " icbi %0,0" "\n" - " synci"; -} - [(set_attr "length" "16") - (set_attr "type" "invalidate_line_media")]) - -(define_insn "ic_invalidate_line_compact" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "z") - (match_operand:SI 1 "register_operand" "r")] - UNSPEC_ICACHE) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT" - "jsr @%1%#" - [(set_attr "type" "sfunc") - (set_attr "needs_delay_slot" "yes")]) - -(define_expand "initialize_trampoline" - [(match_operand:SI 0 "" "") - (match_operand:SI 1 "" "") - (match_operand:SI 2 "" "")] - "TARGET_SHCOMPACT" -{ - rtx sfun, tramp; - - tramp = force_reg (Pmode, operands[0]); - sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline", - SFUNC_STATIC).sym); - emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]); - - emit_insn (gen_initialize_trampoline_compact (tramp, sfun)); - DONE; -}) - -(define_insn "initialize_trampoline_compact" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "z") - (match_operand:SI 1 "register_operand" "r") - (reg:SI R2_REG) (reg:SI R3_REG)] - UNSPEC_INIT_TRAMP) - - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT" - "jsr @%1%#" - [(set_attr "type" "sfunc") - (set_attr "needs_delay_slot" "yes")]) - (define_expand "mov" [(set (match_operand:QIHI 0 "general_movdst_operand") (match_operand:QIHI 1 "general_movsrc_operand"))] @@ -7611,78 +5493,6 @@ label: (const_int 4)] (const_int 2)))]) -(define_insn "*movqi_media" - [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m") - (match_operand:QI 1 "general_movsrc_operand" "r,I16Css,m,rZ"))] - "TARGET_SHMEDIA - && (arith_reg_operand (operands[0], QImode) - || extend_reg_or_0_operand (operands[1], QImode))" - "@ - add.l %1, r63, %0 - movi %1, %0 - ld%M1.ub %m1, %0 - st%M0.b %m0, %N1" - [(set_attr "type" "arith_media,arith_media,load_media,store_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_expand "reload_inqi" - [(set (match_operand:SI 2 "" "=&r") - (match_operand:QI 1 "inqhi_operand" "")) - (set (match_operand:QI 0 "arith_reg_operand" "=r") - (truncate:QI (match_dup 3)))] - "TARGET_SHMEDIA" -{ - rtx inner = XEXP (operands[1], 0); - int regno = REGNO (inner); - - regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1; - operands[1] = gen_rtx_REG (SImode, regno); - operands[3] = gen_rtx_REG (DImode, REGNO (operands[2])); -}) - -(define_insn "*movhi_media" - [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m") - (match_operand:HI 1 "general_movsrc_operand" "r,I16Css,n,m,rZ"))] - "TARGET_SHMEDIA - && (arith_reg_operand (operands[0], HImode) - || arith_reg_or_0_operand (operands[1], HImode))" - "@ - add.l %1, r63, %0 - movi %1, %0 - # - ld%M1.w %m1, %0 - st%M0.w %m0, %N1" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_split - [(set (match_operand:HI 0 "register_operand" "") - (match_operand:HI 1 "immediate_operand" ""))] - "TARGET_SHMEDIA && reload_completed - && ! satisfies_constraint_I16 (operands[1])" - [(set (subreg:DI (match_dup 0) 0) (match_dup 1))]) - -(define_expand "reload_inhi" - [(set (match_operand:SI 2 "" "=&r") - (match_operand:HI 1 "inqhi_operand" "")) - (set (match_operand:HI 0 "arith_reg_operand" "=r") - (truncate:HI (match_dup 3)))] - "TARGET_SHMEDIA" -{ - rtx inner = XEXP (operands[1], 0); - int regno = REGNO (inner); - - regno += HARD_REGNO_NREGS (regno, GET_MODE (inner)) - 1; - operands[1] = gen_rtx_REG (SImode, regno); - operands[3] = gen_rtx_REG (DImode, REGNO (operands[2])); -}) - ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c ;; compiled with -m2 -ml -O3 -funroll-loops (define_insn "*movdi_i" @@ -7749,287 +5559,6 @@ label: FAIL; }) -;; The '?'s in the following constraints may not reflect the time taken -;; to perform the move. They are there to discourage the use of floating- -;; point registers for storing integer values. -(define_insn "*movdi_media" - [(set (match_operand:DI 0 "general_movdst_operand" - "=r,r,r,rl,m,f?,m,f?,r,f?,*b,r,*b") - (match_operand:DI 1 "general_movsrc_operand" - "r,I16Css,nCpgF,m,rlZ,m,f?,rZ,f?,f?,r,*b,Csy"))] - "TARGET_SHMEDIA_FPU - && (register_operand (operands[0], DImode) - || sh_register_operand (operands[1], DImode))" - "@ - add %1, r63, %0 - movi %1, %0 - # - ld%M1.q %m1, %0 - st%M0.q %m0, %N1 - fld%M1.d %m1, %0 - fst%M0.d %m0, %1 - fmov.qd %N1, %0 - fmov.dq %1, %0 - fmov.d %1, %0 - ptabs %1, %0 - gettr %1, %0 - pt %1, %0" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media, - fload_media,fstore_media,fload_media,dfpconv_media, - fmove_media,ptabs_media,gettr_media,pt_media") - (set_attr "length" "4,4,16,4,4,4,4,4,4,4,4,4,*")]) - -(define_insn "*movdi_media_nofpu" - [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,*b"); - (match_operand:DI 1 "general_movsrc_operand" "r,I16Css,nCpgF,m,rlZ,r,*b,Csy"))] - "TARGET_SHMEDIA - && (register_operand (operands[0], DImode) - || sh_register_operand (operands[1], DImode))" - "@ - add %1, r63, %0 - movi %1, %0 - # - ld%M1.q %m1, %0 - st%M0.q %m0, %N1 - ptabs %1, %0 - gettr %1, %0 - pt %1, %0" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media, - ptabs_media,gettr_media,pt_media") - (set_attr "length" "4,4,16,4,4,4,4,*")]) - -(define_insn "*movdi_media_I16" - [(set (match_operand:DI 0 "ext_dest_operand" "=r") - (match_operand:DI 1 "const_int_operand" "I16"))] - "TARGET_SHMEDIA && reload_completed" - "movi %1, %0" - [(set_attr "type" "arith_media") - (set_attr "length" "4")]) - -(define_split - [(set (match_operand:DI 0 "arith_reg_dest" "") - (match_operand:DI 1 "immediate_operand" ""))] - "TARGET_SHMEDIA && reload_completed - && MOVI_SHORI_BASE_OPERAND_P (operands[1])" - [(set (match_dup 0) (match_dup 1))] -{ - rtx insn; - - if (TARGET_SHMEDIA64) - insn = emit_insn (gen_movdi_const (operands[0], operands[1])); - else - insn = emit_insn (gen_movdi_const_32bit (operands[0], operands[1])); - - set_unique_reg_note (insn, REG_EQUAL, copy_rtx (operands[1])); - - DONE; -}) - -(define_expand "movdi_const" - [(set (match_operand:DI 0 "arith_reg_operand" "=r") - (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s") - (const_int 48)] UNSPEC_EXTRACT_S16))) - (set (match_dup 0) - (ior:DI (ashift:DI (match_dup 0) (const_int 16)) - (const:DI (unspec:DI [(match_dup 1) - (const_int 32)] UNSPEC_EXTRACT_U16)))) - (set (match_dup 0) - (ior:DI (ashift:DI (match_dup 0) (const_int 16)) - (const:DI (unspec:DI [(match_dup 1) - (const_int 16)] UNSPEC_EXTRACT_U16)))) - (set (match_dup 0) - (ior:DI (ashift:DI (match_dup 0) (const_int 16)) - (const:DI (unspec:DI [(match_dup 1) - (const_int 0)] UNSPEC_EXTRACT_U16))))] - "TARGET_SHMEDIA64 && reload_completed - && MOVI_SHORI_BASE_OPERAND_P (operands[1])" -{ - sh_mark_label (operands[1], 4); -}) - -(define_expand "movdi_const_32bit" - [(set (match_operand:DI 0 "arith_reg_operand" "=r") - (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s") - (const_int 16)] UNSPEC_EXTRACT_S16))) - (set (match_dup 0) - (ior:DI (ashift:DI (match_dup 0) (const_int 16)) - (const:DI (unspec:DI [(match_dup 1) - (const_int 0)] UNSPEC_EXTRACT_U16))))] - "TARGET_SHMEDIA32 && reload_completed - && MOVI_SHORI_BASE_OPERAND_P (operands[1])" -{ - sh_mark_label (operands[1], 2); -}) - -(define_expand "movdi_const_16bit" - [(set (match_operand:DI 0 "arith_reg_operand" "=r") - (const:DI (unspec:DI [(match_operand:DI 1 "immediate_operand" "s") - (const_int 0)] UNSPEC_EXTRACT_S16)))] - "TARGET_SHMEDIA && flag_pic && reload_completed - && GET_CODE (operands[1]) == SYMBOL_REF" - "") - -(define_split - [(set (match_operand:DI 0 "ext_dest_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] - "TARGET_SHMEDIA && reload_completed - && CONST_INT_P (operands[1]) - && ! satisfies_constraint_I16 (operands[1])" - [(set (match_dup 0) (match_dup 2)) - (match_dup 1)] -{ - unsigned HOST_WIDE_INT val = INTVAL (operands[1]); - unsigned HOST_WIDE_INT low = val; - unsigned HOST_WIDE_INT high = val; - unsigned HOST_WIDE_INT sign; - unsigned HOST_WIDE_INT val2 = val ^ (val-1); - - /* Zero-extend the 16 least-significant bits. */ - low &= 0xffff; - - /* Arithmetic shift right the word by 16 bits. */ - high >>= 16; - if (GET_CODE (operands[0]) == SUBREG - && GET_MODE (SUBREG_REG (operands[0])) == SImode) - { - high &= 0xffff; - high ^= 0x8000; - high -= 0x8000; - } - else - { - sign = 1; - sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1); - high ^= sign; - high -= sign; - } - do - { - /* If we can't generate the constant with a two-insn movi / shori - sequence, try some other strategies. */ - if (! CONST_OK_FOR_I16 (high)) - { - /* Try constant load / left shift. We know VAL != 0. */ - val2 = val ^ (val-1); - if (val2 > 0x1ffff) - { - int trailing_zeroes = exact_log2 ((val2 >> 16) + 1) + 15; - - if (CONST_OK_FOR_I16 (val >> trailing_zeroes) - || (! CONST_OK_FOR_I16 (high >> 16) - && CONST_OK_FOR_I16 (val >> (trailing_zeroes + 16)))) - { - val2 = (HOST_WIDE_INT) val >> trailing_zeroes; - operands[1] = gen_ashldi3_media (operands[0], operands[0], - GEN_INT (trailing_zeroes)); - break; - } - } - /* Try constant load / right shift. */ - val2 = (val >> 15) + 1; - if (val2 == (val2 & -val2)) - { - int shift = 49 - exact_log2 (val2); - - val2 = trunc_int_for_mode (val << shift, DImode); - if (CONST_OK_FOR_I16 (val2)) - { - operands[1] = gen_lshrdi3_media (operands[0], operands[0], - GEN_INT (shift)); - break; - } - } - /* Try mperm.w . */ - val2 = val & 0xffff; - if ((val >> 16 & 0xffff) == val2 - && (val >> 32 & 0xffff) == val2 - && (val >> 48 & 0xffff) == val2) - { - val2 = (HOST_WIDE_INT) val >> 48; - operands[1] = gen_rtx_REG (V4HImode, true_regnum (operands[0])); - operands[1] = gen_mperm_w0 (operands[1], operands[1]); - break; - } - /* Try movi / mshflo.l */ - val2 = (HOST_WIDE_INT) val >> 32; - if (val2 == ((unsigned HOST_WIDE_INT) - trunc_int_for_mode (val, SImode))) - { - operands[1] = gen_mshflo_l_di (operands[0], operands[0], - operands[0]); - break; - } - /* Try movi / mshflo.l w/ r63. */ - val2 = val + ((HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 32)); - if ((HOST_WIDE_INT) val2 < 0 && CONST_OK_FOR_I16 (val2)) - { - operands[1] = gen_mshflo_l_di (operands[0], operands[0], - const0_rtx); - break; - } - } - val2 = high; - operands[1] = gen_shori_media (operands[0], operands[0], GEN_INT (low)); - } - while (0); - operands[2] = GEN_INT (val2); -}) - -(define_split - [(set (match_operand:DI 0 "ext_dest_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] - "TARGET_SHMEDIA && reload_completed - && GET_CODE (operands[1]) == CONST_DOUBLE" - [(set (match_dup 0) (match_dup 2)) - (set (match_dup 0) - (ior:DI (ashift:DI (match_dup 0) (const_int 16)) (match_dup 1)))] -{ - unsigned HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]); - unsigned HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]); - unsigned HOST_WIDE_INT val = low; - unsigned HOST_WIDE_INT sign; - - /* Zero-extend the 16 least-significant bits. */ - val &= 0xffff; - operands[1] = GEN_INT (val); - - /* Arithmetic shift right the double-word by 16 bits. */ - low >>= 16; - low |= (high & 0xffff) << (HOST_BITS_PER_WIDE_INT - 16); - high >>= 16; - sign = 1; - sign <<= (HOST_BITS_PER_WIDE_INT - 16 - 1); - high ^= sign; - high -= sign; - - /* This will only be true if high is a sign-extension of low, i.e., - it must be either 0 or (unsigned)-1, and be zero iff the - most-significant bit of low is set. */ - if (high + (low >> (HOST_BITS_PER_WIDE_INT - 1)) == 0) - operands[2] = GEN_INT (low); - else - operands[2] = immed_double_const (low, high, DImode); -}) - -(define_insn "shori_media" - [(set (match_operand:DI 0 "ext_dest_operand" "=r,r") - (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0,0") - (const_int 16)) - (match_operand:DI 2 "immediate_operand" "K16Csu,nF")))] - "TARGET_SHMEDIA && (reload_completed || arith_reg_dest (operands[0], DImode))" - "@ - shori %u2, %0 - #" - [(set_attr "type" "arith_media,*")]) - -(define_insn "*shori_media_si" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") - (const_int 16)) - (match_operand:SI 2 "immediate_operand" "K16Csu")))] - "TARGET_SHMEDIA" - "shori %u2, %0") - (define_expand "movdi" [(set (match_operand:DI 0 "general_movdst_operand" "") (match_operand:DI 1 "general_movsrc_operand" ""))] @@ -8056,63 +5585,6 @@ label: } }) -(define_insn "movdf_media" - [(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m") - (match_operand:DF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))] - "TARGET_SHMEDIA_FPU - && (register_operand (operands[0], DFmode) - || sh_register_operand (operands[1], DFmode))" - "@ - fmov.d %1, %0 - fmov.qd %N1, %0 - fmov.dq %1, %0 - add %1, r63, %0 - # - fld%M1.d %m1, %0 - fst%M0.d %m0, %1 - ld%M1.q %m1, %0 - st%M0.q %m0, %N1" - [(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*, - fload_media,fstore_media,load_media,store_media")]) - -(define_insn "movdf_media_nofpu" - [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m") - (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rZ"))] - "TARGET_SHMEDIA - && (register_operand (operands[0], DFmode) - || sh_register_operand (operands[1], DFmode))" - "@ - add %1, r63, %0 - # - ld%M1.q %m1, %0 - st%M0.q %m0, %N1" - [(set_attr "type" "arith_media,*,load_media,store_media")]) - -(define_split - [(set (match_operand:DF 0 "arith_reg_dest" "") - (match_operand:DF 1 "immediate_operand" ""))] - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 3) (match_dup 2))] -{ - int endian = WORDS_BIG_ENDIAN ? 1 : 0; - long values[2]; - - REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), values); - - if (HOST_BITS_PER_WIDE_INT >= 64) - operands[2] = immed_double_const ((unsigned long) values[endian] - | ((HOST_WIDE_INT) values[1 - endian] - << 32), 0, DImode); - else - { - gcc_assert (HOST_BITS_PER_WIDE_INT == 32); - operands[2] = immed_double_const (values[endian], values[1 - endian], - DImode); - } - - operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0])); -}) - ;; FIXME: This should be a define_insn_and_split. (define_insn "movdf_k" [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m") @@ -8171,14 +5643,8 @@ label: (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6)) (const_int 4) (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn) - ;; We can't use 4-byte push/pop on SHcompact, so we have to - ;; increment or decrement r15 explicitly. - (if_then_else - (match_test "TARGET_SHCOMPACT") - (const_int 10) (const_int 8)) - (if_then_else - (match_test "TARGET_SHCOMPACT") - (const_int 10) (const_int 8))]) + (const_int 8) + (const_int 8)]) (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,fload") (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*") (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes") @@ -8203,29 +5669,12 @@ label: { rtx insn, tos; - if (TARGET_SH5 && true_regnum (operands[1]) < 16) - { - emit_move_insn (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, -8)); - tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx); - } - else - tos = gen_tmp_stack_mem (DFmode, - gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); + tos = gen_tmp_stack_mem (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); insn = emit_insn (gen_movdf_i4 (tos, operands[1])); - if (! (TARGET_SH5 && true_regnum (operands[1]) < 16)) - add_reg_note (insn, REG_INC, stack_pointer_rtx); - if (TARGET_SH5 && true_regnum (operands[0]) < 16) - tos = gen_tmp_stack_mem (DFmode, stack_pointer_rtx); - else - tos = gen_tmp_stack_mem (DFmode, - gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); + add_reg_note (insn, REG_INC, stack_pointer_rtx); + tos = gen_tmp_stack_mem (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); insn = emit_insn (gen_movdf_i4 (operands[0], tos)); - if (TARGET_SH5 && true_regnum (operands[0]) < 16) - emit_move_insn (stack_pointer_rtx, - plus_constant (Pmode, stack_pointer_rtx, 8)); - else - add_reg_note (insn, REG_INC, stack_pointer_rtx); + add_reg_note (insn, REG_INC, stack_pointer_rtx); DONE; }) @@ -8583,14 +6032,6 @@ label: "" { prepare_move_operands (operands, DFmode); - if (TARGET_SHMEDIA) - { - if (TARGET_SHMEDIA_FPU) - emit_insn (gen_movdf_media (operands[0], operands[1])); - else - emit_insn (gen_movdf_media_nofpu (operands[0], operands[1])); - DONE; - } if (TARGET_SH4 || TARGET_SH2A_DOUBLE) { emit_insn (gen_movdf_i4 (operands[0], operands[1])); @@ -8598,216 +6039,6 @@ label: } }) -;;This is incompatible with the way gcc uses subregs. -;;(define_insn "movv2sf_i" -;; [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,m") -;; (match_operand:V2SF 1 "nonimmediate_operand" "f,m,f"))] -;; "TARGET_SHMEDIA_FPU -;; && (fp_arith_reg_operand (operands[0], V2SFmode) -;; || fp_arith_reg_operand (operands[1], V2SFmode))" -;; "@ -;; # -;; fld%M1.p %m1, %0 -;; fst%M0.p %m0, %1" -;; [(set_attr "type" "*,fload_media,fstore_media")]) -(define_insn_and_split "movv2sf_i" - [(set (match_operand:V2SF 0 "general_movdst_operand" "=f,rf,r,m,mf") - (match_operand:V2SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))] - "TARGET_SHMEDIA_FPU" - "#" - "TARGET_SHMEDIA_FPU && reload_completed" - [(set (match_dup 0) (match_dup 1))] -{ - operands[0] = simplify_gen_subreg (DFmode, operands[0], V2SFmode, 0); - operands[1] = simplify_gen_subreg (DFmode, operands[1], V2SFmode, 0); -}) - -(define_expand "movv2sf" - [(set (match_operand:V2SF 0 "general_movdst_operand" "") - (match_operand:V2SF 1 "nonimmediate_operand" ""))] - "TARGET_SHMEDIA_FPU" -{ - prepare_move_operands (operands, V2SFmode); -}) - -(define_expand "addv2sf3" - [(match_operand:V2SF 0 "fp_arith_reg_operand" "") - (match_operand:V2SF 1 "fp_arith_reg_operand" "") - (match_operand:V2SF 2 "fp_arith_reg_operand" "")] - "TARGET_SHMEDIA_FPU" -{ - sh_expand_binop_v2sf (PLUS, operands[0], operands[1], operands[2]); - DONE; -}) - -(define_expand "subv2sf3" - [(match_operand:V2SF 0 "fp_arith_reg_operand" "") - (match_operand:V2SF 1 "fp_arith_reg_operand" "") - (match_operand:V2SF 2 "fp_arith_reg_operand" "")] - "TARGET_SHMEDIA_FPU" -{ - sh_expand_binop_v2sf (MINUS, operands[0], operands[1], operands[2]); - DONE; -}) - -(define_expand "mulv2sf3" - [(match_operand:V2SF 0 "fp_arith_reg_operand" "") - (match_operand:V2SF 1 "fp_arith_reg_operand" "") - (match_operand:V2SF 2 "fp_arith_reg_operand" "")] - "TARGET_SHMEDIA_FPU" -{ - sh_expand_binop_v2sf (MULT, operands[0], operands[1], operands[2]); - DONE; -}) - -(define_expand "divv2sf3" - [(match_operand:V2SF 0 "fp_arith_reg_operand" "") - (match_operand:V2SF 1 "fp_arith_reg_operand" "") - (match_operand:V2SF 2 "fp_arith_reg_operand" "")] - "TARGET_SHMEDIA_FPU" -{ - sh_expand_binop_v2sf (DIV, operands[0], operands[1], operands[2]); - DONE; -}) - -(define_insn_and_split "*movv4sf_i" - [(set (match_operand:V4SF 0 "general_movdst_operand" "=f,rf,r,m,mf") - (match_operand:V4SF 1 "general_operand" "fm,rfm?,F?,f,rfZ?"))] - "TARGET_SHMEDIA_FPU" - "#" - "&& reload_completed" - [(const_int 0)] -{ - for (int i = 0; i < 4/2; i++) - { - rtx x, y; - - if (MEM_P (operands[0])) - x = adjust_address (operands[0], V2SFmode, - i * GET_MODE_SIZE (V2SFmode)); - else - x = simplify_gen_subreg (V2SFmode, operands[0], V4SFmode, i * 8); - - if (MEM_P (operands[1])) - y = adjust_address (operands[1], V2SFmode, - i * GET_MODE_SIZE (V2SFmode)); - else - y = simplify_gen_subreg (V2SFmode, operands[1], V4SFmode, i * 8); - - emit_insn (gen_movv2sf_i (x, y)); - } - - DONE; -} - [(set_attr "length" "8")]) - -(define_expand "movv4sf" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "") - (match_operand:V4SF 1 "general_operand" ""))] - "TARGET_SHMEDIA_FPU" -{ - prepare_move_operands (operands, V4SFmode); -}) - -(define_insn_and_split "*movv16sf_i" - [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m") - (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))] - "TARGET_SHMEDIA_FPU" - "#" - "&& reload_completed" - [(const_int 0)] -{ - for (int i = 0; i < 16/2; i++) - { - rtx x, y; - - if (MEM_P (operands[0])) - x = adjust_address (operands[0], V2SFmode, - i * GET_MODE_SIZE (V2SFmode)); - else - { - x = gen_rtx_SUBREG (V2SFmode, operands[0], i * 8); - alter_subreg (&x, true); - } - - if (MEM_P (operands[1])) - y = adjust_address (operands[1], V2SFmode, - i * GET_MODE_SIZE (V2SFmode)); - else - { - y = gen_rtx_SUBREG (V2SFmode, operands[1], i * 8); - alter_subreg (&y, true); - } - - emit_insn (gen_movv2sf_i (x, y)); - } - - DONE; -} - [(set_attr "length" "32")]) - -(define_expand "movv16sf" - [(set (match_operand:V16SF 0 "nonimmediate_operand" "=f,f,m") - (match_operand:V16SF 1 "nonimmediate_operand" "f,m,f"))] - "TARGET_SHMEDIA_FPU" -{ - prepare_move_operands (operands, V16SFmode); -}) - -(define_insn "movsf_media" - [(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m") - (match_operand:SF 1 "general_movsrc_operand" "f,rZ,f,r,F,m,f,m,rZ"))] - "TARGET_SHMEDIA_FPU - && (register_operand (operands[0], SFmode) - || sh_register_operand (operands[1], SFmode))" - "@ - fmov.s %1, %0 - fmov.ls %N1, %0 - fmov.sl %1, %0 - add.l %1, r63, %0 - # - fld%M1.s %m1, %0 - fst%M0.s %m0, %1 - ld%M1.l %m1, %0 - st%M0.l %m0, %N1" - [(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_insn "movsf_media_nofpu" - [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m") - (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rZ"))] - "TARGET_SHMEDIA - && (register_operand (operands[0], SFmode) - || sh_register_operand (operands[1], SFmode))" - "@ - add.l %1, r63, %0 - # - ld%M1.l %m1, %0 - st%M0.l %m0, %N1" - [(set_attr "type" "arith_media,*,load_media,store_media") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_split - [(set (match_operand:SF 0 "arith_reg_dest" "") - (match_operand:SF 1 "immediate_operand" ""))] - "TARGET_SHMEDIA && reload_completed - && ! FP_REGISTER_P (true_regnum (operands[0]))" - [(set (match_dup 3) (match_dup 2))] -{ - long values; - - REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), values); - operands[2] = GEN_INT (values); - - operands[3] = gen_rtx_REG (DImode, true_regnum (operands[0])); -}) - (define_insn "movsf_i" [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r") (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))] @@ -9035,14 +6266,6 @@ label: "" { prepare_move_operands (operands, SFmode); - if (TARGET_SHMEDIA) - { - if (TARGET_SHMEDIA_FPU) - emit_insn (gen_movsf_media (operands[0], operands[1])); - else - emit_insn (gen_movsf_media_nofpu (operands[0], operands[1])); - DONE; - } if (TARGET_SH2E) { if (lra_in_progress) @@ -9080,63 +6303,6 @@ label: "TARGET_SH1" "") -(define_expand "ptabs" - [(set (match_operand 0 "" "=b") (match_operand 1 "" "r"))] - "TARGET_SHMEDIA" -{ - if (!TARGET_PT_FIXED) - { - rtx eq = operands[1]; - - /* ??? For canonical RTL we really should remove any CONST from EQ - before wrapping it in the AND, and finally wrap the EQ into a - const if is constant. However, for reload we must expose the - input register or symbolic constant, and we can't have - different insn structures outside of the operands for different - alternatives of the same pattern. */ - eq = gen_rtx_EQ (SImode, gen_rtx_AND (Pmode, eq, GEN_INT (3)), - GEN_INT (3)); - operands[1] - = (gen_rtx_IF_THEN_ELSE - (PDImode, - eq, - gen_rtx_MEM (PDImode, operands[1]), - gen_rtx_fmt_e (TARGET_SHMEDIA32 ? SIGN_EXTEND : TRUNCATE, - PDImode, operands[1]))); - } -}) - -;; expanded by ptabs expander. -(define_insn "*extendsipdi_media" - [(set (match_operand:PDI 0 "target_reg_operand" "=b,b"); - (if_then_else:PDI (eq (and:SI (match_operand:SI 1 "target_operand" - "r,Csy") - (const_int 3)) - (const_int 3)) - (mem:PDI (match_dup 1)) - (sign_extend:PDI (match_dup 1))))] - "TARGET_SHMEDIA && !TARGET_PT_FIXED" - "@ - ptabs %1, %0 - pt %1, %0" - [(set_attr "type" "ptabs_media,pt_media") - (set_attr "length" "4,*")]) - -(define_insn "*truncdipdi_media" - [(set (match_operand:PDI 0 "target_reg_operand" "=b,b"); - (if_then_else:PDI (eq (and:DI (match_operand:DI 1 "target_operand" - "r,Csy") - (const_int 3)) - (const_int 3)) - (mem:PDI (match_dup 1)) - (truncate:PDI (match_dup 1))))] - "TARGET_SHMEDIA && !TARGET_PT_FIXED" - "@ - ptabs %1, %0 - pt %1, %0" - [(set_attr "type" "ptabs_media,pt_media") - (set_attr "length" "4,*")]) - (define_insn "*movsi_y" [(set (match_operand:SI 0 "register_operand" "=y,y") (match_operand:SI 1 "immediate_operand" "Qi,I08")) @@ -9248,177 +6414,6 @@ label: ;; Conditional branch insns -(define_expand "cbranchint4_media" - [(set (pc) - (if_then_else (match_operator 0 "shmedia_cbranch_comparison_operator" - [(match_operand 1 "" "") - (match_operand 2 "" "")]) - (match_operand 3 "" "") - (pc)))] - "TARGET_SHMEDIA" -{ - machine_mode mode = GET_MODE (operands[1]); - if (mode == VOIDmode) - mode = GET_MODE (operands[2]); - if (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE) - { - operands[1] = force_reg (mode, operands[1]); - if (CONSTANT_P (operands[2]) - && (! satisfies_constraint_I06 (operands[2]))) - operands[2] = force_reg (mode, operands[2]); - } - else - { - if (operands[1] != const0_rtx) - operands[1] = force_reg (mode, operands[1]); - if (operands[2] != const0_rtx) - operands[2] = force_reg (mode, operands[2]); - } - switch (GET_CODE (operands[0])) - { - case LEU: - case LE: - case LTU: - case LT: - operands[0] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[0])), - VOIDmode, operands[2], operands[1]); - operands[1] = XEXP (operands[0], 0); - operands[2] = XEXP (operands[0], 1); - break; - default: - operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), - VOIDmode, operands[1], operands[2]); - break; - } - operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]); -}) - -(define_expand "cbranchfp4_media" - [(set (pc) - (if_then_else (match_operator 0 "sh_float_comparison_operator" - [(match_operand 1 "" "") - (match_operand 2 "" "")]) - (match_operand 3 "" "") - (pc)))] - "TARGET_SHMEDIA" -{ - rtx tmp = gen_reg_rtx (SImode); - rtx cmp; - if (GET_CODE (operands[0]) == NE) - cmp = gen_rtx_EQ (SImode, operands[1], operands[2]); - else - cmp = gen_rtx_fmt_ee (GET_CODE (operands[0]), SImode, - operands[1], operands[2]); - - emit_insn (gen_cstore4_media (tmp, cmp, operands[1], operands[2])); - - if (GET_CODE (cmp) == GET_CODE (operands[0])) - operands[0] = gen_rtx_NE (VOIDmode, tmp, const0_rtx); - else - operands[0] = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); - operands[1] = tmp; - operands[2] = const0_rtx; - operands[3] = gen_rtx_LABEL_REF (Pmode, operands[3]); -}) - -(define_insn "*beq_media_i" - [(set (pc) - (if_then_else (match_operator 3 "equality_comparison_operator" - [(match_operand:DI 1 "arith_reg_operand" "r,r") - (match_operand:DI 2 "arith_operand" "r,I06")]) - (match_operand 0 "target_operand" "b,b") - (pc)))] - "TARGET_SHMEDIA" - "@ - b%o3%' %1, %2, %0%> - b%o3i%' %1, %2, %0%>" - [(set_attr "type" "cbranch_media")]) - -(define_insn "*beq_media_i32" - [(set (pc) - (if_then_else (match_operator 3 "equality_comparison_operator" - [(match_operand:SI 1 "arith_reg_operand" "r,r") - (match_operand:SI 2 "arith_operand" "r,I06")]) - (match_operand 0 "target_operand" "b,b") - (pc)))] - "TARGET_SHMEDIA" - "@ - b%o3%' %1, %2, %0%> - b%o3i%' %1, %2, %0%>" - [(set_attr "type" "cbranch_media")]) - -(define_insn "*bgt_media_i" - [(set (pc) - (if_then_else (match_operator 3 "greater_comparison_operator" - [(match_operand:DI 1 "arith_reg_or_0_operand" "rN") - (match_operand:DI 2 "arith_reg_or_0_operand" "rN")]) - (match_operand 0 "target_operand" "b") - (pc)))] - "TARGET_SHMEDIA" - "b%o3%' %N1, %N2, %0%>" - [(set_attr "type" "cbranch_media")]) - -(define_insn "*bgt_media_i32" - [(set (pc) - (if_then_else (match_operator 3 "greater_comparison_operator" - [(match_operand:SI 1 "arith_reg_or_0_operand" "rN") - (match_operand:SI 2 "arith_reg_or_0_operand" "rN")]) - (match_operand 0 "target_operand" "b") - (pc)))] - "TARGET_SHMEDIA" - "b%o3%' %N1, %N2, %0%>" - [(set_attr "type" "cbranch_media")]) - -;; These are only needed to make invert_jump() happy - otherwise, jump -;; optimization will be silently disabled. -(define_insn "*blt_media_i" - [(set (pc) - (if_then_else (match_operator 3 "less_comparison_operator" - [(match_operand:DI 1 "arith_reg_or_0_operand" "rN") - (match_operand:DI 2 "arith_reg_or_0_operand" "rN")]) - (match_operand 0 "target_operand" "b") - (pc)))] - "TARGET_SHMEDIA" - "b%o3%' %N2, %N1, %0%>" - [(set_attr "type" "cbranch_media")]) - -(define_insn "*blt_media_i32" - [(set (pc) - (if_then_else (match_operator 3 "less_comparison_operator" - [(match_operand:SI 1 "arith_reg_or_0_operand" "rN") - (match_operand:SI 2 "arith_reg_or_0_operand" "rN")]) - (match_operand 0 "target_operand" "b") - (pc)))] - "TARGET_SHMEDIA" - "b%o3%' %N2, %N1, %0%>" - [(set_attr "type" "cbranch_media")]) - -;; combiner splitter for test-and-branch on single bit in register. This -;; is endian dependent because the non-paradoxical subreg looks different -;; on big endian. -(define_split - [(set (pc) - (if_then_else - (match_operator 3 "equality_comparison_operator" - [(subreg:SI - (zero_extract:DI - (subreg:DI (match_operand:SI 1 "extend_reg_operand" "") 0) - (const_int 1) - (match_operand 2 "const_int_operand" "")) 0) - (const_int 0)]) - (match_operand 0 "target_operand" "") - (pc))) - (clobber (match_operand:SI 4 "arith_reg_dest" ""))] - "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN" - [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 5))) - (set (pc) (if_then_else (match_dup 6) (match_dup 0) (pc)))] -{ - operands[5] = GEN_INT (31 - INTVAL (operands[2])); - operands[6] = (GET_CODE (operands[3]) == EQ - ? gen_rtx_GE (VOIDmode, operands[4], const0_rtx) - : gen_rtx_GT (VOIDmode, const0_rtx, operands[4])); -}) - ; operand 0 is the loop count pseudo register ; operand 1 is the label to jump to at the top of the loop (define_expand "doloop_end" @@ -9490,51 +6485,15 @@ label: [(set_attr "type" "jump") (set_attr "length" "16")]) -;; ??? It would be much saner to explicitly use the scratch register -;; in the jump insn, and have indirect_jump_scratch only set it, -;; but fill_simple_delay_slots would refuse to do delay slot filling -;; from the target then, as it uses simplejump_p. -;;(define_insn "jump_compact_far" -;; [(set (pc) -;; (label_ref (match_operand 0 "" ""))) -;; (use (match_operand 1 "register_operand" "r")] -;; "TARGET_SH1" -;; "* return output_far_jump(insn, operands[0], operands[1]);" -;; [(set_attr "type" "jump") -;; (set_attr "needs_delay_slot" "yes")]) - -(define_insn "jump_media" - [(set (pc) - (match_operand 0 "target_operand" "b"))] - "TARGET_SHMEDIA" - "blink %0, r63%>" - [(set_attr "type" "jump_media")]) - (define_expand "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" { - if (TARGET_SH1) - emit_jump_insn (gen_jump_compact (operands[0])); - else if (TARGET_SHMEDIA) - { - if (reload_in_progress || reload_completed) - FAIL; - emit_jump_insn (gen_jump_media (gen_rtx_LABEL_REF (Pmode, operands[0]))); - } + emit_jump_insn (gen_jump_compact (operands[0])); DONE; }) -(define_insn "force_mode_for_call" - [(use (reg:SI FPSCR_MODES_REG))] - "TARGET_SHCOMPACT" - "" - [(set_attr "length" "0") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double")))]) - (define_insn "calli" [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) (match_operand 1 "" "")) @@ -9642,47 +6601,6 @@ label: (set_attr "needs_delay_slot" "yes") (set_attr "fp_set" "unknown")]) -(define_insn "call_compact" - [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) - (match_operand 1 "" "")) - (match_operand 2 "immediate_operand" "n") - (use (reg:SI R0_REG)) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))" - "jsr @%0%#" - [(set_attr "type" "call") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double"))) - (set_attr "needs_delay_slot" "yes")]) - -(define_insn "call_compact_rettramp" - [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) - (match_operand 1 "" "")) - (match_operand 2 "immediate_operand" "n") - (use (reg:SI R0_REG)) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - (clobber (reg:SI R10_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))" - "jsr @%0%#" - [(set_attr "type" "call") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double"))) - (set_attr "needs_delay_slot" "yes")]) - -(define_insn "call_media" - [(call (mem:DI (match_operand 0 "target_reg_operand" "b")) - (match_operand 1 "" "")) - (clobber (reg:DI PR_MEDIA_REG))] - "TARGET_SHMEDIA" - "blink %0, r18" - [(set_attr "type" "jump_media")]) - (define_insn "call_valuei" [(set (match_operand 0 "" "=rf") (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) @@ -9795,50 +6713,6 @@ label: (set_attr "needs_delay_slot" "yes") (set_attr "fp_set" "unknown")]) -(define_insn "call_value_compact" - [(set (match_operand 0 "" "=rf") - (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) - (match_operand 2 "" ""))) - (match_operand 3 "immediate_operand" "n") - (use (reg:SI R0_REG)) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))" - "jsr @%1%#" - [(set_attr "type" "call") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double"))) - (set_attr "needs_delay_slot" "yes")]) - -(define_insn "call_value_compact_rettramp" - [(set (match_operand 0 "" "=rf") - (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) - (match_operand 2 "" ""))) - (match_operand 3 "immediate_operand" "n") - (use (reg:SI R0_REG)) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - (clobber (reg:SI R10_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))" - "jsr @%1%#" - [(set_attr "type" "call") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double"))) - (set_attr "needs_delay_slot" "yes")]) - -(define_insn "call_value_media" - [(set (match_operand 0 "" "=rf") - (call (mem:DI (match_operand 1 "target_reg_operand" "b")) - (match_operand 2 "" ""))) - (clobber (reg:DI PR_MEDIA_REG))] - "TARGET_SHMEDIA" - "blink %1, r18" - [(set_attr "type" "jump_media")]) - (define_expand "call" [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" "")) (match_operand 1 "" "")) @@ -9853,65 +6727,6 @@ label: emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); } - if (TARGET_SHMEDIA) - { - operands[0] = shmedia_prepare_call_address (operands[0], 0); - emit_call_insn (gen_call_media (operands[0], operands[1])); - DONE; - } - else if (TARGET_SHCOMPACT && operands[2] && INTVAL (operands[2])) - { - rtx cookie_rtx = operands[2]; - long cookie = INTVAL (cookie_rtx); - rtx func = XEXP (operands[0], 0); - rtx r0, r1; - - if (flag_pic) - { - if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func)) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOTPLT2reg (reg, func)); - func = reg; - } - else - func = legitimize_pic_address (func, Pmode, 0); - } - - r0 = gen_rtx_REG (SImode, R0_REG); - r1 = gen_rtx_REG (SImode, R1_REG); - - /* Since such a call function may use all call-clobbered - registers, we force a mode switch earlier, so that we don't - run out of registers when adjusting fpscr for the call. */ - emit_insn (gen_force_mode_for_call ()); - - operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", - SFUNC_GOT).sym; - operands[0] = force_reg (SImode, operands[0]); - - emit_move_insn (r0, func); - emit_move_insn (r1, cookie_rtx); - - if (cookie & CALL_COOKIE_RET_TRAMP (1)) - emit_call_insn (gen_call_compact_rettramp (operands[0], operands[1], - operands[2])); - else - emit_call_insn (gen_call_compact (operands[0], operands[1], - operands[2])); - - DONE; - } - else if (TARGET_SHCOMPACT && flag_pic - && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF - && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0))) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[0], 0))); - XEXP (operands[0], 0) = reg; - } if (!flag_pic && TARGET_SH2A && MEM_P (operands[0]) && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) @@ -9946,98 +6761,6 @@ label: DONE; }) -(define_insn "call_pop_compact" - [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) - (match_operand 1 "" "")) - (match_operand 2 "immediate_operand" "n") - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand 3 "immediate_operand" "n"))) - (use (reg:SI R0_REG)) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT && ! (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))" - "jsr @%0%#" - [(set_attr "type" "call") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double"))) - (set_attr "needs_delay_slot" "yes")]) - -(define_insn "call_pop_compact_rettramp" - [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) - (match_operand 1 "" "")) - (match_operand 2 "immediate_operand" "n") - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand 3 "immediate_operand" "n"))) - (use (reg:SI R0_REG)) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - (clobber (reg:SI R10_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT && (INTVAL (operands[2]) & CALL_COOKIE_RET_TRAMP (1))" - "jsr @%0%#" - [(set_attr "type" "call") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double"))) - (set_attr "needs_delay_slot" "yes")]) - -(define_expand "call_pop" - [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" "")) - (match_operand 1 "" "")) - (match_operand 2 "" "") - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand 3 "" "")))])] - "TARGET_SHCOMPACT" -{ - rtx cookie_rtx; - long cookie; - rtx func; - rtx r0, r1; - - gcc_assert (operands[2] && INTVAL (operands[2])); - cookie_rtx = operands[2]; - cookie = INTVAL (cookie_rtx); - func = XEXP (operands[0], 0); - - if (flag_pic) - { - if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func)) - { - rtx reg = gen_reg_rtx (Pmode); - emit_insn (gen_symGOTPLT2reg (reg, func)); - func = reg; - } - else - func = legitimize_pic_address (func, Pmode, 0); - } - - r0 = gen_rtx_REG (SImode, R0_REG); - r1 = gen_rtx_REG (SImode, R1_REG); - - /* Since such a call function may use all call-clobbered - registers, we force a mode switch earlier, so that we don't - run out of registers when adjusting fpscr for the call. */ - emit_insn (gen_force_mode_for_call ()); - - operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", - SFUNC_GOT).sym; - operands[0] = force_reg (SImode, operands[0]); - - emit_move_insn (r0, func); - emit_move_insn (r1, cookie_rtx); - - if (cookie & CALL_COOKIE_RET_TRAMP (1)) - emit_call_insn (gen_call_pop_compact_rettramp - (operands[0], operands[1], operands[2], operands[3])); - else - emit_call_insn (gen_call_pop_compact - (operands[0], operands[1], operands[2], operands[3])); - - DONE; -}) - (define_expand "call_value" [(parallel [(set (match_operand 0 "arith_reg_operand" "") (call (mem:SI (match_operand 1 "arith_reg_operand" "")) @@ -10053,68 +6776,6 @@ label: emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); } - if (TARGET_SHMEDIA) - { - operands[1] = shmedia_prepare_call_address (operands[1], 0); - emit_call_insn (gen_call_value_media (operands[0], operands[1], - operands[2])); - DONE; - } - else if (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3])) - { - rtx cookie_rtx = operands[3]; - long cookie = INTVAL (cookie_rtx); - rtx func = XEXP (operands[1], 0); - rtx r0, r1; - - if (flag_pic) - { - if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func)) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOTPLT2reg (reg, func)); - func = reg; - } - else - func = legitimize_pic_address (func, Pmode, 0); - } - - r0 = gen_rtx_REG (SImode, R0_REG); - r1 = gen_rtx_REG (SImode, R1_REG); - - /* Since such a call function may use all call-clobbered - registers, we force a mode switch earlier, so that we don't - run out of registers when adjusting fpscr for the call. */ - emit_insn (gen_force_mode_for_call ()); - - operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", - SFUNC_GOT).sym; - operands[1] = force_reg (SImode, operands[1]); - - emit_move_insn (r0, func); - emit_move_insn (r1, cookie_rtx); - - if (cookie & CALL_COOKIE_RET_TRAMP (1)) - emit_call_insn (gen_call_value_compact_rettramp (operands[0], - operands[1], - operands[2], - operands[3])); - else - emit_call_insn (gen_call_value_compact (operands[0], operands[1], - operands[2], operands[3])); - - DONE; - } - else if (TARGET_SHCOMPACT && flag_pic - && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF - && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0))) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOTPLT2reg (reg, XEXP (operands[1], 0))); - XEXP (operands[1], 0) = reg; - } if (!flag_pic && TARGET_SH2A && MEM_P (operands[1]) && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) @@ -10278,41 +6939,6 @@ label: (const_string "single") (const_string "double"))) (set_attr "type" "jump_ind")]) -(define_insn "sibcall_compact" - [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k")) - (match_operand 1 "" "")) - (return) - (use (match_operand:SI 2 "register_operand" "z,x")) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - ;; We want to make sure the `x' above will only match MACH_REG - ;; because sibcall_epilogue may clobber MACL_REG. - (clobber (reg:SI MACL_REG))] - "TARGET_SHCOMPACT" -{ - static const char* alt[] = - { - "jmp @%0%#", - - "jmp @%0" "\n" - " sts %2,r0" - }; - return alt[which_alternative]; -} - [(set_attr "needs_delay_slot" "yes,no") - (set_attr "length" "2,4") - (set (attr "fp_mode") (const_string "single")) - (set_attr "type" "jump_ind")]) - -(define_insn "sibcall_media" - [(call (mem:DI (match_operand 0 "target_reg_operand" "k")) - (match_operand 1 "" "")) - (use (reg:SI PR_MEDIA_REG)) - (return)] - "TARGET_SHMEDIA" - "blink %0, r63" - [(set_attr "type" "jump_media")]) - (define_expand "sibcall" [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" "")) @@ -10328,77 +6954,6 @@ label: emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); } - if (TARGET_SHMEDIA) - { - operands[0] = shmedia_prepare_call_address (operands[0], 1); - emit_call_insn (gen_sibcall_media (operands[0], operands[1])); - DONE; - } - else if (TARGET_SHCOMPACT && operands[2] - && (INTVAL (operands[2]) & ~ CALL_COOKIE_RET_TRAMP (1))) - { - rtx cookie_rtx = operands[2]; - long cookie = INTVAL (cookie_rtx); - rtx func = XEXP (operands[0], 0); - rtx mach, r1; - - if (flag_pic) - { - if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func)) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOT2reg (reg, func)); - func = reg; - } - else - func = legitimize_pic_address (func, Pmode, 0); - } - - /* FIXME: if we could tell whether all argument registers are - already taken, we could decide whether to force the use of - MACH_REG or to stick to R0_REG. Unfortunately, there's no - simple way to tell. We could use the CALL_COOKIE, but we - can't currently tell a register used for regular argument - passing from one that is unused. If we leave it up to reload - to decide which register to use, it seems to always choose - R0_REG, which leaves no available registers in SIBCALL_REGS - to hold the address of the trampoline. */ - mach = gen_rtx_REG (SImode, MACH_REG); - r1 = gen_rtx_REG (SImode, R1_REG); - - /* Since such a call function may use all call-clobbered - registers, we force a mode switch earlier, so that we don't - run out of registers when adjusting fpscr for the call. */ - emit_insn (gen_force_mode_for_call ()); - - operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", - SFUNC_GOT).sym; - operands[0] = force_reg (SImode, operands[0]); - - /* We don't need a return trampoline, since the callee will - return directly to the upper caller. */ - if (cookie & CALL_COOKIE_RET_TRAMP (1)) - { - cookie &= ~ CALL_COOKIE_RET_TRAMP (1); - cookie_rtx = GEN_INT (cookie); - } - - emit_move_insn (mach, func); - emit_move_insn (r1, cookie_rtx); - - emit_call_insn (gen_sibcall_compact (operands[0], operands[1], mach)); - DONE; - } - else if (TARGET_SHCOMPACT && flag_pic - && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF - && ! SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0))) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOT2reg (reg, XEXP (operands[0], 0))); - XEXP (operands[0], 0) = reg; - } if (flag_pic && TARGET_SH2 && MEM_P (operands[0]) && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF @@ -10561,43 +7116,6 @@ label: (const_string "single") (const_string "double"))) (set_attr "type" "jump_ind")]) -(define_insn "sibcall_value_compact" - [(set (match_operand 0 "" "=rf,rf") - (call (mem:SI (match_operand:SI 1 "register_operand" "k,k")) - (match_operand 2 "" ""))) - (return) - (use (match_operand:SI 3 "register_operand" "z,x")) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - ;; We want to make sure the `x' above will only match MACH_REG - ;; because sibcall_epilogue may clobber MACL_REG. - (clobber (reg:SI MACL_REG))] - "TARGET_SHCOMPACT" -{ - static const char* alt[] = - { - "jmp @%1%#", - - "jmp @%1" "\n" - " sts %3,r0" - }; - return alt[which_alternative]; -} - [(set_attr "needs_delay_slot" "yes,no") - (set_attr "length" "2,4") - (set (attr "fp_mode") (const_string "single")) - (set_attr "type" "jump_ind")]) - -(define_insn "sibcall_value_media" - [(set (match_operand 0 "" "=rf") - (call (mem:DI (match_operand 1 "target_reg_operand" "k")) - (match_operand 2 "" ""))) - (use (reg:SI PR_MEDIA_REG)) - (return)] - "TARGET_SHMEDIA" - "blink %1, r63" - [(set_attr "type" "jump_media")]) - (define_expand "sibcall_value" [(parallel [(set (match_operand 0 "arith_reg_operand" "") @@ -10614,79 +7132,6 @@ label: emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); } - if (TARGET_SHMEDIA) - { - operands[1] = shmedia_prepare_call_address (operands[1], 1); - emit_call_insn (gen_sibcall_value_media (operands[0], operands[1], - operands[2])); - DONE; - } - else if (TARGET_SHCOMPACT && operands[3] - && (INTVAL (operands[3]) & ~ CALL_COOKIE_RET_TRAMP (1))) - { - rtx cookie_rtx = operands[3]; - long cookie = INTVAL (cookie_rtx); - rtx func = XEXP (operands[1], 0); - rtx mach, r1; - - if (flag_pic) - { - if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func)) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOT2reg (reg, func)); - func = reg; - } - else - func = legitimize_pic_address (func, Pmode, 0); - } - - /* FIXME: if we could tell whether all argument registers are - already taken, we could decide whether to force the use of - MACH_REG or to stick to R0_REG. Unfortunately, there's no - simple way to tell. We could use the CALL_COOKIE, but we - can't currently tell a register used for regular argument - passing from one that is unused. If we leave it up to reload - to decide which register to use, it seems to always choose - R0_REG, which leaves no available registers in SIBCALL_REGS - to hold the address of the trampoline. */ - mach = gen_rtx_REG (SImode, MACH_REG); - r1 = gen_rtx_REG (SImode, R1_REG); - - /* Since such a call function may use all call-clobbered - registers, we force a mode switch earlier, so that we don't - run out of registers when adjusting fpscr for the call. */ - emit_insn (gen_force_mode_for_call ()); - - operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", - SFUNC_GOT).sym; - operands[1] = force_reg (SImode, operands[1]); - - /* We don't need a return trampoline, since the callee will - return directly to the upper caller. */ - if (cookie & CALL_COOKIE_RET_TRAMP (1)) - { - cookie &= ~ CALL_COOKIE_RET_TRAMP (1); - cookie_rtx = GEN_INT (cookie); - } - - emit_move_insn (mach, func); - emit_move_insn (r1, cookie_rtx); - - emit_call_insn (gen_sibcall_value_compact (operands[0], operands[1], - operands[2], mach)); - DONE; - } - else if (TARGET_SHCOMPACT && flag_pic - && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF - && ! SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0))) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOT2reg (reg, XEXP (operands[1], 0))); - XEXP (operands[1], 0) = reg; - } if (flag_pic && TARGET_SH2 && MEM_P (operands[1]) && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF @@ -10719,133 +7164,11 @@ label: DONE; }) -(define_insn "call_value_pop_compact" - [(set (match_operand 0 "" "=rf") - (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) - (match_operand 2 "" ""))) - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand 4 "immediate_operand" "n"))) - (match_operand 3 "immediate_operand" "n") - (use (reg:SI R0_REG)) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT && ! (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))" - "jsr @%1%#" - [(set_attr "type" "call") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double"))) - (set_attr "needs_delay_slot" "yes")]) - -(define_insn "call_value_pop_compact_rettramp" - [(set (match_operand 0 "" "=rf") - (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) - (match_operand 2 "" ""))) - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand 4 "immediate_operand" "n"))) - (match_operand 3 "immediate_operand" "n") - (use (reg:SI R0_REG)) - (use (reg:SI R1_REG)) - (use (reg:SI FPSCR_MODES_REG)) - (clobber (reg:SI R10_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT && (INTVAL (operands[3]) & CALL_COOKIE_RET_TRAMP (1))" - "jsr @%1%#" - [(set_attr "type" "call") - (set (attr "fp_mode") - (if_then_else (eq_attr "fpu_single" "yes") - (const_string "single") (const_string "double"))) - (set_attr "needs_delay_slot" "yes")]) - -(define_expand "call_value_pop" - [(parallel [(set (match_operand 0 "arith_reg_operand" "") - (call (mem:SI (match_operand 1 "arith_reg_operand" "")) - (match_operand 2 "" ""))) - (match_operand 3 "" "") - (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand 4 "" "")))])] - "TARGET_SHCOMPACT" -{ - rtx cookie_rtx; - long cookie; - rtx func; - rtx r0, r1; - - gcc_assert (TARGET_SHCOMPACT && operands[3] && INTVAL (operands[3])); - cookie_rtx = operands[3]; - cookie = INTVAL (cookie_rtx); - func = XEXP (operands[1], 0); - - if (flag_pic) - { - if (GET_CODE (func) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P (func)) - { - rtx reg = gen_reg_rtx (Pmode); - - emit_insn (gen_symGOTPLT2reg (reg, func)); - func = reg; - } - else - func = legitimize_pic_address (func, Pmode, 0); - } - - r0 = gen_rtx_REG (SImode, R0_REG); - r1 = gen_rtx_REG (SImode, R1_REG); - - /* Since such a call function may use all call-clobbered - registers, we force a mode switch earlier, so that we don't - run out of registers when adjusting fpscr for the call. */ - emit_insn (gen_force_mode_for_call ()); - - operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", - SFUNC_GOT).sym; - operands[1] = force_reg (SImode, operands[1]); - - emit_move_insn (r0, func); - emit_move_insn (r1, cookie_rtx); - - if (cookie & CALL_COOKIE_RET_TRAMP (1)) - emit_call_insn (gen_call_value_pop_compact_rettramp - (operands[0], operands[1], operands[2], - operands[3], operands[4])); - else - emit_call_insn (gen_call_value_pop_compact - (operands[0], operands[1], operands[2], - operands[3], operands[4])); - - DONE; -}) - (define_expand "sibcall_epilogue" [(return)] "" { sh_expand_epilogue (true); - if (TARGET_SHCOMPACT) - { - rtx_insn *insn; - rtx set; - - /* If epilogue clobbers r0, preserve it in macl. */ - for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) - if ((set = single_set (insn)) - && REG_P (SET_DEST (set)) - && REGNO (SET_DEST (set)) == R0_REG) - { - rtx r0 = gen_rtx_REG (SImode, R0_REG); - rtx tmp = gen_rtx_REG (SImode, MACL_REG); - - /* We can't tell at this point whether the sibcall is a - sibcall_compact and, if it is, whether it uses r0 or - mach as operand 2, so let the instructions that - preserve r0 be optimized away if r0 turns out to be - dead. */ - emit_insn_before (gen_rtx_SET (tmp, r0), insn); - emit_move_insn (r0, tmp); - break; - } - } DONE; }) @@ -10891,13 +7214,6 @@ label: [(set_attr "needs_delay_slot" "yes") (set_attr "type" "jump_ind")]) -(define_insn "casesi_jump_media" - [(set (pc) (match_operand 0 "target_reg_operand" "b")) - (use (label_ref (match_operand 1 "" "")))] - "TARGET_SHMEDIA" - "blink %0, r63" - [(set_attr "type" "jump_media")]) - ;; Call subroutine returning any type. ;; ??? This probably doesn't work. (define_expand "untyped_call" @@ -10905,19 +7221,13 @@ label: (const_int 0)) (match_operand 1 "" "") (match_operand 2 "" "")])] - "(TARGET_SH2E || TARGET_SH2A) || TARGET_SHMEDIA" + "TARGET_SH2E || TARGET_SH2A" { - if (! TARGET_SHMEDIA) - { - /* RA does not know that the call sets the function value registers. - We avoid problems by claiming that those registers are clobbered - at this point. */ - for (int i = 0; i < XVECLEN (operands[2], 0); i++) - { - rtx set = XVECEXP (operands[2], 0, i); - emit_clobber (SET_SRC (set)); - } - } + /* RA does not know that the call sets the function value registers. + We avoid problems by claiming that those registers are clobbered + at this point. */ + for (int i = 0; i < XVECLEN (operands[2], 0); i++) + emit_clobber (SET_SRC (XVECEXP (operands[2], 0, i))); emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); @@ -11006,36 +7316,6 @@ label: operands[1] = gen_rtx_REG (Pmode, PIC_REG); operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); - - if (TARGET_SHMEDIA) - { - rtx tr = gen_rtx_REG (Pmode, TR0_REG); - rtx pic = operands[1]; - rtx lab = PATTERN (gen_call_site ()); - rtx insn, equiv; - - equiv = operands[2]; - operands[2] = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[2], lab), - UNSPEC_PCREL_SYMOFF); - operands[2] = gen_rtx_CONST (Pmode, operands[2]); - - if (Pmode == SImode) - { - emit_insn (gen_movsi_const (pic, operands[2])); - emit_insn (gen_ptrel_si (tr, pic, copy_rtx (lab))); - } - else - { - emit_insn (gen_movdi_const (pic, operands[2])); - emit_insn (gen_ptrel_di (tr, pic, copy_rtx (lab))); - } - - insn = emit_move_insn (operands[1], tr); - - set_unique_reg_note (insn, REG_EQUAL, equiv); - - DONE; - } }) ;; A helper for GOTaddr2picreg to finish up the initialization of the @@ -11052,34 +7332,6 @@ label: (reg:SI R0_REG))))] "TARGET_VXWORKS_RTP") -(define_insn "*ptb" - [(set (match_operand 0 "target_reg_operand" "=b") - (const (unspec [(match_operand 1 "" "Csy")] - UNSPEC_DATALABEL)))] - "TARGET_SHMEDIA && flag_pic - && satisfies_constraint_Csy (operands[1])" - "ptb/u datalabel %1, %0" - [(set_attr "type" "ptabs_media") - (set_attr "length" "*")]) - -(define_insn "ptrel_si" - [(set (match_operand:SI 0 "target_reg_operand" "=b") - (plus:SI (match_operand:SI 1 "register_operand" "r") - (pc))) - (match_operand:SI 2 "" "")] - "TARGET_SHMEDIA" - "%O2: ptrel/u %1, %0" - [(set_attr "type" "ptabs_media")]) - -(define_insn "ptrel_di" - [(set (match_operand:DI 0 "target_reg_operand" "=b") - (plus:DI (match_operand:DI 1 "register_operand" "r") - (pc))) - (match_operand:DI 2 "" "")] - "TARGET_SHMEDIA" - "%O2: ptrel/u %1, %0" - [(set_attr "type" "ptabs_media")]) - (define_expand "builtin_setjmp_receiver" [(match_operand 0 "" "")] "flag_pic" @@ -11145,7 +7397,7 @@ label: operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); - if (!TARGET_SHMEDIA && !TARGET_FDPIC + if (!TARGET_FDPIC && flag_stack_protect && GET_CODE (operands[1]) == CONST && GET_CODE (XEXP (operands[1], 0)) == UNSPEC @@ -11154,27 +7406,7 @@ label: "__stack_chk_guard") == 0) stack_chk_guard_p = true; - if (TARGET_SHMEDIA) - { - rtx reg = operands[2]; - - if (Pmode == DImode) - { - if (flag_pic > 1) - emit_insn (gen_movdi_const_32bit (reg, operands[1])); - else - emit_insn (gen_movdi_const_16bit (reg, operands[1])); - } - else - { - if (flag_pic > 1) - emit_insn (gen_movsi_const (reg, operands[1])); - else - emit_insn (gen_movsi_const_16bit (reg, operands[1])); - } - } - else - emit_move_insn (operands[2], operands[1]); + emit_move_insn (operands[2], operands[1]); /* When stack protector inserts codes after the result is set to R0, @(rX, r12) will cause a spill failure for R0. Use a unspec @@ -11661,43 +7893,7 @@ label: { rtx reg = gen_reg_rtx (SImode); rtx reg2 = gen_reg_rtx (SImode); - if (TARGET_SHMEDIA) - { - rtx reg = gen_reg_rtx (DImode); - rtx reg2 = gen_reg_rtx (DImode); - rtx reg3 = gen_reg_rtx (Pmode); - rtx reg4 = gen_reg_rtx (Pmode); - rtx reg5 = gen_reg_rtx (Pmode); - rtx load, test; - - operands[0] = convert_modes (DImode, SImode, operands[0], 0); - operands[1] = convert_modes (DImode, SImode, operands[1], 0); - operands[2] = convert_modes (DImode, SImode, operands[2], 1); - - test = gen_rtx_GT (VOIDmode, operands[1], operands[0]); - emit_jump_insn (gen_cbranchdi4 (test, operands[1], operands[0], - operands[4])); - emit_move_insn (reg, gen_rtx_MINUS (DImode, operands[0], operands[1])); - test = gen_rtx_GTU (VOIDmode, reg, operands[2]); - emit_jump_insn (gen_cbranchdi4 (test, reg, operands[2], operands[4])); - emit_insn (gen_casesi_shift_media (reg2, reg, operands[3])); - emit_move_insn (reg3, gen_datalabel_ref (gen_rtx_LABEL_REF - (Pmode, operands[3]))); - /* Messy: can we subreg to clean this up? */ - if (Pmode == DImode) - load = gen_casesi_load_media (reg4, reg3, reg2, operands[3]); - else - load = gen_casesi_load_media (reg4, - gen_rtx_SUBREG (DImode, reg3, 0), - reg2, operands[3]); - PUT_MODE (SET_SRC (load), Pmode); - emit_insn (load); - /* ??? The following add could be eliminated if we used ptrel. */ - emit_move_insn (reg5, gen_rtx_PLUS (Pmode, reg3, reg4)); - emit_jump_insn (gen_casesi_jump_media (reg5, operands[3])); - emit_barrier (); - DONE; - } + operands[1] = copy_to_mode_reg (SImode, operands[1]); operands[2] = copy_to_mode_reg (SImode, operands[2]); /* If optimizing, casesi_worker depends on the mode of the instruction @@ -11861,91 +8057,17 @@ label: } [(set_attr "length" "8")]) -(define_insn "casesi_shift_media" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r") - (unspec:DI [(label_ref:DI (match_operand 2 "" ""))] - UNSPEC_CASESI)))] - "TARGET_SHMEDIA" -{ - rtx diff_vec = PATTERN (NEXT_INSN (as_a (operands[2]))); - - gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); - - switch (GET_MODE (diff_vec)) - { - case SImode: - return "shlli %1, 2, %0"; - case HImode: - return "shlli %1, 1, %0"; - case QImode: - if (rtx_equal_p (operands[0], operands[1])) - return ""; - return "add %1, r63, %0"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "arith_media")]) - -(define_insn "casesi_load_media" - [(set (match_operand 0 "any_arith_reg_dest" "=r") - (mem (unspec [(match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "arith_reg_operand" "r") - (label_ref:DI (match_operand 3 "" ""))] UNSPEC_CASESI)))] - "TARGET_SHMEDIA" -{ - rtx diff_vec = PATTERN (NEXT_INSN (as_a (operands[3]))); - - gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); - - switch (GET_MODE (diff_vec)) - { - case SImode: - return "ldx.l %1, %2, %0"; - case HImode: -#if 0 - if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) - return "ldx.uw %1, %2, %0"; -#endif - return "ldx.w %1, %2, %0"; - case QImode: - if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) - return "ldx.ub %1, %2, %0"; - return "ldx.b %1, %2, %0"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "load_media")]) - (define_expand "simple_return" [(simple_return)] "sh_can_use_simple_return_p ()") (define_expand "return" [(return)] - "reload_completed && epilogue_completed" -{ - if (TARGET_SHMEDIA) - { - emit_jump_insn (gen_return_media ()); - DONE; - } - - if (TARGET_SHCOMPACT - && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))) - { - emit_jump_insn (gen_shcompact_return_tramp ()); - DONE; - } -}) + "reload_completed && epilogue_completed") (define_insn "*_i" [(any_return)] - "TARGET_SH1 && ! (TARGET_SHCOMPACT - && (crtl->args.info.call_cookie - & CALL_COOKIE_RET_TRAMP (1))) + "TARGET_SH1 && reload_completed && ! sh_cfun_trap_exit_p ()" { @@ -11961,110 +8083,10 @@ label: ;; trapa has no delay slot. (define_insn "*return_trapa" [(return)] - "TARGET_SH1 && !TARGET_SHCOMPACT - && reload_completed" + "TARGET_SH1 && reload_completed" "%@" [(set_attr "type" "return")]) -(define_expand "shcompact_return_tramp" - [(return)] - "TARGET_SHCOMPACT - && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))" -{ - rtx reg = gen_rtx_REG (Pmode, R0_REG); - - function_symbol (reg, "__GCC_shcompact_return_trampoline", SFUNC_STATIC); - emit_jump_insn (gen_shcompact_return_tramp_i ()); - DONE; -}) - -(define_insn "shcompact_return_tramp_i" - [(parallel [(return) (use (reg:SI R0_REG))])] - "TARGET_SHCOMPACT - && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1))" - "jmp @r0%#" - [(set_attr "type" "jump_ind") - (set_attr "needs_delay_slot" "yes")]) - -(define_insn "return_media_i" - [(parallel [(return) (use (match_operand 0 "target_reg_operand" "k"))])] - "TARGET_SHMEDIA && reload_completed" - "blink %0, r63" - [(set_attr "type" "jump_media")]) - -(define_insn "return_media_rte" - [(return)] - "TARGET_SHMEDIA && reload_completed && current_function_interrupt" - "rte" - [(set_attr "type" "jump_media")]) - -(define_expand "return_media" - [(return)] - "TARGET_SHMEDIA && reload_completed" -{ - int tr_regno = sh_media_register_for_return (); - rtx tr; - - if (current_function_interrupt) - { - emit_jump_insn (gen_return_media_rte ()); - DONE; - } - if (tr_regno < 0) - { - rtx r18 = gen_rtx_REG (Pmode, PR_MEDIA_REG); - - gcc_assert (call_really_used_regs[TR0_REG] && !fixed_regs[TR0_REG]); - tr_regno = TR0_REG; - tr = gen_rtx_REG (Pmode, tr_regno); - emit_move_insn (tr, r18); - } - else - tr = gen_rtx_REG (Pmode, tr_regno); - - emit_jump_insn (gen_return_media_i (tr)); - DONE; -}) - -(define_insn "shcompact_preserve_incoming_args" - [(set (match_operand:SI 0 "register_operand" "+r") - (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))] - "TARGET_SHCOMPACT" - "" - [(set_attr "length" "0")]) - -(define_insn "shcompact_incoming_args" - [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS)) - (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS)) - (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS)) - (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS)) - (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS)) - (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS)) - (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS)) - (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS)) - (set (mem:BLK (reg:SI MACL_REG)) - (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS)) - (use (reg:SI R0_REG)) - (clobber (reg:SI R0_REG)) - (clobber (reg:SI MACL_REG)) - (clobber (reg:SI MACH_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT" - "jsr @r0%#" - [(set_attr "needs_delay_slot" "yes")]) - -(define_insn "shmedia_save_restore_regs_compact" - [(set (reg:SI SP_REG) - (plus:SI (reg:SI SP_REG) - (match_operand:SI 0 "immediate_operand" "i"))) - (use (reg:SI R0_REG)) - (clobber (reg:SI PR_REG))] - "TARGET_SHCOMPACT - && (INTVAL (operands[0]) == SHMEDIA_REGS_STACK_ADJUST () - || INTVAL (operands[0]) == - SHMEDIA_REGS_STACK_ADJUST ())" - "jsr @r0%#" - [(set_attr "needs_delay_slot" "yes")]) - (define_expand "prologue" [(const_int 0)] "" @@ -12078,26 +8100,13 @@ label: "" { sh_expand_epilogue (false); - if (TARGET_SHMEDIA - || (TARGET_SHCOMPACT - && (crtl->args.info.call_cookie & CALL_COOKIE_RET_TRAMP (1)))) - { - emit_jump_insn (gen_return ()); - DONE; - } }) (define_expand "eh_return" [(use (match_operand 0 "register_operand" ""))] "" { - rtx ra = operands[0]; - - if (TARGET_SHMEDIA64) - emit_insn (gen_eh_set_ra_di (ra)); - else - emit_insn (gen_eh_set_ra_si (ra)); - + emit_insn (gen_eh_set_ra_si (operands[0])); DONE; }) @@ -12108,14 +8117,7 @@ label: [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] UNSPECV_EH_RETURN) (clobber (match_scratch:SI 1 "=&r"))] - "! TARGET_SHMEDIA64" - "#") - -(define_insn "eh_set_ra_di" - [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] - UNSPECV_EH_RETURN) - (clobber (match_scratch:DI 1 "=&r"))] - "TARGET_SHMEDIA64" + "" "#") (define_split @@ -12186,95 +8188,13 @@ label: "movrt %0" [(set_attr "type" "arith")]) -(define_expand "cstore4_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator:SI 1 "sh_float_comparison_operator" - [(match_operand 2 "logical_operand" "") - (match_operand 3 "cmp_operand" "")]))] - "TARGET_SHMEDIA" -{ - machine_mode mode = GET_MODE (operands[2]); - enum rtx_code code = GET_CODE (operands[1]); - bool invert, swap; - if (mode == VOIDmode) - mode = GET_MODE (operands[3]); - if (operands[2] == const0_rtx) - { - if (code == EQ || code == NE) - operands[2] = operands[3], operands[3] = const0_rtx; - } - else - operands[2] = force_reg (mode, operands[2]); - if (operands[3] != const0_rtx) - operands[3] = force_reg (mode, operands[3]); - - switch (code) - { - case GEU: - case GE: - swap = invert = !FLOAT_MODE_P (mode); - break; - - case LEU: - case LE: - swap = FLOAT_MODE_P (mode), invert = !swap; - break; - - case LTU: - case LT: - swap = true, invert = false; - break; - - case GTU: - case GT: - case EQ: - case UNORDERED: - swap = invert = false; - break; - - case NE: - swap = invert = true; - break; - - default: - gcc_unreachable (); - } - - if (swap) - { - std::swap (operands[2], operands[3]); - code = swap_condition (code); - } - - if (invert) - { - rtx tem = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0]; - code = reverse_condition (code); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]); - emit_insn (gen_cstore4_media (tem, operands[1], - operands[2], operands[3])); - code = EQ; - operands[2] = tem; - operands[3] = const0_rtx; - } - - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, operands[2], operands[3]); -}) - (define_expand "cstoresi4" [(set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 1 "comparison_operator" [(match_operand:SI 2 "cmpsi_operand" "") (match_operand:SI 3 "arith_operand" "")]))] - "TARGET_SH1 || TARGET_SHMEDIA" + "TARGET_SH1" { - if (TARGET_SHMEDIA) - { - emit_insn (gen_cstore4_media (operands[0], operands[1], - operands[2], operands[3])); - DONE; - } - if (sh_expand_t_scc (operands)) DONE; @@ -12290,15 +8210,8 @@ label: (match_operator:SI 1 "comparison_operator" [(match_operand:DI 2 "arith_operand" "") (match_operand:DI 3 "arith_operand" "")]))] - "TARGET_SH2 || TARGET_SHMEDIA" + "TARGET_SH2" { - if (TARGET_SHMEDIA) - { - emit_insn (gen_cstore4_media (operands[0], operands[1], - operands[2], operands[3])); - DONE; - } - if (sh_expand_t_scc (operands)) DONE; @@ -12662,18 +8575,11 @@ label: (define_expand "cstoresf4" [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator:SI 1 "sh_float_comparison_operator" + (match_operator:SI 1 "ordered_comparison_operator" [(match_operand:SF 2 "arith_operand" "") (match_operand:SF 3 "arith_operand" "")]))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" + "TARGET_SH2E" { - if (TARGET_SHMEDIA) - { - emit_insn (gen_cstore4_media (operands[0], operands[1], - operands[2], operands[3])); - DONE; - } - if (! currently_expanding_to_rtl) FAIL; @@ -12683,18 +8589,11 @@ label: (define_expand "cstoredf4" [(set (match_operand:SI 0 "register_operand" "=r") - (match_operator:SI 1 "sh_float_comparison_operator" + (match_operator:SI 1 "ordered_comparison_operator" [(match_operand:DF 2 "arith_operand" "") (match_operand:DF 3 "arith_operand" "")]))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SHMEDIA) - { - emit_insn (gen_cstore4_media (operands[0], operands[1], - operands[2], operands[3])); - DONE; - } - if (! currently_expanding_to_rtl) FAIL; @@ -13036,7 +8935,7 @@ label: (clobber (reg:SI R4_REG)) (clobber (reg:SI R5_REG)) (clobber (reg:SI R0_REG))])] - "TARGET_SH1 && ! TARGET_SH5" + "TARGET_SH1" { if (expand_block_move (operands)) DONE; @@ -13292,106 +9191,13 @@ label: [(set (match_operand:SF 0 "fp_arith_reg_operand") (plus:SF (match_operand:SF 1 "fp_arith_reg_operand") (match_operand:SF 2 "fp_arith_reg_operand")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" + "TARGET_SH2E" { - if (TARGET_SH2E) - { - emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "*addsf3_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fadd.s %1, %2, %0" - [(set_attr "type" "fparith_media")]) - -(define_insn_and_split "unary_sf_op" - [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f") - (vec_select:V2SF - (vec_concat:V2SF - (vec_select:SF - (match_dup 0) - (parallel [(not:BI (match_operand 3 "const_int_operand" "n"))])) - (match_operator:SF 2 "unary_float_operator" - [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f") - (parallel [(match_operand 4 - "const_int_operand" "n")]))])) - (parallel [(not:BI (match_dup 3)) (match_dup 3)])))] - "TARGET_SHMEDIA_FPU" - "#" - "TARGET_SHMEDIA_FPU && reload_completed" - [(set (match_dup 5) (match_dup 6))] -{ - int endian = TARGET_LITTLE_ENDIAN ? 0 : 1; - rtx op1 = gen_rtx_REG (SFmode, - (true_regnum (operands[1]) - + (INTVAL (operands[4]) ^ endian))); - - operands[7] = gen_rtx_REG (SFmode, - (true_regnum (operands[0]) - + (INTVAL (operands[3]) ^ endian))); - operands[6] = gen_rtx_fmt_e (GET_CODE (operands[2]), SFmode, op1); -} - [(set_attr "type" "fparith_media")]) - -(define_insn_and_split "binary_sf_op0" - [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f") - (vec_concat:V2SF - (match_operator:SF 3 "binary_float_operator" - [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f") - (parallel [(const_int 0)])) - (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f") - (parallel [(const_int 0)]))]) - (vec_select:SF - (match_dup 0) - (parallel [(const_int 1)]))))] - "TARGET_SHMEDIA_FPU" - "#" - "&& reload_completed" - [(set (match_dup 4) (match_dup 5))] -{ - int endian = TARGET_LITTLE_ENDIAN ? 0 : 1; - rtx op1 = gen_rtx_REG (SFmode, - true_regnum (operands[1]) + endian); - rtx op2 = gen_rtx_REG (SFmode, - true_regnum (operands[2]) + endian); - - operands[4] = gen_rtx_REG (SFmode, - true_regnum (operands[0]) + endian); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2); -} - [(set_attr "type" "fparith_media")]) - -(define_insn_and_split "binary_sf_op1" - [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f") - (vec_concat:V2SF - (vec_select:SF - (match_dup 0) - (parallel [(const_int 0)])) - (match_operator:SF 3 "binary_float_operator" - [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f") - (parallel [(const_int 1)])) - (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f") - (parallel [(const_int 1)]))])))] - "TARGET_SHMEDIA_FPU" - "#" - "&& reload_completed" - [(set (match_dup 4) (match_dup 5))] -{ - int endian = TARGET_LITTLE_ENDIAN ? 0 : 1; - rtx op1 = gen_rtx_REG (SFmode, true_regnum (operands[1]) + (1 ^ endian)); - rtx op2 = gen_rtx_REG (SFmode, true_regnum (operands[2]) + (1 ^ endian)); - - operands[4] = gen_rtx_REG (SFmode, true_regnum (operands[0]) + (1 ^ endian)); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SFmode, op1, op2); -} - [(set_attr "type" "fparith_media")]) - -(define_insn "addsf3_i" +(define_insn "addsf3_i" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0") (match_operand:SF 2 "fp_arith_reg_operand" "f"))) @@ -13406,23 +9212,12 @@ label: [(set (match_operand:SF 0 "fp_arith_reg_operand" "") (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "") (match_operand:SF 2 "fp_arith_reg_operand" "")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" + "TARGET_SH2E" { - if (TARGET_SH2E) - { - emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "*subsf3_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fsub.s %1, %2, %0" - [(set_attr "type" "fparith_media")]) - (define_insn "subsf3_i" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0") @@ -13438,23 +9233,12 @@ label: [(set (match_operand:SF 0 "fp_arith_reg_operand" "") (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "") (match_operand:SF 2 "fp_arith_reg_operand" "")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" + "TARGET_SH2E" { - if (TARGET_SH2E) - { - emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "*mulsf3_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fmul.s %1, %2, %0" - [(set_attr "type" "fparith_media")]) - (define_insn "mulsf3_i" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0") @@ -13472,14 +9256,10 @@ label: (fma:SF (match_operand:SF 1 "fp_arith_reg_operand") (match_operand:SF 2 "fp_arith_reg_operand") (match_operand:SF 3 "fp_arith_reg_operand")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" + "TARGET_SH2E" { - if (TARGET_SH2E) - { - emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2], - operands[3])); - DONE; - } + emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2], operands[3])); + DONE; }) (define_insn "fmasf4_i" @@ -13494,15 +9274,6 @@ label: [(set_attr "type" "fp") (set_attr "fp_mode" "single")]) -(define_insn "fmasf4_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "f") - (match_operand:SF 2 "fp_arith_reg_operand" "f") - (match_operand:SF 3 "fp_arith_reg_operand" "0")))] - "TARGET_SHMEDIA_FPU" - "fmac.s %1, %2, %0" - [(set_attr "type" "fparith_media")]) - ;; For some cases such as 'a * b + a' the FMA pattern is not generated by ;; previous transformations. If FMA is generally allowed, let the combine ;; pass utilize it. @@ -13529,38 +9300,8 @@ label: [(set_attr "type" "fp") (set_attr "fp_mode" "single")]) -(define_insn "*fmasf4_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")) - (match_operand:SF 3 "fp_arith_reg_operand" "0")))] - "TARGET_SHMEDIA_FPU && flag_fp_contract_mode != FP_CONTRACT_OFF" - "fmac.s %1, %2, %0" - [(set_attr "type" "fparith_media")]) - -(define_expand "divsf3" - [(set (match_operand:SF 0 "fp_arith_reg_operand") - (div:SF (match_operand:SF 1 "fp_arith_reg_operand") - (match_operand:SF 2 "fp_arith_reg_operand")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" -{ - if (TARGET_SH2E) - { - emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2])); - DONE; - } -}) - -(define_insn "*divsf3_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fdiv.s %1, %2, %0" - [(set_attr "type" "fdiv_media")]) - (define_insn "divsf3_i" - [(set (match_operand:SF 0 "fp_arith_reg_dest" "=f") + [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0") (match_operand:SF 2 "fp_arith_reg_operand" "f"))) (clobber (reg:SI FPSCR_STAT_REG)) @@ -13570,32 +9311,15 @@ label: [(set_attr "type" "fdiv") (set_attr "fp_mode" "single")]) -(define_insn "floatdisf2" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (float:SF (match_operand:DI 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "float.qs %1, %0" - [(set_attr "type" "fpconv_media")]) - (define_expand "floatsisf2" [(set (match_operand:SF 0 "fp_arith_reg_operand" "") (float:SF (match_operand:SI 1 "fpul_operand" "")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" + "TARGET_SH2E" { - if (!TARGET_SHMEDIA_FPU) - { - emit_insn (gen_floatsisf2_i4 (operands[0], operands[1])); - DONE; - } + emit_insn (gen_floatsisf2_i4 (operands[0], operands[1])); + DONE; }) -(define_insn "*floatsisf2_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (float:SF (match_operand:SI 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "float.ls %1, %0" - [(set_attr "type" "fpconv_media")]) - (define_insn "floatsisf2_i4" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") (float:SF (match_operand:SI 1 "fpul_operand" "y"))) @@ -13606,32 +9330,15 @@ label: [(set_attr "type" "fp") (set_attr "fp_mode" "single")]) -(define_insn "fix_truncsfdi2" - [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f") - (fix:DI (match_operand:SF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "ftrc.sq %1, %0" - [(set_attr "type" "fpconv_media")]) - (define_expand "fix_truncsfsi2" [(set (match_operand:SI 0 "fpul_operand" "=y") (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" + "TARGET_SH2E" { - if (!TARGET_SHMEDIA_FPU) - { - emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1])); - DONE; - } + emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1])); + DONE; }) -(define_insn "*fix_truncsfsi2_media" - [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f") - (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "ftrc.sl %1, %0" - [(set_attr "type" "fpconv_media")]) - (define_insn "fix_truncsfsi2_i4" [(set (match_operand:SI 0 "fpul_operand" "=y") (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f"))) @@ -13678,66 +9385,23 @@ label: [(set_attr "length" "4") (set_attr "fp_mode" "single")]) -(define_insn "cmpeqsf_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (match_operand:SF 1 "fp_arith_reg_operand" "f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcmpeq.s %1, %2, %0" - [(set_attr "type" "fcmp_media")]) - -(define_insn "cmpgtsf_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (gt:SI (match_operand:SF 1 "fp_arith_reg_operand" "f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcmpgt.s %1, %2, %0" - [(set_attr "type" "fcmp_media")]) - -(define_insn "cmpgesf_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (ge:SI (match_operand:SF 1 "fp_arith_reg_operand" "f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcmpge.s %1, %2, %0" - [(set_attr "type" "fcmp_media")]) - -(define_insn "cmpunsf_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (unordered:SI (match_operand:SF 1 "fp_arith_reg_operand" "f") - (match_operand:SF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcmpun.s %1, %2, %0" - [(set_attr "type" "fcmp_media")]) - (define_expand "cbranchsf4" [(set (pc) - (if_then_else (match_operator 0 "sh_float_comparison_operator" + (if_then_else (match_operator 0 "ordered_comparison_operator" [(match_operand:SF 1 "arith_operand" "") (match_operand:SF 2 "arith_operand" "")]) (match_operand 3 "" "") (pc)))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU" + "TARGET_SH2E" { - if (TARGET_SHMEDIA) - emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2], - operands[3])); - else - sh_emit_compare_and_branch (operands, SFmode); + sh_emit_compare_and_branch (operands, SFmode); DONE; }) (define_expand "negsf2" [(set (match_operand:SF 0 "fp_arith_reg_operand") (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU") - -(define_insn "*negsf2_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fneg.s %1, %0" - [(set_attr "type" "fmove_media")]) + "TARGET_SH2E") (define_insn "*negsf2_i" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") @@ -13749,22 +9413,12 @@ label: (define_expand "sqrtsf2" [(set (match_operand:SF 0 "fp_arith_reg_operand" "") (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))] - "TARGET_SH3E || TARGET_SHMEDIA_FPU" + "TARGET_SH3E" { - if (TARGET_SH3E) - { - emit_insn (gen_sqrtsf2_i (operands[0], operands[1])); - DONE; - } + emit_insn (gen_sqrtsf2_i (operands[0], operands[1])); + DONE; }) -(define_insn "*sqrtsf2_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fsqrt.s %1, %0" - [(set_attr "type" "fdiv_media")]) - (define_insn "sqrtsf2_i" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0"))) @@ -13845,14 +9499,7 @@ label: (define_expand "abssf2" [(set (match_operand:SF 0 "fp_arith_reg_operand") (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))] - "TARGET_SH2E || TARGET_SHMEDIA_FPU") - -(define_insn "*abssf2_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fabs.s %1, %0" - [(set_attr "type" "fmove_media")]) + "TARGET_SH2E") (define_insn "*abssf2_i" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") @@ -13865,23 +9512,12 @@ label: [(set (match_operand:DF 0 "fp_arith_reg_operand" "") (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "") (match_operand:DF 2 "fp_arith_reg_operand" "")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "*adddf3_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f") - (match_operand:DF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fadd.d %1, %2, %0" - [(set_attr "type" "dfparith_media")]) - (define_insn "adddf3_i" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0") @@ -13897,23 +9533,12 @@ label: [(set (match_operand:DF 0 "fp_arith_reg_operand" "") (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "") (match_operand:DF 2 "fp_arith_reg_operand" "")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "*subdf3_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "f") - (match_operand:DF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fsub.d %1, %2, %0" - [(set_attr "type" "dfparith_media")]) - (define_insn "subdf3_i" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0") @@ -13929,23 +9554,12 @@ label: [(set (match_operand:DF 0 "fp_arith_reg_operand" "") (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "") (match_operand:DF 2 "fp_arith_reg_operand" "")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "*muldf3_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%f") - (match_operand:DF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fmul.d %1, %2, %0" - [(set_attr "type" "dfmul_media")]) - (define_insn "muldf3_i" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0") @@ -13961,23 +9575,12 @@ label: [(set (match_operand:DF 0 "fp_arith_reg_operand" "") (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "") (match_operand:DF 2 "fp_arith_reg_operand" "")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2])); - DONE; - } + emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2])); + DONE; }) -(define_insn "*divdf3_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "f") - (match_operand:DF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fdiv.d %1, %2, %0" - [(set_attr "type" "dfdiv_media")]) - (define_insn "divdf3_i" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0") @@ -13989,32 +9592,15 @@ label: [(set_attr "type" "dfdiv") (set_attr "fp_mode" "double")]) -(define_insn "floatdidf2" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (float:DF (match_operand:DI 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "float.qd %1, %0" - [(set_attr "type" "dfpconv_media")]) - (define_expand "floatsidf2" [(set (match_operand:DF 0 "fp_arith_reg_operand" "") (float:DF (match_operand:SI 1 "fpul_operand" "")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_floatsidf2_i (operands[0], operands[1])); - DONE; - } + emit_insn (gen_floatsidf2_i (operands[0], operands[1])); + DONE; }) -(define_insn "*floatsidf2_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (float:DF (match_operand:SI 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "float.ld %1, %0" - [(set_attr "type" "dfpconv_media")]) - (define_insn "floatsidf2_i" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (float:DF (match_operand:SI 1 "fpul_operand" "y"))) @@ -14025,32 +9611,15 @@ label: [(set_attr "type" "dfp_conv") (set_attr "fp_mode" "double")]) -(define_insn "fix_truncdfdi2" - [(set (match_operand:DI 0 "fp_arith_reg_dest" "=f") - (fix:DI (match_operand:DF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "ftrc.dq %1, %0" - [(set_attr "type" "dfpconv_media")]) - (define_expand "fix_truncdfsi2" [(set (match_operand:SI 0 "fpul_operand" "") (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1])); - DONE; - } + emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1])); + DONE; }) -(define_insn "*fix_truncdfsi2_media" - [(set (match_operand:SI 0 "fp_arith_reg_operand" "=f") - (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "ftrc.dl %1, %0" - [(set_attr "type" "dfpconv_media")]) - (define_insn "fix_truncdfsi2_i" [(set (match_operand:SI 0 "fpul_operand" "=y") (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f"))) @@ -14098,66 +9667,23 @@ label: [(set_attr "length" "4") (set_attr "fp_mode" "double")]) -(define_insn "cmpeqdf_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (match_operand:DF 1 "fp_arith_reg_operand" "f") - (match_operand:DF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcmpeq.d %1,%2,%0" - [(set_attr "type" "fcmp_media")]) - -(define_insn "cmpgtdf_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (gt:SI (match_operand:DF 1 "fp_arith_reg_operand" "f") - (match_operand:DF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcmpgt.d %1,%2,%0" - [(set_attr "type" "fcmp_media")]) - -(define_insn "cmpgedf_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (ge:SI (match_operand:DF 1 "fp_arith_reg_operand" "f") - (match_operand:DF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcmpge.d %1,%2,%0" - [(set_attr "type" "fcmp_media")]) - -(define_insn "cmpundf_media" - [(set (match_operand:SI 0 "register_operand" "=r") - (unordered:SI (match_operand:DF 1 "fp_arith_reg_operand" "f") - (match_operand:DF 2 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcmpun.d %1,%2,%0" - [(set_attr "type" "fcmp_media")]) - (define_expand "cbranchdf4" [(set (pc) - (if_then_else (match_operator 0 "sh_float_comparison_operator" + (if_then_else (match_operator 0 "ordered_comparison_operator" [(match_operand:DF 1 "arith_operand" "") (match_operand:DF 2 "arith_operand" "")]) (match_operand 3 "" "") (pc)))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SHMEDIA) - emit_jump_insn (gen_cbranchfp4_media (operands[0], operands[1], operands[2], - operands[3])); - else - sh_emit_compare_and_branch (operands, DFmode); + sh_emit_compare_and_branch (operands, DFmode); DONE; }) (define_expand "negdf2" [(set (match_operand:DF 0 "fp_arith_reg_operand") (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU") - -(define_insn "*negdf2_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fneg.d %1, %0" - [(set_attr "type" "fmove_media")]) + "TARGET_SH4 || TARGET_SH2A_DOUBLE") (define_insn "*negdf2_i" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") @@ -14169,22 +9695,12 @@ label: (define_expand "sqrtdf2" [(set (match_operand:DF 0 "fp_arith_reg_operand") (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_sqrtdf2_i (operands[0], operands[1])); - DONE; - } + emit_insn (gen_sqrtdf2_i (operands[0], operands[1])); + DONE; }) -(define_insn "*sqrtdf2_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fsqrt.d %1, %0" - [(set_attr "type" "dfdiv_media")]) - (define_insn "sqrtdf2_i" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0"))) @@ -14198,14 +9714,7 @@ label: (define_expand "absdf2" [(set (match_operand:DF 0 "fp_arith_reg_operand") (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU") - -(define_insn "*absdf2_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fabs.d %1, %0" - [(set_attr "type" "fmove_media")]) + "TARGET_SH4 || TARGET_SH2A_DOUBLE") (define_insn "*absdf2_i" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") @@ -14217,22 +9726,12 @@ label: (define_expand "extendsfdf2" [(set (match_operand:DF 0 "fp_arith_reg_operand" "") (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1])); - DONE; - } + emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1])); + DONE; }) -(define_insn "*extendsfdf2_media" - [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") - (float_extend:DF (match_operand:SF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcnv.sd %1, %0" - [(set_attr "type" "dfpconv_media")]) - (define_insn "extendsfdf2_i4" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (float_extend:DF (match_operand:SF 1 "fpul_operand" "y"))) @@ -14246,22 +9745,12 @@ label: (define_expand "truncdfsf2" [(set (match_operand:SF 0 "fpul_operand" "") (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))] - "(TARGET_SH4 || TARGET_SH2A_DOUBLE) || TARGET_SHMEDIA_FPU" + "TARGET_SH4 || TARGET_SH2A_DOUBLE" { - if (TARGET_SH4 || TARGET_SH2A_DOUBLE) - { - emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1])); - DONE; - } + emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1])); + DONE; }) -(define_insn "*truncdfsf2_media" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))] - "TARGET_SHMEDIA_FPU" - "fcnv.ds %1, %0" - [(set_attr "type" "dfpconv_media")]) - (define_insn "truncdfsf2_i4" [(set (match_operand:SF 0 "fpul_operand" "=y") (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f"))) @@ -15373,1927 +10862,49 @@ label: } [(set_attr "length" "4")]) -;; ------------------------------------------------------------------------- -;; Integer vector moves -;; ------------------------------------------------------------------------- - -(define_expand "movv8qi" - [(set (match_operand:V8QI 0 "general_movdst_operand" "") - (match_operand:V8QI 1 "general_movsrc_operand" ""))] - "TARGET_SHMEDIA" -{ - prepare_move_operands (operands, V8QImode); -}) - -(define_insn "movv8qi_i" - [(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m") - (match_operand:V8QI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))] - "TARGET_SHMEDIA - && (register_operand (operands[0], V8QImode) - || sh_register_operand (operands[1], V8QImode))" - "@ - add %1, r63, %0 - movi %1, %0 - # - ld%M1.q %m1, %0 - st%M0.q %m0, %N1" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media") - (set_attr "length" "4,4,16,4,4")]) - -(define_split - [(set (match_operand:V8QI 0 "arith_reg_dest" "") - (subreg:V8QI (const_int 0) 0))] - "TARGET_SHMEDIA" - [(set (match_dup 0) - (const_vector:V8QI [(const_int 0) (const_int 0) (const_int 0) - (const_int 0) (const_int 0) (const_int 0) - (const_int 0) (const_int 0)]))]) - -(define_split - [(set (match_operand 0 "arith_reg_dest" "") - (match_operand 1 "sh_rep_vec" ""))] - "TARGET_SHMEDIA && reload_completed - && GET_MODE (operands[0]) == GET_MODE (operands[1]) - && sh_vector_mode_supported_p (GET_MODE (operands[0])) - && GET_MODE_SIZE (GET_MODE (operands[0])) == 8 - && (XVECEXP (operands[1], 0, 0) != const0_rtx - || XVECEXP (operands[1], 0, 1) != const0_rtx) - && (XVECEXP (operands[1], 0, 0) != constm1_rtx - || XVECEXP (operands[1], 0, 1) != constm1_rtx)" - [(set (match_dup 0) (match_dup 1)) - (match_dup 2)] -{ - int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (operands[1])); - rtx elt1 = XVECEXP (operands[1], 0, 1); - - if (unit_size > 2) - operands[2] = gen_mshflo_l (operands[0], operands[0], operands[0]); - else - { - if (unit_size < 2) - operands[0] = gen_rtx_REG (V4HImode, true_regnum (operands[0])); - operands[2] = gen_mperm_w0 (operands[0], operands[0]); - } - operands[0] = gen_rtx_REG (DImode, true_regnum (operands[0])); - operands[1] = XVECEXP (operands[1], 0, 0); - if (unit_size < 2) - { - if (CONST_INT_P (operands[1]) && CONST_INT_P (elt1)) - operands[1] - = GEN_INT (TARGET_LITTLE_ENDIAN - ? (INTVAL (operands[1]) & 0xff) + (INTVAL (elt1) << 8) - : (INTVAL (operands[1]) << 8) + (INTVAL (elt1) & 0xff)); - else - { - operands[0] = gen_rtx_REG (V2QImode, true_regnum (operands[0])); - operands[1] - = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, operands[1], elt1)); - } - } -}) - -(define_split - [(set (match_operand 0 "arith_reg_dest" "") - (match_operand 1 "sh_const_vec" ""))] - "TARGET_SHMEDIA && reload_completed - && GET_MODE (operands[0]) == GET_MODE (operands[1]) - && sh_vector_mode_supported_p (GET_MODE (operands[0]))" - [(set (match_dup 0) (match_dup 1))] -{ - rtx v = operands[1]; - machine_mode new_mode - = mode_for_size (GET_MODE_BITSIZE (GET_MODE (v)), MODE_INT, 0); - - operands[0] = gen_rtx_REG (new_mode, true_regnum (operands[0])); - operands[1] - = simplify_subreg (new_mode, operands[1], GET_MODE (operands[1]), 0); -}) - -(define_expand "movv2hi" - [(set (match_operand:V2HI 0 "general_movdst_operand" "") - (match_operand:V2HI 1 "general_movsrc_operand" ""))] - "TARGET_SHMEDIA" -{ - prepare_move_operands (operands, V2HImode); -}) - -(define_insn "movv2hi_i" - [(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m") - (match_operand:V2HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))] - "TARGET_SHMEDIA - && (register_operand (operands[0], V2HImode) - || sh_register_operand (operands[1], V2HImode))" - "@ - add.l %1, r63, %0 - movi %1, %0 - # - ld%M1.l %m1, %0 - st%M0.l %m0, %N1" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media") - (set_attr "length" "4,4,16,4,4") - (set (attr "highpart") - (cond [(match_test "sh_contains_memref_p (insn)") - (const_string "user")] - (const_string "ignore")))]) - -(define_expand "movv4hi" - [(set (match_operand:V4HI 0 "general_movdst_operand" "") - (match_operand:V4HI 1 "general_movsrc_operand" ""))] - "TARGET_SHMEDIA" -{ - prepare_move_operands (operands, V4HImode); -}) -(define_insn "movv4hi_i" - [(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m") - (match_operand:V4HI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))] - "TARGET_SHMEDIA - && (register_operand (operands[0], V4HImode) - || sh_register_operand (operands[1], V4HImode))" - "@ - add %1, r63, %0 - movi %1, %0 - # - ld%M1.q %m1, %0 - st%M0.q %m0, %N1" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media") - (set_attr "length" "4,4,16,4,4") - (set_attr "highpart" "depend")]) - -(define_expand "movv2si" - [(set (match_operand:V2SI 0 "general_movdst_operand" "") - (match_operand:V2SI 1 "general_movsrc_operand" ""))] - "TARGET_SHMEDIA" -{ - prepare_move_operands (operands, V2SImode); -}) +;; In user mode, the "pref" instruction will raise a RADDERR exception +;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable +;; implementation of __builtin_prefetch for VxWorks RTPs. +(define_expand "prefetch" + [(prefetch (match_operand 0 "address_operand" "") + (match_operand:SI 1 "const_int_operand" "") + (match_operand:SI 2 "const_int_operand" ""))] + "(TARGET_SH2A || TARGET_SH3) && !TARGET_VXWORKS_RTP") -(define_insn "movv2si_i" - [(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m") - (match_operand:V2SI 1 "general_movsrc_operand" "r,I16CssZ,nW,m,rlZ"))] - "TARGET_SHMEDIA - && (register_operand (operands[0], V2SImode) - || sh_register_operand (operands[1], V2SImode))" - "@ - add %1, r63, %0 - # - # - ld%M1.q %m1, %0 - st%M0.q %m0, %N1" - [(set_attr "type" "arith_media,arith_media,*,load_media,store_media") - (set_attr "length" "4,4,16,4,4") - (set_attr "highpart" "depend")]) +(define_insn "*prefetch" + [(prefetch (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "const_int_operand" "n") + (match_operand:SI 2 "const_int_operand" "n"))] + "(TARGET_SH2A || TARGET_SH3) && ! TARGET_VXWORKS_RTP" + "pref @%0" + [(set_attr "type" "other")]) ;; ------------------------------------------------------------------------- -;; Multimedia Intrinsics +;; Stack Protector Patterns ;; ------------------------------------------------------------------------- -(define_insn "absv2si2" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (abs:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mabs.l %1, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "absv4hi2" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (abs:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mabs.w %1, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "addv2si3" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r") - (match_operand:V2SI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "madd.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn "addv4hi3" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r") - (match_operand:V4HI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "madd.w %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn_and_split "addv2hi3" - [(set (match_operand:V2HI 0 "arith_reg_dest" "=r") - (plus:V2HI (match_operand:V2HI 1 "extend_reg_operand" "%r") - (match_operand:V2HI 2 "extend_reg_operand" "r")))] - "TARGET_SHMEDIA" - "#" - "TARGET_SHMEDIA" - [(const_int 0)] +(define_expand "stack_protect_set" + [(set (match_operand 0 "memory_operand" "") + (match_operand 1 "memory_operand" ""))] + "" { - rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0); - rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0); - rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0); - rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0); - rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0); - - emit_insn (gen_addv4hi3 (v4hi_dst, src0, src1)); - emit_insn (gen_truncdisi2 (si_dst, di_dst)); - DONE; -} - [(set_attr "highpart" "must_split")]) - -(define_insn "ssaddv2si3" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (ss_plus:V2SI (match_operand:V2SI 1 "arith_reg_operand" "%r") - (match_operand:V2SI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "madds.l %1, %2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "usaddv8qi3" - [(set (match_operand:V8QI 0 "arith_reg_dest" "=r") - (us_plus:V8QI (match_operand:V8QI 1 "arith_reg_operand" "%r") - (match_operand:V8QI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "madds.ub %1, %2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "ssaddv4hi3" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (ss_plus:V4HI (match_operand:V4HI 1 "arith_reg_operand" "%r") - (match_operand:V4HI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "madds.w %1, %2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "negcmpeqv8qi" - [(set (match_operand:V8QI 0 "arith_reg_dest" "=r") - (neg:V8QI (eq:V8QI - (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ") - (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcmpeq.b %N1, %N2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "negcmpeqv2si" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (neg:V2SI (eq:V2SI - (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ") - (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcmpeq.l %N1, %N2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "negcmpeqv4hi" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (neg:V4HI (eq:V4HI - (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ") - (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcmpeq.w %N1, %N2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "negcmpgtuv8qi" - [(set (match_operand:V8QI 0 "arith_reg_dest" "=r") - (neg:V8QI (gtu:V8QI - (match_operand:V8QI 1 "arith_reg_or_0_operand" "%rZ") - (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcmpgt.ub %N1, %N2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "negcmpgtv2si" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (neg:V2SI (gt:V2SI - (match_operand:V2SI 1 "arith_reg_or_0_operand" "%rZ") - (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcmpgt.l %N1, %N2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "negcmpgtv4hi" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (neg:V4HI (gt:V4HI - (match_operand:V4HI 1 "arith_reg_or_0_operand" "%rZ") - (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcmpgt.w %N1, %N2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "mcmv" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:DI 2 "arith_reg_operand" "r")) - (and:DI (match_operand:DI 3 "arith_reg_operand" "0") - (not:DI (match_dup 2)))))] - "TARGET_SHMEDIA" - "mcmv %N1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn "mcnvs_lw" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (vec_concat:V4HI - (ss_truncate:V2HI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ")) - (ss_truncate:V2HI - (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcnvs.lw %N1, %N2, %0" - [(set_attr "type" "mcmp_media")]) - -(define_insn "mcnvs_wb" - [(set (match_operand:V8QI 0 "arith_reg_dest" "=r") - (vec_concat:V8QI - (ss_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")) - (ss_truncate:V4QI - (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcnvs.wb %N1, %N2, %0" - [(set_attr "type" "mcmp_media")]) - -(define_insn "mcnvs_wub" - [(set (match_operand:V8QI 0 "arith_reg_dest" "=r") - (vec_concat:V8QI - (us_truncate:V4QI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ")) - (us_truncate:V4QI - (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mcnvs.wub %N1, %N2, %0" - [(set_attr "type" "mcmp_media")]) - -(define_insn "mextr_rl" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:HI 3 "mextr_bit_offset" "i")) - (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") - (match_operand:HI 4 "mextr_bit_offset" "i"))))] - "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64" -{ - static char templ[21]; - sprintf (templ, "mextr%d %%N1, %%N2, %%0", - (int) INTVAL (operands[3]) >> 3); - return templ; -} - [(set_attr "type" "arith_media")]) - -(define_insn "*mextr_lr" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:HI 3 "mextr_bit_offset" "i")) - (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") - (match_operand:HI 4 "mextr_bit_offset" "i"))))] - "TARGET_SHMEDIA && INTVAL (operands[3]) + INTVAL (operands[4]) == 64" -{ - static char templ[21]; - sprintf (templ, "mextr%d %%N2, %%N1, %%0", - (int) INTVAL (operands[4]) >> 3); - return templ; -} - [(set_attr "type" "arith_media")]) - -; mextrN can be modelled with vec_select / vec_concat, but the selection -; vector then varies depending on endianness. -(define_expand "mextr1" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2], - GEN_INT (1 * 8), GEN_INT (7 * 8))); + emit_insn (gen_stack_protect_set_si (operands[0], operands[1])); DONE; }) -(define_expand "mextr2" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" +(define_insn "stack_protect_set_si" + [(set (match_operand:SI 0 "memory_operand" "=m") + (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) + (set (match_scratch:SI 2 "=&r") (const_int 0))] + "" { - emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2], - GEN_INT (2 * 8), GEN_INT (6 * 8))); - DONE; -}) - -(define_expand "mextr3" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2], - GEN_INT (3 * 8), GEN_INT (5 * 8))); - DONE; -}) - -(define_expand "mextr4" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2], - GEN_INT (4 * 8), GEN_INT (4 * 8))); - DONE; -}) - -(define_expand "mextr5" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2], - GEN_INT (5 * 8), GEN_INT (3 * 8))); - DONE; -}) - -(define_expand "mextr6" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2], - GEN_INT (6 * 8), GEN_INT (2 * 8))); - DONE; -}) - -(define_expand "mextr7" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:DI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mextr_rl (operands[0], operands[1], operands[2], - GEN_INT (7 * 8), GEN_INT (1 * 8))); - DONE; -}) - -(define_expand "mmacfx_wl" - [(match_operand:V2SI 0 "arith_reg_dest" "") - (match_operand:V2HI 1 "extend_reg_operand" "") - (match_operand:V2HI 2 "extend_reg_operand" "") - (match_operand:V2SI 3 "arith_reg_operand" "")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mmacfx_wl_i (operands[0], operands[3], - operands[1], operands[2])); - DONE; -}) - -;; This could be highpart ignore if it only had inputs 2 or 3, but input 1 -;; is depend -(define_insn "mmacfx_wl_i" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (ss_plus:V2SI - (match_operand:V2SI 1 "arith_reg_operand" "0") - (ss_truncate:V2SI - (ashift:V2DI - (sign_extend:V2DI - (mult:V2SI - (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r")) - (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r")))) - (const_int 1)))))] - "TARGET_SHMEDIA" - "mmacfx.wl %2, %3, %0" - [(set_attr "type" "mac_media") - (set_attr "highpart" "depend")]) - -(define_expand "mmacnfx_wl" - [(match_operand:V2SI 0 "arith_reg_dest" "") - (match_operand:V2HI 1 "extend_reg_operand" "") - (match_operand:V2HI 2 "extend_reg_operand" "") - (match_operand:V2SI 3 "arith_reg_operand" "")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mmacnfx_wl_i (operands[0], operands[3], - operands[1], operands[2])); - DONE; -}) - -(define_insn "mmacnfx_wl_i" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (ss_minus:V2SI - (match_operand:V2SI 1 "arith_reg_operand" "0") - (ss_truncate:V2SI - (ashift:V2DI - (sign_extend:V2DI - (mult:V2SI - (sign_extend:V2SI (match_operand:V2HI 2 "extend_reg_operand" "r")) - (sign_extend:V2SI (match_operand:V2HI 3 "extend_reg_operand" "r")))) - (const_int 1)))))] - "TARGET_SHMEDIA" - "mmacnfx.wl %2, %3, %0" - [(set_attr "type" "mac_media") - (set_attr "highpart" "depend")]) - -(define_insn "mulv2si3" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (mult:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r") - (match_operand:V2SI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mmul.l %1, %2, %0" - [(set_attr "type" "d2mpy_media") - (set_attr "highpart" "depend")]) - -(define_insn "mulv4hi3" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (mult:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r") - (match_operand:V4HI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mmul.w %1, %2, %0" - [(set_attr "type" "dmpy_media") - (set_attr "highpart" "depend")]) - -(define_insn "mmulfx_l" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (ss_truncate:V2SI - (ashiftrt:V2DI - (mult:V2DI - (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r")) - (sign_extend:V2DI (match_operand:V2SI 2 "arith_reg_operand" "r"))) - (const_int 31))))] - "TARGET_SHMEDIA" - "mmulfx.l %1, %2, %0" - [(set_attr "type" "d2mpy_media") - (set_attr "highpart" "depend")]) - -(define_insn "mmulfx_w" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (ss_truncate:V4HI - (ashiftrt:V4SI - (mult:V4SI - (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r")) - (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r"))) - (const_int 15))))] - "TARGET_SHMEDIA" - "mmulfx.w %1, %2, %0" - [(set_attr "type" "dmpy_media") - (set_attr "highpart" "depend")]) - -(define_insn "mmulfxrp_w" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (ss_truncate:V4HI - (ashiftrt:V4SI - (plus:V4SI - (mult:V4SI - (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r")) - (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r"))) - (const_int 16384)) - (const_int 15))))] - "TARGET_SHMEDIA" - "mmulfxrp.w %1, %2, %0" - [(set_attr "type" "dmpy_media") - (set_attr "highpart" "depend")]) - - -(define_expand "mmulhi_wl" - [(match_operand:V2SI 0 "arith_reg_dest" "") - (match_operand:V4HI 1 "arith_reg_operand" "") - (match_operand:V4HI 2 "arith_reg_operand" "")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul23_wl : gen_mmul01_wl) - (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "mmullo_wl" - [(match_operand:V2SI 0 "arith_reg_dest" "") - (match_operand:V4HI 1 "arith_reg_operand" "") - (match_operand:V4HI 2 "arith_reg_operand" "")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mmul01_wl : gen_mmul23_wl) - (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_insn "mmul23_wl" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (vec_select:V2SI - (mult:V4SI - (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r")) - (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r"))) - (parallel [(const_int 2) (const_int 3)])))] - "TARGET_SHMEDIA" -{ - return (TARGET_LITTLE_ENDIAN - ? "mmulhi.wl %1, %2, %0" - : "mmullo.wl %1, %2, %0"); -} - [(set_attr "type" "dmpy_media") - (set (attr "highpart") - (cond [(eq_attr "endian" "big") (const_string "ignore")] - (const_string "user")))]) - -(define_insn "mmul01_wl" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (vec_select:V2SI - (mult:V4SI - (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r")) - (sign_extend:V4SI (match_operand:V4HI 2 "arith_reg_operand" "r"))) - (parallel [(const_int 0) (const_int 1)])))] - "TARGET_SHMEDIA" -{ - return (TARGET_LITTLE_ENDIAN - ? "mmullo.wl %1, %2, %0" - : "mmulhi.wl %1, %2, %0"); -} - [(set_attr "type" "dmpy_media") - (set (attr "highpart") - (cond [(eq_attr "endian" "little") (const_string "ignore")] - (const_string "user")))]) - - -(define_expand "mmulsum_wq" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:V4HI 1 "arith_reg_operand" "") - (match_operand:V4HI 2 "arith_reg_operand" "") - (match_operand:DI 3 "arith_reg_operand" "")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_mmulsum_wq_i (operands[0], operands[3], - operands[1], operands[2])); - DONE; -}) - -(define_insn "mmulsum_wq_i" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (plus:DI (match_operand:DI 1 "arith_reg_operand" "0") - (plus:DI - (plus:DI - (vec_select:DI - (mult:V4DI - (sign_extend:V4DI (match_operand:V4HI 2 "arith_reg_operand" "r")) - (sign_extend:V4DI (match_operand:V4HI 3 "arith_reg_operand" "r"))) - (parallel [(const_int 0)])) - (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2)) - (sign_extend:V4DI (match_dup 3))) - (parallel [(const_int 1)]))) - (plus:DI - (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2)) - (sign_extend:V4DI (match_dup 3))) - (parallel [(const_int 2)])) - (vec_select:DI (mult:V4DI (sign_extend:V4DI (match_dup 2)) - (sign_extend:V4DI (match_dup 3))) - (parallel [(const_int 3)]))))))] - "TARGET_SHMEDIA" - "mmulsum.wq %2, %3, %0" - [(set_attr "type" "mac_media")]) - -(define_expand "mperm_w" - [(match_operand:V4HI 0 "arith_reg_dest" "=r") - (match_operand:V4HI 1 "arith_reg_operand" "r") - (match_operand:QI 2 "extend_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mperm_w_little : gen_mperm_w_big) - (operands[0], operands[1], operands[2])); - DONE; -}) - -; This use of vec_select isn't exactly correct according to rtl.texi -; (because not constant), but it seems a straightforward extension. -(define_insn "mperm_w_little" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (vec_select:V4HI - (match_operand:V4HI 1 "arith_reg_operand" "r") - (parallel - [(zero_extract:QI (match_operand:QI 2 "extend_reg_or_0_operand" "rZ") - (const_int 2) (const_int 0)) - (zero_extract:QI (match_dup 2) (const_int 2) (const_int 2)) - (zero_extract:QI (match_dup 2) (const_int 2) (const_int 4)) - (zero_extract:QI (match_dup 2) (const_int 2) (const_int 6))])))] - "TARGET_SHMEDIA && TARGET_LITTLE_ENDIAN" - "mperm.w %1, %N2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "mperm_w_big" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (vec_select:V4HI - (match_operand:V4HI 1 "arith_reg_operand" "r") - (parallel - [(zero_extract:QI (not:QI (match_operand:QI 2 - "extend_reg_or_0_operand" "rZ")) - (const_int 2) (const_int 0)) - (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 2)) - (zero_extract:QI (not:QI (match_dup 2)) (const_int 2) (const_int 4)) - (zero_extract:QI (not:QI (match_dup 2)) - (const_int 2) (const_int 6))])))] - "TARGET_SHMEDIA && TARGET_BIG_ENDIAN" - "mperm.w %1, %N2, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "mperm_w0" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (vec_duplicate:V4HI (truncate:HI (match_operand 1 - "trunc_hi_operand" "r"))))] - "TARGET_SHMEDIA" - "mperm.w %1, r63, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_expand "msad_ubq" - [(match_operand:DI 0 "arith_reg_dest" "") - (match_operand:V8QI 1 "arith_reg_or_0_operand" "") - (match_operand:V8QI 2 "arith_reg_or_0_operand" "") - (match_operand:DI 3 "arith_reg_operand" "")] - "TARGET_SHMEDIA" -{ - emit_insn (gen_msad_ubq_i (operands[0], operands[3], - operands[1], operands[2])); - DONE; -}) - -(define_insn "msad_ubq_i" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (plus:DI - (plus:DI - (plus:DI - (plus:DI - (match_operand:DI 1 "arith_reg_operand" "0") - (abs:DI (vec_select:DI - (minus:V8DI - (zero_extend:V8DI - (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")) - (zero_extend:V8DI - (match_operand:V8QI 3 "arith_reg_or_0_operand" "rZ"))) - (parallel [(const_int 0)])))) - (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2)) - (zero_extend:V8DI (match_dup 3))) - (parallel [(const_int 1)])))) - (plus:DI - (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2)) - (zero_extend:V8DI (match_dup 3))) - (parallel [(const_int 2)]))) - (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2)) - (zero_extend:V8DI (match_dup 3))) - (parallel [(const_int 3)]))))) - (plus:DI - (plus:DI - (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2)) - (zero_extend:V8DI (match_dup 3))) - (parallel [(const_int 4)]))) - (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2)) - (zero_extend:V8DI (match_dup 3))) - (parallel [(const_int 5)])))) - (plus:DI - (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2)) - (zero_extend:V8DI (match_dup 3))) - (parallel [(const_int 6)]))) - (abs:DI (vec_select:DI (minus:V8DI (zero_extend:V8DI (match_dup 2)) - (zero_extend:V8DI (match_dup 3))) - (parallel [(const_int 7)])))))))] - "TARGET_SHMEDIA" - "msad.ubq %N2, %N3, %0" - [(set_attr "type" "mac_media")]) - -(define_insn "mshalds_l" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (ss_truncate:V2SI - (ashift:V2DI - (sign_extend:V2DI (match_operand:V2SI 1 "arith_reg_operand" "r")) - (and:DI (match_operand:DI 2 "arith_reg_operand" "r") - (const_int 31)))))] - "TARGET_SHMEDIA" - "mshalds.l %1, %2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "mshalds_w" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (ss_truncate:V4HI - (ashift:V4SI - (sign_extend:V4SI (match_operand:V4HI 1 "arith_reg_operand" "r")) - (and:DI (match_operand:DI 2 "arith_reg_operand" "r") - (const_int 15)))))] - "TARGET_SHMEDIA" - "mshalds.w %1, %2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "ashrv2si3" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (ashiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mshard.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn "ashrv4hi3" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (ashiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mshard.w %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn "mshards_q" - [(set (match_operand:HI 0 "arith_reg_dest" "=r") - (ss_truncate:HI - (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "arith_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mshards.q %1, %N2, %0" - [(set_attr "type" "mcmp_media")]) - -(define_expand "mshfhi_b" - [(match_operand:V8QI 0 "arith_reg_dest" "") - (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_b : gen_mshf0_b) - (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "mshflo_b" - [(match_operand:V8QI 0 "arith_reg_dest" "") - (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_b : gen_mshf4_b) - (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_insn "mshf4_b" - [(set - (match_operand:V8QI 0 "arith_reg_dest" "=r") - (vec_select:V8QI - (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")) - (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13) - (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))] - "TARGET_SHMEDIA" -{ - return (TARGET_LITTLE_ENDIAN - ? "mshfhi.b %N1, %N2, %0" - : "mshflo.b %N1, %N2, %0"); -} - [(set_attr "type" "arith_media") - (set (attr "highpart") - (cond [(eq_attr "endian" "big") (const_string "ignore")] - (const_string "user")))]) - -(define_insn "mshf0_b" - [(set - (match_operand:V8QI 0 "arith_reg_dest" "=r") - (vec_select:V8QI - (vec_concat:V16QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V8QI 2 "arith_reg_or_0_operand" "rZ")) - (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9) - (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))] - "TARGET_SHMEDIA" -{ - return (TARGET_LITTLE_ENDIAN - ? "mshflo.b %N1, %N2, %0" - : "mshfhi.b %N1, %N2, %0"); -} - [(set_attr "type" "arith_media") - (set (attr "highpart") - (cond [(eq_attr "endian" "little") (const_string "ignore")] - (const_string "user")))]) - -(define_expand "mshfhi_l" - [(match_operand:V2SI 0 "arith_reg_dest" "") - (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_l : gen_mshf0_l) - (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "mshflo_l" - [(match_operand:V2SI 0 "arith_reg_dest" "") - (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_l : gen_mshf4_l) - (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_insn "mshf4_l" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (vec_select:V2SI - (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")) - (parallel [(const_int 1) (const_int 3)])))] - "TARGET_SHMEDIA" -{ - return (TARGET_LITTLE_ENDIAN - ? "mshfhi.l %N1, %N2, %0" - : "mshflo.l %N1, %N2, %0"); -} - [(set_attr "type" "arith_media") - (set (attr "highpart") - (cond [(eq_attr "endian" "big") (const_string "ignore")] - (const_string "user")))]) - -(define_insn "mshf0_l" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (vec_select:V2SI - (vec_concat:V4SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V2SI 2 "arith_reg_or_0_operand" "rZ")) - (parallel [(const_int 0) (const_int 2)])))] - "TARGET_SHMEDIA" -{ - return (TARGET_LITTLE_ENDIAN - ? "mshflo.l %N1, %N2, %0" - : "mshfhi.l %N1, %N2, %0"); -} - [(set_attr "type" "arith_media") - (set (attr "highpart") - (cond [(eq_attr "endian" "little") (const_string "ignore")] - (const_string "user")))]) - -(define_expand "mshfhi_w" - [(match_operand:V4HI 0 "arith_reg_dest" "") - (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf4_w : gen_mshf0_w) - (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_expand "mshflo_w" - [(match_operand:V4HI 0 "arith_reg_dest" "") - (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")] - "TARGET_SHMEDIA" -{ - emit_insn ((TARGET_LITTLE_ENDIAN ? gen_mshf0_w : gen_mshf4_w) - (operands[0], operands[1], operands[2])); - DONE; -}) - -(define_insn "mshf4_w" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (vec_select:V4HI - (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")) - (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] - "TARGET_SHMEDIA" -{ - return (TARGET_LITTLE_ENDIAN - ? "mshfhi.w %N1, %N2, %0" - : "mshflo.w %N1, %N2, %0"); -} - [(set_attr "type" "arith_media") - (set (attr "highpart") - (cond [(eq_attr "endian" "big") (const_string "ignore")] - (const_string "user")))]) - -(define_insn "mshf0_w" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (vec_select:V4HI - (vec_concat:V8HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V4HI 2 "arith_reg_or_0_operand" "rZ")) - (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] - "TARGET_SHMEDIA" -{ - return (TARGET_LITTLE_ENDIAN - ? "mshflo.w %N1, %N2, %0" - : "mshfhi.w %N1, %N2, %0"); -} - [(set_attr "type" "arith_media") - (set (attr "highpart") - (cond [(eq_attr "endian" "little") (const_string "ignore")] - (const_string "user")))]) - -(define_insn "mshflo_w_x" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (vec_select:V4HI - (vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rZ") - (match_operand:V2HI 2 "extend_reg_or_0_operand" "rZ")) - (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))] - "TARGET_SHMEDIA" - "mshflo.w %N1, %N2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -;; These are useful to expand ANDs and as combiner patterns. -(define_insn_and_split "mshfhi_l_di" - [(set (match_operand:DI 0 "arith_reg_dest" "=r,f") - (ior:DI (lshiftrt:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ,f") - (const_int 32)) - (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ,?f") - (const_int -4294967296))))] - "TARGET_SHMEDIA" - "@ - mshfhi.l %N1, %N2, %0 - #" - "TARGET_SHMEDIA && reload_completed - && ! GENERAL_REGISTER_P (true_regnum (operands[0]))" - [(set (match_dup 3) (match_dup 4)) - (set (match_dup 5) (match_dup 6))] -{ - operands[3] = gen_lowpart (SImode, operands[0]); - operands[4] = gen_highpart (SImode, operands[1]); - operands[5] = gen_highpart (SImode, operands[0]); - operands[6] = gen_highpart (SImode, operands[2]); -} - [(set_attr "type" "arith_media")]) - -(define_insn "*mshfhi_l_di_rev" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (const_int -4294967296)) - (lshiftrt:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") - (const_int 32))))] - "TARGET_SHMEDIA" - "mshfhi.l %N2, %N1, %0" - [(set_attr "type" "arith_media")]) - -(define_split - [(set (match_operand:DI 0 "arith_reg_dest" "") - (ior:DI (zero_extend:DI (match_operand:SI 1 - "extend_reg_or_0_operand" "")) - (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "") - (const_int -4294967296)))) - (clobber (match_operand:DI 3 "arith_reg_dest" ""))] - "TARGET_SHMEDIA" - [(const_int 0)] -{ - emit_insn (gen_ashldi3_media (operands[3], - simplify_gen_subreg (DImode, operands[1], - SImode, 0), - GEN_INT (32))); - emit_insn (gen_mshfhi_l_di (operands[0], operands[3], operands[2])); - DONE; -}) - -(define_insn "mshflo_l_di" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (and:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (const_int 4294967295)) - (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") - (const_int 32))))] - - "TARGET_SHMEDIA" - "mshflo.l %N1, %N2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_insn "*mshflo_l_di_rev" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (const_int 32)) - (and:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") - (const_int 4294967295))))] - - "TARGET_SHMEDIA" - "mshflo.l %N2, %N1, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -;; Combiner pattern for trampoline initialization. -(define_insn_and_split "*double_shori" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0") - (const_int 32)) - (match_operand:DI 2 "const_int_operand" "n")))] - "TARGET_SHMEDIA - && ! (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)" - "#" - "rtx_equal_p (operands[0], operands[1])" - [(const_int 0)] -{ - HOST_WIDE_INT v = INTVAL (operands[2]); - - emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v >> 16))); - emit_insn (gen_shori_media (operands[0], operands[0], GEN_INT (v & 65535))); - DONE; -} - [(set_attr "highpart" "ignore")]) - -(define_insn "*mshflo_l_di_x" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (zero_extend:DI (match_operand:SI 1 "extend_reg_or_0_operand" - "rZ")) - (ashift:DI (match_operand:DI 2 "arith_reg_or_0_operand" "rZ") - (const_int 32))))] - "TARGET_SHMEDIA" - "mshflo.l %N1, %N2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_insn_and_split "concat_v2sf" - [(set (match_operand:V2SF 0 "register_operand" "=r,f,f?") -;; (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,0,f") - (vec_concat:V2SF (match_operand:SF 1 "register_operand" "rZ,f,f") - (match_operand:SF 2 "register_operand" "rZ,f,f")))] - "TARGET_SHMEDIA" - "@ - mshflo.l %N1, %N2, %0 - # - #" - "TARGET_SHMEDIA && reload_completed - && ! GENERAL_REGISTER_P (true_regnum (operands[0]))" - [(set (match_dup 3) (match_dup 1)) - (set (match_dup 4) (match_dup 2))] -{ - operands[3] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 0); - operands[4] = simplify_gen_subreg (SFmode, operands[0], V2SFmode, 4); -} - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_insn "*mshflo_l_di_x_rev" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (ior:DI (ashift:DI (match_operand:DI 1 "arith_reg_or_0_operand" "rZ") - (const_int 32)) - (zero_extend:DI - (match_operand:SI 2 "extend_reg_or_0_operand" "rZ"))))] - "TARGET_SHMEDIA" - "mshflo.l %N2, %N1, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "ignore")]) - -(define_insn "ashlv2si3" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (ashift:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "shift_count_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mshlld.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_split - [(set (match_operand 0 "any_register_operand" "") - (match_operator 3 "shift_operator" - [(match_operand 1 "any_register_operand" "") - (match_operand 2 "shift_count_reg_operand" "")]))] - "TARGET_SHMEDIA && ! register_operand (operands[2], VOIDmode)" - [(set (match_dup 0) (match_dup 3))] -{ - rtx count = operands[2]; - machine_mode outer_mode = GET_MODE (operands[2]), inner_mode; - - while (GET_CODE (count) == ZERO_EXTEND || GET_CODE (count) == SIGN_EXTEND - || (GET_CODE (count) == SUBREG && SUBREG_BYTE (count) == 0) - || GET_CODE (count) == TRUNCATE) - count = XEXP (count, 0); - inner_mode = GET_MODE (count); - count = simplify_gen_subreg (outer_mode, count, inner_mode, - subreg_lowpart_offset (outer_mode, inner_mode)); - operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), GET_MODE (operands[3]), - operands[1], count); -}) - -(define_insn "ashlv4hi3" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (ashift:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "shift_count_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mshlld.w %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn "lshrv2si3" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (lshiftrt:V2SI (match_operand:V2SI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "shift_count_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mshlrd.l %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn "lshrv4hi3" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (lshiftrt:V4HI (match_operand:V4HI 1 "arith_reg_operand" "r") - (match_operand:DI 2 "shift_count_reg_operand" "r")))] - "TARGET_SHMEDIA" - "mshlrd.w %1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn "subv2si3" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V2SI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "msub.l %N1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn "subv4hi3" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V4HI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "msub.w %N1, %2, %0" - [(set_attr "type" "arith_media") - (set_attr "highpart" "depend")]) - -(define_insn_and_split "subv2hi3" - [(set (match_operand:V2HI 0 "arith_reg_dest" "=r") - (minus:V2HI (match_operand:V2HI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V2HI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "#" - "TARGET_SHMEDIA" - [(const_int 0)] -{ - rtx src0 = simplify_gen_subreg (V4HImode, operands[1], V2HImode, 0); - rtx src1 = simplify_gen_subreg (V4HImode, operands[2], V2HImode, 0); - rtx v4hi_dst = simplify_gen_subreg (V4HImode, operands[0], V2HImode, 0); - rtx di_dst = simplify_gen_subreg (DImode, operands[0], V2HImode, 0); - rtx si_dst = simplify_gen_subreg (SImode, operands[0], V2HImode, 0); - - emit_insn (gen_subv4hi3 (v4hi_dst, src0, src1)); - emit_insn (gen_truncdisi2 (si_dst, di_dst)); - DONE; -} - [(set_attr "highpart" "must_split")]) - -(define_insn "sssubv2si3" - [(set (match_operand:V2SI 0 "arith_reg_dest" "=r") - (ss_minus:V2SI (match_operand:V2SI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V2SI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "msubs.l %N1, %2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "ussubv8qi3" - [(set (match_operand:V8QI 0 "arith_reg_dest" "=r") - (us_minus:V8QI (match_operand:V8QI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V8QI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "msubs.ub %N1, %2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -(define_insn "sssubv4hi3" - [(set (match_operand:V4HI 0 "arith_reg_dest" "=r") - (ss_minus:V4HI (match_operand:V4HI 1 "arith_reg_or_0_operand" "rZ") - (match_operand:V4HI 2 "arith_reg_operand" "r")))] - "TARGET_SHMEDIA" - "msubs.w %N1, %2, %0" - [(set_attr "type" "mcmp_media") - (set_attr "highpart" "depend")]) - -;; ------------------------------------------------------------------------- -;; Floating Point Intrinsics -;; ------------------------------------------------------------------------- - -(define_insn "fcosa_s" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")] - UNSPEC_FCOSA))] - "TARGET_SHMEDIA" - "fcosa.s %1, %0" - [(set_attr "type" "atrans_media")]) - -(define_insn "fsina_s" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (unspec:SF [(match_operand:SI 1 "fp_arith_reg_operand" "f")] - UNSPEC_FSINA))] - "TARGET_SHMEDIA" - "fsina.s %1, %0" - [(set_attr "type" "atrans_media")]) - -(define_insn "fipr" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (plus:SF (plus:SF (vec_select:SF (mult:V4SF (match_operand:V4SF 1 - "fp_arith_reg_operand" "f") - (match_operand:V4SF 2 - "fp_arith_reg_operand" "f")) - (parallel [(const_int 0)])) - (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2)) - (parallel [(const_int 1)]))) - (plus:SF (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2)) - (parallel [(const_int 2)])) - (vec_select:SF (mult:V4SF (match_dup 1) (match_dup 2)) - (parallel [(const_int 3)])))))] - "TARGET_SHMEDIA" - "fipr.s %1, %2, %0" - [(set_attr "type" "fparith_media")]) - -(define_insn "fsrra_s" - [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") - (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "f")] - UNSPEC_FSRRA))] - "TARGET_SHMEDIA" - "fsrra.s %1, %0" - [(set_attr "type" "atrans_media")]) - -(define_insn "ftrv" - [(set (match_operand:V4SF 0 "fp_arith_reg_operand" "=f") - (plus:V4SF - (plus:V4SF - (mult:V4SF - (vec_select:V4SF (match_operand:V16SF 1 "fp_arith_reg_operand" "f") - (parallel [(const_int 0) (const_int 5) - (const_int 10) (const_int 15)])) - (match_operand:V4SF 2 "fp_arith_reg_operand" "f")) - (mult:V4SF - (vec_select:V4SF (match_dup 1) - (parallel [(const_int 4) (const_int 9) - (const_int 14) (const_int 3)])) - (vec_select:V4SF (match_dup 2) - (parallel [(const_int 1) (const_int 2) - (const_int 3) (const_int 0)])))) - (plus:V4SF - (mult:V4SF - (vec_select:V4SF (match_dup 1) - (parallel [(const_int 8) (const_int 13) - (const_int 2) (const_int 7)])) - (vec_select:V4SF (match_dup 2) - (parallel [(const_int 2) (const_int 3) - (const_int 0) (const_int 1)]))) - (mult:V4SF - (vec_select:V4SF (match_dup 1) - (parallel [(const_int 12) (const_int 1) - (const_int 6) (const_int 11)])) - (vec_select:V4SF (match_dup 2) - (parallel [(const_int 3) (const_int 0) - (const_int 1) (const_int 2)]))))))] - "TARGET_SHMEDIA" - "ftrv.s %1, %2, %0" - [(set_attr "type" "fparith_media")]) - -(define_insn "ldhi_l" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (zero_extract:SI - (mem:SI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p") - (const_int 3)) - (const_int -3))) - (plus:SI (and:SI (match_dup 1) (const_int 3)) (const_int 1)) - (const_int 0)))] - "TARGET_SHMEDIA32" - "ldhi.l %U1, %0" - [(set_attr "type" "load_media")]) - -(define_insn "ldhi_q" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extract:DI - (mem:DI (plus:SI (ior:SI (match_operand:QI 1 "ua_address_operand" "p") - (const_int 7)) - (const_int -7))) - (plus:SI (and:SI (match_dup 1) (const_int 7)) (const_int 1)) - (const_int 0)))] - "TARGET_SHMEDIA32" - "ldhi.q %U1, %0" - [(set_attr "type" "load_media")]) - -(define_insn_and_split "*ldhi_q_comb0" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extract:DI - (mem:DI (plus:SI (ior:SI (plus:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "ua_offset" "I06")) - (const_int 7)) - (const_int -7))) - (plus:SI (and:SI (match_dup 1) (const_int 7)) - (const_int 1)) - (const_int 0)))] - "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0" - "#" - "" - [(pc)] -{ - emit_insn (gen_ldhi_q (operands[0], - gen_rtx_PLUS (SImode, operands[1], operands[2]))); - DONE; -}) - -(define_insn_and_split "*ldhi_q_comb1" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extract:DI - (mem:DI (plus:SI (ior:SI (plus:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "ua_offset" "I06")) - (const_int 7)) - (const_int -7))) - (plus:SI (and:SI (plus:SI (match_dup 1) - (match_operand:SI 3 "ua_offset" "I06")) - (const_int 7)) - (const_int 1)) - (const_int 0)))] - "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8) - && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])" - "#" - "" - [(pc)] -{ - emit_insn (gen_ldhi_q (operands[0], - gen_rtx_PLUS (SImode, operands[1], operands[2]))); - DONE; -}) - -(define_insn "ldlo_l" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (zero_extract:SI - (mem:SI (and:SI (match_operand:QI 1 "ua_address_operand" "p") - (const_int -4))) - (minus:SI (const_int 4) (and:SI (match_dup 1) (const_int 3))) - (and:SI (match_dup 1) (const_int 3))))] - "TARGET_SHMEDIA32" - "ldlo.l %U1, %0" - [(set_attr "type" "load_media")]) - -(define_insn "ldlo_q" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extract:DI - (mem:DI (and:SI (match_operand:QI 1 "ua_address_operand" "p") - (const_int -8))) - (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7))) - (and:SI (match_dup 1) (const_int 7))))] - "TARGET_SHMEDIA32" - "ldlo.q %U1, %0" - [(set_attr "type" "load_media")]) - -(define_insn_and_split "*ldlo_q_comb0" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extract:DI - (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "ua_offset" "I06")) - (const_int -8))) - (minus:SI (const_int 8) (and:SI (match_dup 1) (const_int 7))) - (and:SI (match_dup 1) (const_int 7))))] - "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & 7) == 0" - "#" - "" - [(pc)] -{ - emit_insn (gen_ldlo_q (operands[0], - gen_rtx_PLUS (SImode, operands[1], operands[2]))); - DONE; -}) - -(define_insn_and_split "*ldlo_q_comb1" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extract:DI - (mem:DI (and:SI (plus:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "ua_offset" "I06")) - (const_int -8))) - (minus:SI (const_int 8) - (and:SI (plus:SI (match_dup 1) - (match_operand:SI 3 "ua_offset" "I06")) - (const_int 7))) - (and:SI (plus:SI (match_dup 1) (match_dup 3)) (const_int 7))))] - "TARGET_SHMEDIA32 && (INTVAL (operands[2]) & -8) - && (INTVAL (operands[2]) & 7) == INTVAL (operands[3])" - "#" - "" - [(pc)] -{ - emit_insn (gen_ldlo_q (operands[0], - gen_rtx_PLUS (SImode, operands[1], operands[2]))); - DONE; -}) - -(define_insn "sthi_l" - [(set (zero_extract:SI - (mem:SI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p") - (const_int 3)) - (const_int -3))) - (plus:SI (and:SI (match_dup 0) (const_int 3)) (const_int 1)) - (const_int 0)) - (match_operand:SI 1 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA32" - "sthi.l %U0, %1" - [(set_attr "type" "ustore_media")]) - -;; All unaligned stores are considered to be 'narrow' because they typically -;; operate on less that a quadword, and when they operate on a full quadword, -;; the vanilla store high / store low sequence will cause a stall if not -;; scheduled apart. -(define_insn "sthi_q" - [(set (zero_extract:DI - (mem:DI (plus:SI (ior:SI (match_operand:QI 0 "ua_address_operand" "p") - (const_int 7)) - (const_int -7))) - (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1)) - (const_int 0)) - (match_operand:DI 1 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA32" - "sthi.q %U0, %1" - [(set_attr "type" "ustore_media")]) - -(define_insn_and_split "*sthi_q_comb0" - [(set (zero_extract:DI - (mem:DI (plus:SI (ior:SI (plus:SI - (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "ua_offset" "I06")) - (const_int 7)) - (const_int -7))) - (plus:SI (and:SI (match_dup 0) (const_int 7)) (const_int 1)) - (const_int 0)) - (match_operand:DI 2 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0" - "#" - "" - [(pc)] -{ - emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]), - operands[2])); - DONE; -}) - -(define_insn_and_split "*sthi_q_comb1" - [(set (zero_extract:DI - (mem:DI (plus:SI (ior:SI (plus:SI - (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "ua_offset" "I06")) - (const_int 7)) - (const_int -7))) - (plus:SI (and:SI (plus:SI (match_dup 0) - (match_operand:SI 2 "ua_offset" "I06")) - (const_int 7)) - (const_int 1)) - (const_int 0)) - (match_operand:DI 3 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & -8) - && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])" - "#" - "" - [(pc)] -{ - emit_insn (gen_sthi_q (gen_rtx_PLUS (SImode, operands[0], operands[1]), - operands[3])); - DONE; -}) - -;; This is highpart user because the address is used as full 64 bit. -(define_insn "stlo_l" - [(set (zero_extract:SI - (mem:SI (and:SI (match_operand:QI 0 "ua_address_operand" "p") - (const_int -4))) - (minus:SI (const_int 4) (and:SI (match_dup 0) (const_int 3))) - (and:SI (match_dup 0) (const_int 3))) - (match_operand:SI 1 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA32" - "stlo.l %U0, %1" - [(set_attr "type" "ustore_media")]) - -(define_insn "stlo_q" - [(set (zero_extract:DI - (mem:DI (and:SI (match_operand:QI 0 "ua_address_operand" "p") - (const_int -8))) - (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7))) - (and:SI (match_dup 0) (const_int 7))) - (match_operand:DI 1 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA32" - "stlo.q %U0, %1" - [(set_attr "type" "ustore_media")]) - -(define_insn_and_split "*stlo_q_comb0" - [(set (zero_extract:DI - (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "ua_offset" "I06")) - (const_int -8))) - (minus:SI (const_int 8) (and:SI (match_dup 0) (const_int 7))) - (and:SI (match_dup 0) (const_int 7))) - (match_operand:DI 2 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == 0" - "#" - "" - [(pc)] -{ - emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]), - operands[2])); - DONE; -}) - -(define_insn_and_split "*stlo_q_comb1" - [(set (zero_extract:DI - (mem:DI (and:SI (plus:SI (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "ua_offset" "I06")) - (const_int -8))) - (minus:SI (const_int 8) - (and:SI (plus:SI (match_dup 0) - (match_operand:SI 2 "ua_offset" "I06")) - (const_int 7))) - (and:SI (plus:SI (match_dup 0) (match_dup 2)) (const_int 7))) - (match_operand:DI 3 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA32 && (INTVAL (operands[1]) & 7) == INTVAL (operands[2])" - "#" - "" - [(pc)] -{ - emit_insn (gen_stlo_q (gen_rtx_PLUS (SImode, operands[0], operands[1]), - operands[3])); - DONE; -}) - -(define_insn "ldhi_l64" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (zero_extract:SI - (mem:SI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p") - (const_int 3)) - (const_int -3))) - (plus:DI (and:DI (match_dup 1) (const_int 3)) (const_int 1)) - (const_int 0)))] - "TARGET_SHMEDIA64" - "ldhi.l %U1, %0" - [(set_attr "type" "load_media")]) - -(define_insn "ldhi_q64" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extract:DI - (mem:DI (plus:DI (ior:DI (match_operand:QI 1 "ua_address_operand" "p") - (const_int 7)) - (const_int -7))) - (plus:DI (and:DI (match_dup 1) (const_int 7)) (const_int 1)) - (const_int 0)))] - "TARGET_SHMEDIA64" - "ldhi.q %U1, %0" - [(set_attr "type" "load_media")]) - -(define_insn "ldlo_l64" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (zero_extract:SI - (mem:SI (and:DI (match_operand:QI 1 "ua_address_operand" "p") - (const_int -4))) - (minus:DI (const_int 4) (and:DI (match_dup 1) (const_int 3))) - (and:DI (match_dup 1) (const_int 3))))] - "TARGET_SHMEDIA64" - "ldlo.l %U1, %0" - [(set_attr "type" "load_media")]) - -(define_insn "ldlo_q64" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extract:DI - (mem:DI (and:DI (match_operand:QI 1 "ua_address_operand" "p") - (const_int -8))) - (minus:DI (const_int 8) (and:DI (match_dup 1) (const_int 7))) - (and:DI (match_dup 1) (const_int 7))))] - "TARGET_SHMEDIA64" - "ldlo.q %U1, %0" - [(set_attr "type" "load_media")]) - -(define_insn "sthi_l64" - [(set (zero_extract:SI - (mem:SI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p") - (const_int 3)) - (const_int -3))) - (plus:DI (and:DI (match_dup 0) (const_int 3)) (const_int 1)) - (const_int 0)) - (match_operand:SI 1 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA64" - "sthi.l %U0, %1" - [(set_attr "type" "ustore_media")]) - -(define_insn "sthi_q64" - [(set (zero_extract:DI - (mem:DI (plus:DI (ior:DI (match_operand:QI 0 "ua_address_operand" "p") - (const_int 7)) - (const_int -7))) - (plus:DI (and:DI (match_dup 0) (const_int 7)) (const_int 1)) - (const_int 0)) - (match_operand:DI 1 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA64" - "sthi.q %U0, %1" - [(set_attr "type" "ustore_media")]) - -(define_insn "stlo_l64" - [(set (zero_extract:SI - (mem:SI (and:DI (match_operand:QI 0 "ua_address_operand" "p") - (const_int -4))) - (minus:DI (const_int 4) (and:DI (match_dup 0) (const_int 3))) - (and:DI (match_dup 0) (const_int 3))) - (match_operand:SI 1 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA64" - "stlo.l %U0, %1" - [(set_attr "type" "ustore_media")]) - -(define_insn "stlo_q64" - [(set (zero_extract:DI - (mem:DI (and:DI (match_operand:QI 0 "ua_address_operand" "p") - (const_int -8))) - (minus:DI (const_int 8) (and:DI (match_dup 0) (const_int 7))) - (and:DI (match_dup 0) (const_int 7))) - (match_operand:DI 1 "arith_reg_operand" "r"))] - "TARGET_SHMEDIA64" - "stlo.q %U0, %1" - [(set_attr "type" "ustore_media")]) - -(define_insn "nsb" - [(set (match_operand:QI 0 "arith_reg_dest" "=r") - (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")] - UNSPEC_NSB))] - "TARGET_SHMEDIA" - "nsb %1, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "nsbsi" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (zero_extend:SI - (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")] - UNSPEC_NSB)))] - "TARGET_SHMEDIA" - "nsb %1, %0" - [(set_attr "type" "arith_media")]) - -(define_insn "nsbdi" - [(set (match_operand:DI 0 "arith_reg_dest" "=r") - (zero_extend:DI - (unspec:QI [(match_operand:DI 1 "arith_reg_operand" "r")] - UNSPEC_NSB)))] - "TARGET_SHMEDIA" - "nsb %1, %0" - [(set_attr "type" "arith_media")]) - -(define_expand "ffsdi2" - [(set (match_operand:DI 0 "arith_reg_dest" "") - (ffs:DI (match_operand:DI 1 "arith_reg_operand" "")))] - "TARGET_SHMEDIA" -{ - rtx scratch = gen_reg_rtx (DImode); - rtx last; - - emit_insn (gen_adddi3 (scratch, operands[1], constm1_rtx)); - emit_insn (gen_xordi3 (scratch, operands[1], scratch)); - emit_insn (gen_lshrdi3_media (scratch, scratch, const1_rtx)); - emit_insn (gen_nsbdi (scratch, scratch)); - emit_insn (gen_adddi3 (scratch, scratch, GEN_INT (-64))); - emit_insn (gen_movdicc_false (scratch, operands[1], const0_rtx, scratch)); - last = emit_insn (gen_subdi3 (operands[0], const0_rtx, scratch)); - set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (DImode, operands[0])); - - DONE; -}) - -(define_expand "ffssi2" - [(set (match_operand:SI 0 "arith_reg_dest" "") - (ffs:SI (match_operand:SI 1 "arith_reg_operand" "")))] - "TARGET_SHMEDIA" -{ - rtx scratch = gen_reg_rtx (SImode); - rtx discratch = gen_reg_rtx (DImode); - rtx last; - - emit_insn (gen_adddi3 (discratch, - simplify_gen_subreg (DImode, operands[1], SImode, 0), - constm1_rtx)); - emit_insn (gen_andcdi3 (discratch, - simplify_gen_subreg (DImode, operands[1], SImode, 0), - discratch)); - emit_insn (gen_nsbsi (scratch, discratch)); - last = emit_insn (gen_subsi3 (operands[0], - force_reg (SImode, GEN_INT (63)), scratch)); - set_unique_reg_note (last, REG_EQUAL, gen_rtx_FFS (SImode, operands[0])); - - DONE; -}) - -(define_insn "byterev" - [(set (match_operand:V8QI 0 "arith_reg_dest" "=r") - (vec_select:V8QI (match_operand:V8QI 1 "arith_reg_operand" "r") - (parallel [(const_int 7) (const_int 6) (const_int 5) - (const_int 4) (const_int 3) (const_int 2) - (const_int 1) (const_int 0)])))] - "TARGET_SHMEDIA" - "byterev %1, %0" - [(set_attr "type" "arith_media")]) - -;; In user mode, the "pref" instruction will raise a RADDERR exception -;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable -;; implementation of __builtin_prefetch for VxWorks RTPs. -(define_expand "prefetch" - [(prefetch (match_operand 0 "address_operand" "") - (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "const_int_operand" ""))] - "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5) - && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)") - -(define_insn "*prefetch" - [(prefetch (match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "const_int_operand" "n") - (match_operand:SI 2 "const_int_operand" "n"))] - "(TARGET_SH2A || TARGET_SH3 || TARGET_SHCOMPACT) && ! TARGET_VXWORKS_RTP" - "pref @%0" - [(set_attr "type" "other")]) - -(define_insn "*prefetch_media" - [(prefetch (match_operand:QI 0 "address_operand" "p") - (match_operand:SI 1 "const_int_operand" "n") - (match_operand:SI 2 "const_int_operand" "n"))] - "TARGET_SHMEDIA" -{ - operands[0] = gen_rtx_MEM (QImode, operands[0]); - output_asm_insn ("ld%M0.b %m0,r63", operands); - return ""; -} - [(set_attr "type" "other")]) - -(define_insn "alloco_i" - [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p")) - (unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))] - "TARGET_SHMEDIA32" -{ - rtx xops[2]; - - if (GET_CODE (operands[0]) == PLUS) - { - xops[0] = XEXP (operands[0], 0); - xops[1] = XEXP (operands[0], 1); - } - else - { - xops[0] = operands[0]; - xops[1] = const0_rtx; - } - output_asm_insn ("alloco %0, %1", xops); - return ""; -} - [(set_attr "type" "other")]) - -(define_split - [(set (match_operand 0 "any_register_operand" "") - (match_operand 1 "" ""))] - "TARGET_SHMEDIA && reload_completed" - [(set (match_dup 0) (match_dup 1))] -{ - if (!shmedia_cleanup_truncate (operands[1])) - FAIL; -}) - -;; ------------------------------------------------------------------------- -;; Stack Protector Patterns -;; ------------------------------------------------------------------------- - -(define_expand "stack_protect_set" - [(set (match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" ""))] - "" -{ - if (TARGET_SHMEDIA) - { - if (TARGET_SHMEDIA64) - emit_insn (gen_stack_protect_set_di_media (operands[0], operands[1])); - else - emit_insn (gen_stack_protect_set_si_media (operands[0], operands[1])); - } - else - emit_insn (gen_stack_protect_set_si (operands[0], operands[1])); - - DONE; -}) - -(define_insn "stack_protect_set_si" - [(set (match_operand:SI 0 "memory_operand" "=m") - (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) - (set (match_scratch:SI 2 "=&r") (const_int 0))] - "!TARGET_SHMEDIA" -{ - return "mov.l %1,%2" "\n" - " mov.l %2,%0" "\n" - " mov #0,%2"; -} - [(set_attr "type" "other") - (set_attr "length" "6")]) - -(define_insn "stack_protect_set_si_media" - [(set (match_operand:SI 0 "memory_operand" "=m") - (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) - (set (match_scratch:SI 2 "=&r") (const_int 0))] - "TARGET_SHMEDIA" -{ - return "ld%M1.l %m1,%2" "\n" - " st%M0.l %m0,%2" "\n" - " movi 0,%2"; -} - [(set_attr "type" "other") - (set_attr "length" "12")]) - -(define_insn "stack_protect_set_di_media" - [(set (match_operand:DI 0 "memory_operand" "=m") - (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET)) - (set (match_scratch:DI 2 "=&r") (const_int 0))] - "TARGET_SHMEDIA64" -{ - return "ld%M1.q %m1,%2" "\n" - " st%M0.q %m0,%2" "\n" - " movi 0,%2"; -} - [(set_attr "type" "other") - (set_attr "length" "12")]) + return "mov.l %1,%2" "\n" + " mov.l %2,%0" "\n" + " mov #0,%2"; +} + [(set_attr "type" "other") + (set_attr "length" "6")]) (define_expand "stack_protect_test" [(match_operand 0 "memory_operand" "") @@ -17301,31 +10912,8 @@ label: (match_operand 2 "" "")] "" { - if (TARGET_SHMEDIA) - { - rtx tmp = gen_reg_rtx (GET_MODE (operands[0])); - rtx test; - - test = gen_rtx_NE (VOIDmode, tmp, const0_rtx); - if (TARGET_SHMEDIA64) - { - emit_insn (gen_stack_protect_test_di_media (tmp, operands[0], - operands[1])); - emit_jump_insn (gen_cbranchdi4 (test, tmp, const0_rtx, operands[2])); - } - else - { - emit_insn (gen_stack_protect_test_si_media (tmp, operands[0], - operands[1])); - emit_jump_insn (gen_cbranchsi4 (test, tmp, const0_rtx, operands[2])); - } - } - else - { - emit_insn (gen_stack_protect_test_si (operands[0], operands[1])); - emit_jump_insn (gen_branch_true (operands[2])); - } - + emit_insn (gen_stack_protect_test_si (operands[0], operands[1])); + emit_jump_insn (gen_branch_true (operands[2])); DONE; }) @@ -17336,7 +10924,7 @@ label: UNSPEC_SP_TEST)) (set (match_scratch:SI 2 "=&r") (const_int 0)) (set (match_scratch:SI 3 "=&r") (const_int 0))] - "!TARGET_SHMEDIA" + "" { return "mov.l %0,%2" "\n" " mov.l %1,%3" "\n" @@ -17347,38 +10935,6 @@ label: [(set_attr "type" "other") (set_attr "length" "10")]) -(define_insn "stack_protect_test_si_media" - [(set (match_operand:SI 0 "register_operand" "=&r") - (unspec:SI [(match_operand:SI 1 "memory_operand" "m") - (match_operand:SI 2 "memory_operand" "m")] - UNSPEC_SP_TEST)) - (set (match_scratch:SI 3 "=&r") (const_int 0))] - "TARGET_SHMEDIA" -{ - return "ld%M1.l %m1,%0" "\n" - " ld%M2.l %m2,%3" "\n" - " cmpeq %0,%3,%0" "\n" - " movi 0,%3"; -} - [(set_attr "type" "other") - (set_attr "length" "16")]) - -(define_insn "stack_protect_test_di_media" - [(set (match_operand:DI 0 "register_operand" "=&r") - (unspec:DI [(match_operand:DI 1 "memory_operand" "m") - (match_operand:DI 2 "memory_operand" "m")] - UNSPEC_SP_TEST)) - (set (match_scratch:DI 3 "=&r") (const_int 0))] - "TARGET_SHMEDIA64" -{ - return "ld%M1.q %m1,%0" "\n" - " ld%M2.q %m2,%3" "\n" - " cmpeq %0,%3,%0" "\n" - " movi 0,%3"; -} - [(set_attr "type" "other") - (set_attr "length" "16")]) - ;; ------------------------------------------------------------------------- ;; Atomic operations ;; ------------------------------------------------------------------------- diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt index 1026c7346c5..a6b63dca6fa 100644 --- a/gcc/config/sh/sh.opt +++ b/gcc/config/sh/sh.opt @@ -37,9 +37,6 @@ Mask(HARD_SH2A_DOUBLE) ;; Set if compiling for SH4 hardware (to be used for insn costs etc.) Mask(HARD_SH4) -;; Set if we should generate code for a SH5 CPU (either ISA). -Mask(SH5) - ;; Set if we should save all target registers. Mask(SAVE_ALL_TARGET_REGS) @@ -180,30 +177,6 @@ m4al Target RejectNegative Condition(SUPPORT_SH4AL) Generate SH4al-dsp code. -m5-32media -Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) -Generate 32-bit SHmedia code. - -m5-32media-nofpu -Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) -Generate 32-bit FPU-less SHmedia code. - -m5-64media -Target RejectNegative Condition(SUPPORT_SH5_64MEDIA) -Generate 64-bit SHmedia code. - -m5-64media-nofpu -Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU) -Generate 64-bit FPU-less SHmedia code. - -m5-compact -Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) -Generate SHcompact code. - -m5-compact-nofpu -Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) -Generate FPU-less SHcompact code. - maccumulate-outgoing-args Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1) Reserve space for outgoing arguments in the function prologue. @@ -244,17 +217,13 @@ mcbranch-force-delay-slot Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0) Force the usage of delay slots for conditional branches. -mcut2-workaround -Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND) -Enable SH5 cut2 workaround. - mdalign Target Report RejectNegative Mask(ALIGN_DOUBLE) Align doubles at 64-bit boundaries. mdiv= Target RejectNegative Joined Var(sh_div_str) Init("") -Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table. +Division strategy, one of: call-div1, call-fp, call-table. mdivsi3_libfunc= Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") @@ -272,10 +241,6 @@ mfixed-range= Target RejectNegative Joined Var(sh_fixed_range_str) Specify range of registers to make fixed. -mgettrcost= -Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1) -Cost to assume for gettr insn. - mhitachi Target Report RejectNegative Mask(HITACHI) Follow Renesas (formerly Hitachi) / SuperH calling conventions. @@ -284,10 +249,6 @@ mieee Target Var(TARGET_IEEE) Increase the IEEE compliance for floating-point comparisons. -mindexed-addressing -Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA) -Enable the use of the indexed addressing mode for SHmedia32/SHcompact. - minline-ic_invalidate Target Report Var(TARGET_INLINE_IC_INVALIDATE) inline code to invalidate instruction cache entries after setting up nested function trampolines. @@ -318,10 +279,6 @@ mprefergot Target Report RejectNegative Mask(PREFERGOT) Emit function-calls using global offset table when generating PIC. -mpt-fixed -Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5) -Assume pt* instructions won't trap - mrelax Target Report RejectNegative Mask(RELAX) Shorten address references during linking. diff --git a/gcc/config/sh/sh64.h b/gcc/config/sh/sh64.h deleted file mode 100644 index 45e5a5cb499..00000000000 --- a/gcc/config/sh/sh64.h +++ /dev/null @@ -1,22 +0,0 @@ -/* Definitions of target machine for GNU compiler for SuperH SH 5. - Copyright (C) 2000-2016 Free Software Foundation, Inc. - Contributed by Alexandre Oliva - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -. */ - -#undef SH_ELF_WCHAR_TYPE -#define SH_ELF_WCHAR_TYPE "int" diff --git a/gcc/config/sh/shmedia.h b/gcc/config/sh/shmedia.h deleted file mode 100644 index 6337441a8bd..00000000000 --- a/gcc/config/sh/shmedia.h +++ /dev/null @@ -1,30 +0,0 @@ -/* Copyright (C) 2000-2016 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - -#ifndef _SHMEDIA_H -#define _SHMEDIA_H - -#include -#include - -#endif diff --git a/gcc/config/sh/shmedia.md b/gcc/config/sh/shmedia.md deleted file mode 100644 index f226113b59c..00000000000 --- a/gcc/config/sh/shmedia.md +++ /dev/null @@ -1,94 +0,0 @@ -;; DFA scheduling description for SH-5 SHmedia instructions. -;; Copyright (C) 2004-2016 Free Software Foundation, Inc. - -;; This file is part of GCC. - -;; GCC is free software; you can redistribute it and/or modify -;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 3, or (at your option) -;; any later version. - -;; GCC is distributed in the hope that it will be useful, -;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;; GNU General Public License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; . - -;; This is just a conversion of the old model using define_function_unit. - -;; When executing SHmedia code, the SH-5 is a fairly straightforward -;; single-issue machine. It has four pipelines, the branch unit (br), -;; the integer and multimedia unit (imu), the load/store unit (lsu), and -;; the floating point unit (fpu). - -(define_automaton "sh5inst_pipe, sh5fpu_pipe") - -(define_cpu_unit "sh5issue" "sh5inst_pipe") - -(define_cpu_unit "sh5fds" "sh5fpu_pipe") - -;; Every instruction on SH-5 occupies the issue resource for at least one -;; cycle. -(define_insn_reservation "shmedia1" 1 - (and (eq_attr "pipe_model" "sh5media") - (eq_attr "type" "!pt_media,ptabs_media,invalidate_line_media,dmpy_media,load_media,fload_media,fcmp_media,fmove_media,fparith_media,dfparith_media,fpconv_media,dfpconv_media,dfmul_media,store_media,fstore_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media")) - "sh5issue") - -;; Specify the various types of instruction which have latency > 1 -(define_insn_reservation "shmedia2" 2 - (and (eq_attr "pipe_model" "sh5media") - (eq_attr "type" "mcmp_media")) - "sh5issue") - -(define_insn_reservation "shmedia3" 3 - (and (eq_attr "pipe_model" "sh5media") - (eq_attr "type" "dmpy_media,load_media,fcmp_media,mac_media")) - "sh5issue") -;; but see sh_adjust_cost for mac_media exception. - -(define_insn_reservation "shmedia4" 4 - (and (eq_attr "pipe_model" "sh5media") - (eq_attr "type" "fload_media,fmove_media")) - "sh5issue") - -(define_insn_reservation "shmedia_d2mpy" 4 - (and (eq_attr "pipe_model" "sh5media") - (eq_attr "type" "d2mpy_media")) - "sh5issue*2") - -(define_insn_reservation "shmedia5" 5 - (and (eq_attr "pipe_model" "sh5media") - (eq_attr "type" "pt_media,ptabs_media")) - "sh5issue") - -(define_insn_reservation "shmedia6" 6 - (and (eq_attr "pipe_model" "sh5media") - (eq_attr "type" "fparith_media,dfparith_media,fpconv_media,dfpconv_media")) - "sh5issue") - -(define_insn_reservation "shmedia_invalidate" 7 - (and (eq_attr "pipe_model" "sh5media") - (eq_attr "type" "invalidate_line_media")) - "sh5issue*7") - -(define_insn_reservation "shmedia_dfmul" 9 - (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfmul_media")) - "sh5issue*4") - -(define_insn_reservation "shmedia_atrans" 10 - (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "atrans_media")) - "sh5issue*5") - -;; Floating-point divide and square-root occupy an additional resource, -;; which is not internally pipelined. However, other instructions -;; can continue to issue. -(define_insn_reservation "shmedia_fdiv" 19 - (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "fdiv_media")) - "sh5issue+sh5fds,sh5fds*18") - -(define_insn_reservation "shmedia_dfdiv" 35 - (and (eq_attr "pipe_model" "sh5media") (eq_attr "type" "dfdiv_media")) - "sh5issue+sh5fds,sh5fds*34") diff --git a/gcc/config/sh/sshmedia.h b/gcc/config/sh/sshmedia.h deleted file mode 100644 index 546ec3d211a..00000000000 --- a/gcc/config/sh/sshmedia.h +++ /dev/null @@ -1,78 +0,0 @@ -/* Copyright (C) 2000-2016 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - - -/* sshmedia.h: Intrinsics corresponding to SHmedia instructions that - may only be executed in privileged mode. */ - -#ifndef _SSHMEDIA_H -#define _SSHMEDIA_H - -#if __SHMEDIA__ -__inline__ static unsigned long long sh_media_GETCON (unsigned int k) - __attribute__((always_inline)); - -__inline__ static -unsigned long long -sh_media_GETCON (unsigned int k) -{ - unsigned long long res; - __asm__ __volatile__ ("getcon cr%1, %0" : "=r" (res) : "n" (k)); - return res; -} - -__inline__ static void sh_media_PUTCON (unsigned long long mm, unsigned int k) - __attribute__((always_inline)); - -__inline__ static -void -sh_media_PUTCON (unsigned long long mm, unsigned int k) -{ - __asm__ __volatile__ ("putcon %0, cr%1" : : "r" (mm), "n" (k)); -} - -__inline__ static -unsigned long long -sh_media_GETCFG (unsigned long long mm, int s) -{ - unsigned long long res; - __asm__ __volatile__ ("getcfg %1, %2, %0" : "=r" (res) : "r" (mm), "n" (s)); - return res; -} - -__inline__ static -void -sh_media_PUTCFG (unsigned long long mm, int s, unsigned long long mw) -{ - __asm__ __volatile__ ("putcfg %0, %1, %2" : : "r" (mm), "n" (s), "r" (mw)); -} - -__inline__ static -void -sh_media_SLEEP (void) -{ - __asm__ __volatile__ ("sleep"); -} -#endif - -#endif diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md index 6f1337b33b4..93007f94c9b 100644 --- a/gcc/config/sh/sync.md +++ b/gcc/config/sh/sync.md @@ -2131,7 +2131,7 @@ [(match_operand:SI 0 "register_operand" "") ;; bool result output (match_operand:QI 1 "memory_operand" "") ;; memory (match_operand:SI 2 "const_int_operand" "")] ;; model - "(TARGET_ATOMIC_ANY || TARGET_ENABLE_TAS) && !TARGET_SHMEDIA" + "TARGET_ATOMIC_ANY || TARGET_ENABLE_TAS" { rtx addr = force_reg (Pmode, XEXP (operands[1], 0)); @@ -2168,7 +2168,7 @@ (const_int 0))) (set (mem:QI (match_dup 0)) (unspec:QI [(const_int 128)] UNSPEC_ATOMIC))] - "TARGET_ENABLE_TAS && !TARGET_SHMEDIA" + "TARGET_ENABLE_TAS" "tas.b @%0" [(set_attr "insn_class" "co_group")]) diff --git a/gcc/config/sh/t-netbsd-sh5-64 b/gcc/config/sh/t-netbsd-sh5-64 deleted file mode 100644 index 8fc6bd1ea18..00000000000 --- a/gcc/config/sh/t-netbsd-sh5-64 +++ /dev/null @@ -1 +0,0 @@ -MULTILIB_DIRNAMES= $(MULTILIB_RAW_DIRNAMES:/media64=) diff --git a/gcc/config/sh/t-sh64 b/gcc/config/sh/t-sh64 deleted file mode 100644 index 3423b285cea..00000000000 --- a/gcc/config/sh/t-sh64 +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (C) 2002-2016 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# . - -MULTILIB_CPU_DIRS= $(ML_sh1) $(ML_sh2e) $(ML_sh2) $(ML_sh3e) $(ML_sh3) $(ML_sh4_nofpu) $(ML_sh4_single_only) $(ML_sh4_single) $(ML_sh4) $(ML_sh5_32media:m5-32media/=media32) $(ML_sh5_32media_nofpu:m5-32media-nofpu/=nofpu/media32) $(ML_sh5_compact:m5-compact/=compact) $(ML_sh5_compact_nofpu:m5-compact-nofpu/=nofpu/compact) $(ML_sh5_64media:m5-64media/=media64) $(ML_sh5_64media_nofpu:m5-64media-nofpu/=nofpu/media64) - -MULTILIB_RAW_DIRNAMES= $(MULTILIB_ENDIAN:/mb= mb) $(MULTILIB_CPU_DIRS:/=) -MULTILIB_DIRNAMES= $(MULTILIB_RAW_DIRNAMES) diff --git a/gcc/config/sh/ushmedia.h b/gcc/config/sh/ushmedia.h deleted file mode 100644 index 4be53afc6f1..00000000000 --- a/gcc/config/sh/ushmedia.h +++ /dev/null @@ -1,1091 +0,0 @@ -/* Copyright (C) 2000-2016 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -Under Section 7 of GPL version 3, you are granted additional -permissions described in the GCC Runtime Library Exception, version -3.1, as published by the Free Software Foundation. - -You should have received a copy of the GNU General Public License and -a copy of the GCC Runtime Library Exception along with this program; -see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -. */ - - -/* ushmedia.h: Intrinsics corresponding to SHmedia instructions that - may be executed in both user and privileged mode. */ - -#ifndef _USHMEDIA_H -#define _USHMEDIA_H - -#if __SHMEDIA__ -#if ! __SH4_NO_FPU -typedef float __GCC_FV __attribute__ ((vector_size (4 * sizeof (float)))); -typedef float __GCC_MTRX __attribute__ ((vector_size (16 * sizeof (float)))); -#endif - -static __inline unsigned long long -sh_media_MABS_L (unsigned long long mm) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_absv2si2 ((v2si) mm); -} - -static __inline unsigned long long -sh_media_MABS_W (unsigned long long mm) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_absv4hi2 ((v4hi) mm); -} - -static __inline unsigned long long -sh_media_MADD_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_addv2si3 ((v2si) mm, (v2si) mn); -} - -static __inline unsigned long long -sh_media_MADD_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_addv4hi3 ((v4hi) mm, (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MADDS_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_ssaddv2si3 ((v2si) mm, (v2si) mn); -} - -static __inline unsigned long long -sh_media_MADDS_UB (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_usaddv8qi3 ((v8qi) mm, (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MADDS_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_ssaddv4hi3 ((v4hi) mm, (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MCMPEQ_B (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MCMPEQ_B ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MCMPEQ_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_sh_media_MCMPEQ_L ((v2si) mm, - (v2si) mn); -} - -static __inline unsigned long long -sh_media_MCMPEQ_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MCMPEQ_W ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MCMPGT_UB (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MCMPGT_UB ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MCMPGT_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_sh_media_MCMPGT_L ((v2si) mm, - (v2si) mn); -} - -static __inline unsigned long long -sh_media_MCMPGT_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MCMPGT_W ((v4hi) mm, - (v4hi) mn); -} - -#define sh_media_MCMV __builtin_sh_media_MCMV - -static __inline unsigned long long -sh_media_MCNVS_LW (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - typedef unsigned int uv2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_sh_media_MCNVS_LW ((v2si) mm, - (uv2si) mn); -} - -static __inline unsigned long long -sh_media_MCNVS_WB (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MCNVS_WB ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MCNVS_WUB (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MCNVS_WUB ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MEXTR1 (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MEXTR1 ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MEXTR2 (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MEXTR2 ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MEXTR3 (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MEXTR3 ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MEXTR4 (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MEXTR4 ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MEXTR5 (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MEXTR5 ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MEXTR6 (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MEXTR6 ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MEXTR7 (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MEXTR7 ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MMACFX_WL (unsigned long long mm, unsigned long long mn, - unsigned long long mw) -{ - typedef float v2hi __attribute__ ((mode(V2HI))); - typedef float v2si __attribute__ ((mode(V2SI))); - typedef unsigned int uv2si __attribute__ ((mode(V2SI))); - - long mm_l = (long) mm; - long mn_l = (long) mn; - - return ((unsigned long long) - __builtin_sh_media_MMACFX_WL ((v2hi) mm_l, (v2hi) mn_l, - (uv2si) mw)); -} - -static __inline unsigned long long -sh_media_MMACNFX_WL (unsigned long long mm, unsigned long long mn, - unsigned long long mw) -{ - typedef float v2hi __attribute__ ((mode(V2HI))); - typedef float v2si __attribute__ ((mode(V2SI))); - typedef unsigned int uv2si __attribute__ ((mode(V2SI))); - - long mm_l = (long) mm; - long mn_l = (long) mn; - - return ((unsigned long long) - __builtin_sh_media_MMACNFX_WL ((v2hi) mm_l, (v2hi) mn_l, - (uv2si) mw)); -} - -static __inline unsigned long long -sh_media_MMUL_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_mulv2si3 ((v2si) mm, (v2si) mn); -} - -static __inline unsigned long long -sh_media_MMUL_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_mulv4hi3 ((v4hi) mm, (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MMULFX_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_sh_media_MMULFX_L ((v2si) mm, - (v2si) mn); -} - -static __inline unsigned long long -sh_media_MMULFX_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MMULFX_W ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MMULFXRP_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MMULFXRP_W ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MMULHI_WL (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MMULHI_WL ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MMULLO_WL (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MMULLO_WL ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MMULSUM_WQ (unsigned long long mm, unsigned long long mn, - unsigned long long mw) -{ - typedef unsigned int uv4hi __attribute__ ((mode(V4HI))); - - return __builtin_sh_media_MMULSUM_WQ ((uv4hi) mm, (uv4hi) mn, mw); -} - -static __inline unsigned long long -sh_media_MPERM_W (unsigned long long mm, unsigned int mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MPERM_W ((v4hi) mm, mn); -} - -static __inline unsigned long long -sh_media_MSAD_UBQ (unsigned long long mm, unsigned long long mn, - unsigned long long mw) -{ - typedef unsigned int uv8qi __attribute__ ((mode(V8QI))); - - return __builtin_sh_media_MSAD_UBQ ((uv8qi) mm, (uv8qi) mn, mw); -} - -static __inline unsigned long long -sh_media_MSHALDS_L (unsigned long long mm, unsigned int mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_sh_media_MSHALDS_L ((v2si) mm, mn); -} - -static __inline unsigned long long -sh_media_MSHALDS_W (unsigned long long mm, unsigned int mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MSHALDS_W ((v4hi) mm, mn); -} - -static __inline unsigned long long -sh_media_MSHARD_L (unsigned long long mm, unsigned int mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_ashrv2si3 ((v2si) mm, mn); -} - -static __inline unsigned long long -sh_media_MSHARD_W (unsigned long long mm, unsigned int mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_ashrv4hi3 ((v4hi) mm, mn); -} - -#define sh_media_MSHARDS_Q __builtin_sh_media_MSHARDS_Q - -static __inline unsigned long long -sh_media_MSHFHI_B (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MSHFHI_B ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MSHFHI_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_sh_media_MSHFHI_L ((v2si) mm, - (v2si) mn); -} - -static __inline unsigned long long -sh_media_MSHFHI_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MSHFHI_W ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MSHFLO_B (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_MSHFLO_B ((v8qi) mm, - (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MSHFLO_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_sh_media_MSHFLO_L ((v2si) mm, - (v2si) mn); -} - -static __inline unsigned long long -sh_media_MSHFLO_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sh_media_MSHFLO_W ((v4hi) mm, - (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MSHLLD_L (unsigned long long mm, unsigned int mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_ashlv2si3 ((v2si) mm, mn); -} - -static __inline unsigned long long -sh_media_MSHLLD_W (unsigned long long mm, unsigned int mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_ashlv4hi3 ((v4hi) mm, mn); -} - -static __inline unsigned long long -sh_media_MSHLRD_L (unsigned long long mm, unsigned int mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_lshrv2si3 ((v2si) mm, mn); -} - -static __inline unsigned long long -sh_media_MSHLRD_W (unsigned long long mm, unsigned int mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_lshrv4hi3 ((v4hi) mm, mn); -} - -static __inline unsigned long long -sh_media_MSUB_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_subv2si3 ((v2si) mm, (v2si) mn); -} - -static __inline unsigned long long -sh_media_MSUB_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_subv4hi3 ((v4hi) mm, (v4hi) mn); -} - -static __inline unsigned long long -sh_media_MSUBS_L (unsigned long long mm, unsigned long long mn) -{ - typedef float v2si __attribute__ ((mode(V2SI))); - - return (unsigned long long) __builtin_sssubv2si3 ((v2si) mm, (v2si) mn); -} - -static __inline unsigned long long -sh_media_MSUBS_UB (unsigned long long mm, unsigned long long mn) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_ussubv8qi3 ((v8qi) mm, (v8qi) mn); -} - -static __inline unsigned long long -sh_media_MSUBS_W (unsigned long long mm, unsigned long long mn) -{ - typedef float v4hi __attribute__ ((mode(V4HI))); - - return (unsigned long long) __builtin_sssubv4hi3 ((v4hi) mm, (v4hi) mn); -} - -#if ! __SH4_NOFPU__ -/* Floating-point Intrinsics */ - -#define sh_media_FABS_D __builtin_fabs -#define sh_media_FABS_S __builtin_fabsf -#define sh_media_FCMPUN_D __builtin_isunordered -#define sh_media_FCMPUN_S __builtin_isunordered - -static __inline float sh_media_FCOSA_S (float fg) -{ - union { int i; float f; } u; - - u.f = fg; - return __builtin_sh_media_FCOSA_S (u.i); -} - -static __inline float -sh_media_FGETSCR (void) -{ - float f; - - __asm volatile ("fgetscr %0" : "=f" (f)); - return f; -} - -static __inline float -sh_media_FIPR_S (const void *fvg, const void *fvh) -{ - typedef float v4sf __attribute__ ((mode(V4SF))); - v4sf vg = *(v4sf*) fvg; - v4sf vh = *(v4sf*) fvh; - - return __builtin_sh_media_FIPR_S (vg, vh); -} - -#if 0 -/* This gives different results for -O0 */ -static __inline float -sh_media_FMAC_S (float fg, float fh, float fq) -{ - return fg * fh + fq; -} -#else - -#define sh_media_FMAC_S __builtin_sh_media_FMAC_S -#endif - -static __inline long long -sh_media_FMOV_DQ (double dg) -{ - union { long long l; double d; } u; - - u.d = dg; - return u.l; -} - -static __inline float -sh_media_FMOV_LS (int mm) -{ - union { int i; float f; } u; - - u.i = mm; - return u.f; -} - -static __inline double -sh_media_FMOV_QD (long long mm) -{ - union { long long l; double d; } u; - - u.l = mm; - return u.d; -} - -static __inline int -sh_media_FMOV_SL (float fg) -{ - union { int i; float f; } u; - - u.f = fg; - return u.i; -} - -static __inline void -sh_media_FPUTSCR (float fg) -{ - __asm volatile ("fputscr %0" : : "f" (fg)); -} - -static __inline float sh_media_FSINA_S (float fg) -{ - union { int i; float f; } u; - - u.f = fg; - return __builtin_sh_media_FSINA_S (u.i); -} - -/* Can't use __builtin_sqrt / __builtin_sqrtf because they still implement - error handling unless -ffast-math is used. */ -#define sh_media_FSQRT_D __builtin_sh_media_FSQRT_D -#define sh_media_FSQRT_S __builtin_sh_media_FSQRT_S -#define sh_media_FSRRA_S __builtin_sh_media_FSRRA_S - -static __inline void -sh_media_FTRV_S (const void *mtrxg, const void *fvh, void *fvf) -{ - typedef float v16sf __attribute__ ((mode(V16SF))); - typedef float v4sf __attribute__ ((mode(V4SF))); - v16sf mtrx = *(v16sf*) mtrxg; - v4sf vh = *(v4sf*) fvh; - - *(v4sf*) fvf = __builtin_sh_media_FTRV_S (mtrx, vh); -} -#endif /* ! __SH4_NOFPU__ */ - -/* Not implemented here: Control and Configuration intrinsics. */ -/* Misaligned Access Support intrinsics */ - -static __inline unsigned long long -sh_media_LDHI_L (void *p, int s) -{ - return __builtin_sh_media_LDHI_L ((char *)p + s); -} - -static __inline unsigned long long -sh_media_LDHI_Q (void *p, int s) -{ - return __builtin_sh_media_LDHI_Q ((char *)p + s); -} - -static __inline unsigned long long -sh_media_LDLO_L (void *p, int s) -{ - return __builtin_sh_media_LDLO_L ((char *)p + s); -} - -static __inline unsigned long long -sh_media_LDLO_Q (void *p, int s) -{ - return __builtin_sh_media_LDLO_Q ((char *)p + s); -} - -static __inline void -sh_media_STHI_L (void *p, int s, unsigned int mw) -{ - __builtin_sh_media_STHI_L ((char*)p + s, mw); -} - -static __inline void -sh_media_STHI_Q (void *p, int s, unsigned long long mw) -{ - __builtin_sh_media_STHI_Q ((char*)p + s, mw); -} - -static __inline void -sh_media_STLO_L (void *p, int s, unsigned int mw) -{ - __builtin_sh_media_STLO_L ((char*)p + s, mw); -} - -static __inline void -sh_media_STLO_Q (void *p, int s, unsigned long long mw) -{ - __builtin_sh_media_STLO_Q ((char*)p + s, mw); -} - -/* Miscellaneous intrinsics */ - -#define sh_media_NSB __builtin_sh_media_NSB - -static __inline unsigned long long -sh_media_BYTEREV (unsigned long long mm) -{ - typedef float v8qi __attribute__ ((mode(V8QI))); - - return (unsigned long long) __builtin_sh_media_BYTEREV ((v8qi) mm); -} - -__inline__ static unsigned long long -sh_media_CMVEQ (unsigned long long mm, unsigned long long mn, unsigned long long mw) __attribute__ ((always_inline)); - -__inline__ static unsigned long long -sh_media_CMVEQ (unsigned long long mm, unsigned long long mn, unsigned long long mw) -{ - return mm == 0 ? mn : mw; -} - -__inline__ static unsigned long long -sh_media_CMVNE (unsigned long long mm, unsigned long long mn, unsigned long long mw) __attribute__ ((always_inline)); - -__inline__ static unsigned long long -sh_media_CMVNE (unsigned long long mm, unsigned long long mn, unsigned long long mw) -{ - return mm != 0 ? mn : mw; -} - -static __inline long long -sh_media_ADDZ_L (unsigned int mm, unsigned int mn) -{ - return mm + mn; -} - -/* NOP and Synchronization intrinsics not implemented here. */ - -static __inline__ void sh_media_PREFO(void *mm, int s) -{ - __builtin_sh_media_PREFO (mm + s, 0, 0); -} - -/* Event Handling intrinsics not implemented here. */ - -/* Old asm stuff */ - -static __inline__ -void -sh_media_NOP (void) -{ - __asm__ ("nop" : :); -} - -__inline__ static -unsigned long long -sh_media_SWAP_Q (void *mm, long long mn, unsigned long long mw) -{ - unsigned long long res; - unsigned long long *addr = (unsigned long long *)((char *)mm + mn); - __asm__ ("swap.q %m1, %0" : "=r" (res), "+o" (*addr) : "0" (mw)); - return res; -} - -__inline__ static -void -sh_media_SYNCI (void) -{ - __asm__ __volatile__ ("synci"); -} - -__inline__ static -void -sh_media_SYNCO (void) -{ - __asm__ __volatile__ ("synco"); -} - -__inline__ static -void -sh_media_ALLOCO (void *mm, int s) -{ - __builtin_sh_media_ALLOCO (mm + s); -} - -__inline__ static -void -sh_media_ICBI (void *mm, int s) -{ - __asm__ __volatile__ ("icbi %m0" : : "o" (((char*)mm)[s])); -} - -__inline__ static -void -sh_media_OCBI (void *mm, int s) -{ - __asm__ __volatile__ ("ocbi %m0" : : "o" (((char*)mm)[s])); -} - -__inline__ static -void -sh_media_OCBP (void *mm, int s) -{ - __asm__ __volatile__ ("ocbp %m0" : : "o" (((char*)mm)[s])); -} - -__inline__ static -void -sh_media_OCBWB (void *mm, int s) -{ - __asm__ __volatile__ ("ocbwb %m0" : : "o" (((char*)mm)[s])); -} - -__inline__ static -void -sh_media_PREFI (void *mm, int s) -{ - __asm__ __volatile__ ("prefi %m0" : : "o" (((char*)mm)[s])); -} - -__inline__ static -void -sh_media_BRK (void) -{ - __asm__ __volatile__ ("brk"); -} - -__inline__ static -void -sh_media_TRAPA (unsigned long long mm) -{ - __asm__ __volatile__ ("trapa %%0" : : "r" (mm)); -} - -__inline__ static -short -sh_media_unaligned_LD_W (void *p) -{ -#if __LITTLE_ENDIAN__ - return (((unsigned char *)p)[0] - | (((short)((__signed__ char *)p)[1]) << 8)); -#else - return ((((short)((__signed__ char *)p)[0]) << 8) - | ((unsigned char *)p)[1]); -#endif -} - -__inline__ static -unsigned short -sh_media_unaligned_LD_UW (void *p) -{ - unsigned char *addr = p; -#if __LITTLE_ENDIAN__ - return sh_media_MSHFLO_B (addr[0], addr[1]); -#else - return sh_media_MSHFLO_B (addr[1], addr[0]); -#endif -} - -/* We don't use the sh_media_LD* functions here because that turned out - to impede constant propagation of the offsets into the ldhi / ldlo - instructions. */ -__inline__ static -int -sh_media_unaligned_LD_L (void *p) -{ -#if __LITTLE_ENDIAN__ - return (__builtin_sh_media_LDHI_L ((char *)p + 3) - | __builtin_sh_media_LDLO_L (p)); -#else - return (__builtin_sh_media_LDLO_L ((char *)p + 3) - | __builtin_sh_media_LDHI_L (p)); -#endif -} - -__inline__ static -long long -sh_media_unaligned_LD_Q (void *p) -{ -#if __LITTLE_ENDIAN__ - return (__builtin_sh_media_LDHI_Q ((char *)p + 7) - | __builtin_sh_media_LDLO_Q (p)); -#else - return (__builtin_sh_media_LDLO_Q ((char *)p + 7) - | __builtin_sh_media_LDHI_Q (p)); -#endif -} - -__inline__ static -void -sh_media_unaligned_ST_W (void *p, unsigned int k) -{ - char *addr = p; -#if __LITTLE_ENDIAN__ - addr[0] = k; - addr[1] = k >> 8; -#else - addr[1] = k; - addr[0] = k >> 8; -#endif -} - -/* We don't use the sh_media_ST* functions here because that turned out - to impede constant propagation of the offsets into the ldhi / ldlo - instructions. */ -__inline__ static -void -sh_media_unaligned_ST_L (void *p, unsigned int k) -{ -#if __LITTLE_ENDIAN__ - __builtin_sh_media_STHI_L (p + 3, k); - __builtin_sh_media_STLO_L (p, k); -#else - __builtin_sh_media_STLO_L (p + 3, k); - __builtin_sh_media_STHI_L (p, k); -#endif -} - -__inline__ static -void -sh_media_unaligned_ST_Q (void *p, unsigned long long k) -{ -#if __LITTLE_ENDIAN__ - __builtin_sh_media_STHI_Q (p + 7, k); - __builtin_sh_media_STLO_Q (p, k); -#else - __builtin_sh_media_STLO_Q (p + 7, k); - __builtin_sh_media_STHI_Q (p, k); -#endif -} - -#if ! __SH4_NOFPU__ -__inline__ static -void -sh_media_FVCOPY_S (const void *fvg, void *fvf) -{ - const __GCC_FV *g = fvg; - __GCC_FV *f = fvf; - *f = *g; -} - -__inline__ static -void -sh_media_FVADD_S (const void *fvg, const void *fvh, void *fvf) -{ - const float *g = fvg, *h = fvh; - float *f = fvf; -#if 1 - int i; - - for (i = 0; i < 4; i++) - f[i] = g[i] + h[i]; -#else - f[0] = g[0] + h[0]; - f[1] = g[1] + h[1]; - f[2] = g[2] + h[2]; - f[3] = g[3] + h[3]; -#endif -} - -__inline__ static -void -sh_media_FVSUB_S (const void *fvg, const void *fvh, void *fvf) -{ - const float *g = fvg, *h = fvh; - float *f = fvf; -#if 1 - int i; - - for (i = 0; i < 4; i++) - f[i] = g[i] - h[i]; -#else - f[0] = g[0] - h[0]; - f[1] = g[1] - h[1]; - f[2] = g[2] - h[2]; - f[3] = g[3] - h[3]; -#endif -} - -__inline__ static -void -sh_media_FMTRXCOPY_S (const void *mtrxg, void *mtrxf) -{ - const __GCC_MTRX *g = mtrxg; - __GCC_MTRX *f = mtrxf; - *f = *g; -} - -__inline__ static -void -sh_media_FMTRXADD_S (const void *mtrxg, const void *mtrxh, void *mtrxf) -{ - const __GCC_FV *g = mtrxg, *h = mtrxh; - __GCC_FV *f = mtrxf; -#if 1 - int i; - - for (i = 0; i < 4; i++) - sh_media_FVADD_S (&g[i], &h[i], &f[i]); -#else - sh_media_FVADD_S (&g[0], &h[0], &f[0]); - sh_media_FVADD_S (&g[1], &h[1], &f[1]); - sh_media_FVADD_S (&g[2], &h[2], &f[2]); - sh_media_FVADD_S (&g[3], &h[3], &f[3]); -#endif -} - -__inline__ static -void -sh_media_FMTRXSUB_S (const void *mtrxg, const void *mtrxh, void *mtrxf) -{ - const __GCC_FV *g = mtrxg, *h = mtrxh; - __GCC_FV *f = mtrxf; -#if 1 - int i; - - for (i = 0; i < 4; i++) - sh_media_FVSUB_S (&g[i], &h[i], &f[i]); -#else - sh_media_FVSUB_S (&g[0], &h[0], &f[0]); - sh_media_FVSUB_S (&g[1], &h[1], &f[1]); - sh_media_FVSUB_S (&g[2], &h[2], &f[2]); - sh_media_FVSUB_S (&g[3], &h[3], &f[3]); -#endif -} - -__inline__ static -void -sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi, - void *fvf) -{ - sh_media_FTRV_S (mtrxg, fvh, fvf); - sh_media_FVADD_S (fvf, fvi, fvf); -} - -__inline__ static -void -sh_media_FTRVSUB_S (const void *mtrxg, const void *fvh, const void *fvi, - void *fvf) -{ - sh_media_FTRV_S (mtrxg, fvh, fvf); - sh_media_FVSUB_S (fvf, fvi, fvf); -} - -__inline__ static -void -sh_media_FMTRXMUL_S (const void *mtrxg, const void *mtrxh, void *mtrxf) -{ - const __GCC_FV *g = mtrxg; - __GCC_FV *f = mtrxf; -#if 1 - int j; - - for (j = 0; j < 4; j++) - sh_media_FTRV_S (mtrxh, &g[j], &f[j]); -#else - sh_media_FTRV_S (mtrxh, &g[0], &f[0]); - sh_media_FTRV_S (mtrxh, &g[1], &f[1]); - sh_media_FTRV_S (mtrxh, &g[2], &f[2]); - sh_media_FTRV_S (mtrxh, &g[3], &f[3]); -#endif -} - -__inline__ static -void -sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh, - const void *mtrxi, void *mtrxf) -{ - const __GCC_FV *g = mtrxg, *i = mtrxi; - __GCC_FV *f = mtrxf; -#if 1 - int j; - - for (j = 0; j < 4; j++) - sh_media_FTRVADD_S (mtrxh, &g[j], &i[j], &f[j]); -#else - sh_media_FTRVADD_S (mtrxh, &g[0], &i[0], &f[0]); - sh_media_FTRVADD_S (mtrxh, &g[1], &i[1], &f[1]); - sh_media_FTRVADD_S (mtrxh, &g[2], &i[2], &f[2]); - sh_media_FTRVADD_S (mtrxh, &g[3], &i[3], &f[3]); -#endif -} - -__inline__ static -void -sh_media_FMTRXMULSUB_S (const void *mtrxg, const void *mtrxh, - const void *mtrxi, void *mtrxf) -{ - const __GCC_FV *g = mtrxg, *i = mtrxi; - __GCC_FV *f = mtrxf; -#if 1 - int j; - - for (j = 0; j < 4; j++) - sh_media_FTRVSUB_S (mtrxh, &g[j], &i[j], &f[j]); -#else - sh_media_FTRVSUB_S (mtrxh, &g[0], &i[0], &f[0]); - sh_media_FTRVSUB_S (mtrxh, &g[1], &i[1], &f[1]); - sh_media_FTRVSUB_S (mtrxh, &g[2], &i[2], &f[2]); - sh_media_FTRVSUB_S (mtrxh, &g[3], &i[3], &f[3]); -#endif -} -#endif /* ! __SH4_NOFPU__ */ - -#endif /* __SHMEDIA__ */ - -#endif /* _USHMEDIA_H */ -- 2.30.2