From e2008dcc4f78c654520c3d8c28c46e48b59f0e7e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 15 May 2023 20:47:02 +0100 Subject: [PATCH] found the location to cut/paste the disassembly extra from https://bugs.libre-soc.org/show_bug.cgi?id=1084 --- src/openpower/decoder/power_insn.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 9774b6c4..3a4bee10 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1493,12 +1493,12 @@ class ConditionRegisterFieldOperand(ExtendableOperand): yield f"{indent}{indent}{int(value):0{value.bits}b}" yield f"{indent}{indent}{', '.join(span)}" if isinstance(insn, SVP64Instruction): - extra_idx = self.extra_idx - if self.record.etype is _SVEType.NONE: - yield f"{indent}{indent}extra[none]" - else: - etype = repr(self.record.etype).lower() - yield f"{indent}{indent}{etype}{extra_idx!r}" + for extra_idx in frozenset(self.extra_idx): + if self.record.etype is _SVEType.NONE: + yield f"{indent}{indent}extra[none]" + else: + etype = repr(self.record.etype).lower() + yield f"{indent}{indent}{etype}{extra_idx!r}" else: vector = "*" if vector else "" CR = int(value >> 2) -- 2.30.2