From e2176cefc2ac7b0916eaf25a3f0ddebdcfbae212 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 11 May 2020 22:39:17 +0200 Subject: [PATCH] soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters. --- litex/soc/integration/soc.py | 4 ++-- litex/soc/integration/soc_core.py | 27 +++++++++++---------------- 2 files changed, 13 insertions(+), 18 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index c6cc1e0f..64819fca 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -758,8 +758,8 @@ class SoC(Module): def add_csr_bridge(self, origin): self.submodules.csr_bridge = wishbone2csr.WB2CSR( bus_csr = csr_bus.Interface( - address_width = self.csr.address_width, - data_width = self.csr.data_width)) + address_width = self.csr.address_width, + data_width = self.csr.data_width)) csr_size = 2**(self.csr.address_width + 2) csr_region = SoCRegion(origin=origin, size=csr_size, cached=False) self.bus.add_slave("csr", self.csr_bridge.wishbone, csr_region) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index f61555a3..68499ad2 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -61,6 +61,11 @@ class SoCCore(LiteXSoC): } def __init__(self, platform, clk_freq, + # Bus parameters + bus_standard = "wishbone", + bus_data_width = 32, + bus_address_width = 32, + bus_timeout = 1e6, # CPU parameters cpu_type = "vexriscv", cpu_reset_address = None, @@ -92,18 +97,15 @@ class SoCCore(LiteXSoC): with_timer = True, # Controller parameters with_ctrl = True, - # Wishbone parameters - with_wishbone = True, - wishbone_timeout_cycles = 1e6, # Others **kwargs): # New LiteXSoC class ---------------------------------------------------------------------------- LiteXSoC.__init__(self, platform, clk_freq, - bus_standard = "wishbone", - bus_data_width = 32, - bus_address_width = 32, - bus_timeout = wishbone_timeout_cycles, + bus_standard = bus_standard, + bus_data_width = bus_data_width, + bus_address_width = bus_address_width, + bus_timeout = bus_timeout, bus_reserved_regions = {}, csr_data_width = csr_data_width, @@ -127,9 +129,6 @@ class SoCCore(LiteXSoC): cpu_reset_address = None if cpu_reset_address == "None" else cpu_reset_address cpu_variant = cpu.check_format_cpu_variant(cpu_variant) - if not with_wishbone: - self.mem_map["csr"] = 0x00000000 - self.cpu_type = cpu_type self.cpu_variant = cpu_variant self.cpu_cls = cpu_cls @@ -141,9 +140,6 @@ class SoCCore(LiteXSoC): self.csr_data_width = csr_data_width - self.with_wishbone = with_wishbone - self.wishbone_timeout_cycles = wishbone_timeout_cycles - self.wb_slaves = {} # Modules instances ------------------------------------------------------------------------ @@ -187,9 +183,8 @@ class SoCCore(LiteXSoC): if with_timer: self.add_timer(name="timer0") - # Add Wishbone to CSR bridge - if with_wishbone: - self.add_csr_bridge(self.mem_map["csr"]) + # Add CSR bridge + self.add_csr_bridge(self.mem_map["csr"]) # Methods -------------------------------------------------------------------------------------- -- 2.30.2